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https://gitee.com/seekfree/TC264_Library.git
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V1.1.10
修复通过#pragma section all "cpux_dsram"指定变量位置失效的问题
This commit is contained in:
SEEKFREE_Kang
@@ -1,70 +1,74 @@
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/**
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/**********************************************************************************************************************
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* \file Lcf_Tasking_Tricore_Tc.lsl
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* \brief Linker command file for Tasking compiler.
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*
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* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
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*
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*
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*
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* IMPORTANT NOTICE
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*
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*
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* Infineon Technologies AG (Infineon) is supplying this file for use
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* exclusively with Infineon's microcontroller products. This file can be freely
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* distributed within development tools that are supporting such microcontroller
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* products.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
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* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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*/
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* \copyright Copyright (C) Infineon Technologies AG 2019
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*
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* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
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* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
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* are agreed, use of this file is subject to following:
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*
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* Boost Software License - Version 1.0 - August 17th, 2003
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*
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* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
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* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
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* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
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* Software is furnished to do so, all subject to the following:
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*
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* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
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* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
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* derivative works of the Software, unless such copies or derivative works are solely in the form of
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* machine-executable object code generated by a source language processor.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
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* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
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* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*********************************************************************************************************************/
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#define LCF_CSA0_SIZE 8k
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#define LCF_USTACK0_SIZE 2k
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#define LCF_ISTACK0_SIZE 1k
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#define LCF_CSA0_SIZE 8k
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#define LCF_USTACK0_SIZE 2k
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#define LCF_ISTACK0_SIZE 1k
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#define LCF_CSA1_SIZE 8k
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#define LCF_USTACK1_SIZE 2k
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#define LCF_ISTACK1_SIZE 1k
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#define LCF_CSA1_SIZE 8k
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#define LCF_USTACK1_SIZE 2k
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#define LCF_ISTACK1_SIZE 1k
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#define LCF_HEAP_SIZE 2k
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#define LCF_HEAP_SIZE 2k
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#define LCF_CPU0 0
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#define LCF_CPU1 1
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#define LCF_CPU0 0
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#define LCF_CPU1 1
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/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
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/*#define LCF_DEFAULT_HOST LCF_CPU0*/
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#define LCF_DEFAULT_HOST LCF_CPU1
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/*#define LCF_DEFAULT_HOST LCF_CPU0*/
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#define LCF_DEFAULT_HOST LCF_CPU1
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#define LCF_DSPR1_START 0x60000000
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#define LCF_DSPR1_SIZE 120k
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#define LCF_DSPR1_START 0x60000000
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#define LCF_DSPR1_SIZE 120k
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#define LCF_DSPR0_START 0x70000000
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#define LCF_DSPR0_SIZE 72k
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#define LCF_DSPR0_START 0x70000000
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#define LCF_DSPR0_SIZE 72k
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#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
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#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
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#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
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#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
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#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
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#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
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#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
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#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
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#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
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#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
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#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
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#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
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#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
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#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
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#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
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#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
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#define LCF_INTVEC0_START 0x800F4000
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#define LCF_TRAPVEC0_START 0x80000100
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#define LCF_TRAPVEC1_START 0x800F6000
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#define LCF_INTVEC0_START 0x800F4000
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#define LCF_TRAPVEC0_START 0x80000100
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#define LCF_TRAPVEC1_START 0x800F6000
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#define INTTAB0 (LCF_INTVEC0_START)
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#define TRAPTAB0 (LCF_TRAPVEC0_START)
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#define TRAPTAB1 (LCF_TRAPVEC1_START)
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#define INTTAB0 (LCF_INTVEC0_START)
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#define TRAPTAB0 (LCF_TRAPVEC0_START)
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#define TRAPTAB1 (LCF_TRAPVEC1_START)
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#define RESET 0x80000020
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#define RESET 0x80000020
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#include "tc1v1_6_x.lsl"
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@@ -72,398 +76,374 @@
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processor mpe
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{
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derivative = tc26;
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derivative = tc26B;
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}
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derivative tc26
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derivative tc26B
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{
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core tc0
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{
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architecture = TC1V1.6.X;
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space_id_offset = 100; // add 100 to all space IDs in the architecture definition
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copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
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}
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core tc1 // core 1 TC16E
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{
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architecture = TC1V1.6.X;
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space_id_offset = 200; // add 200 to all space IDs in the architecture definition
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copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
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}
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core vtc
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{
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architecture = TC1V1.6.X;
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import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
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import tc1; // tc1
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}
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bus sri
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{
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mau = 8;
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width = 32;
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// map shared addresses one-to-one to real cores and virtual cores
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map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
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map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
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map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
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}
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memory dsram1 // Data Scratch Pad Ram
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{
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mau = 8;
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size = 120k;
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type = ram;
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map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
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map (dest=bus:sri, dest_offset=0x60000000, size=120k);
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}
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memory psram1 // Program Scratch Pad Ram
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{
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mau = 8;
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size = 32k;
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type = ram;
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map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
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map (dest=bus:sri, dest_offset=0x60100000, size=32k);
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}
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memory dsram0 // Data Scratch Pad Ram
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{
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mau = 8;
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size = 72k;
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type = ram;
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map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
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map (dest=bus:sri, dest_offset=0x70000000, size=72k);
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}
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memory psram0 // Program Scratch Pad Ram
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{
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mau = 8;
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size = 16k;
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type = ram;
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map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
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map (dest=bus:sri, dest_offset=0x70100000, size=16k);
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}
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memory pfls0
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{
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mau = 8;
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size = 1536K;
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type = rom;
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map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
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map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
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}
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memory dfls0
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{
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mau = 8;
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size = 1m+16k;
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type = reserved nvram;
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map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
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}
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memory lmuram
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{
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mau = 8;
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size = 32k;
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type = ram;
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priority = 2;
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map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
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map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
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}
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memory edmem
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{
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mau = 8;
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size = 1M;
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type = ram;
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map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
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map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
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}
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core tc0
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{
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architecture = TC1V1.6.X;
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space_id_offset = 100; // add 100 to all space IDs in the architecture definition
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copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
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}
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core tc1 // core 1 TC16E
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{
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architecture = TC1V1.6.X;
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space_id_offset = 200; // add 200 to all space IDs in the architecture definition
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copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
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}
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core vtc
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{
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architecture = TC1V1.6.X;
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import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
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import tc1; // tc1
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}
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bus sri
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{
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mau = 8;
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width = 32;
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// map shared addresses one-to-one to real cores and virtual cores
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map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
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map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
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map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
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}
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memory dsram1 // Data Scratch Pad Ram
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{
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mau = 8;
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size = 120k;
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type = ram;
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map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
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map (dest=bus:sri, dest_offset=0x60000000, size=120k);
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}
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memory psram1 // Program Scratch Pad Ram
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{
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mau = 8;
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size = 32k;
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type = ram;
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map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
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map (dest=bus:sri, dest_offset=0x60100000, size=32k);
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}
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memory dsram0 // Data Scratch Pad Ram
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{
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mau = 8;
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size = 72k;
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type = ram;
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map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
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map (dest=bus:sri, dest_offset=0x70000000, size=72k);
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}
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memory psram0 // Program Scratch Pad Ram
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{
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mau = 8;
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size = 16k;
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type = ram;
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map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
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map (dest=bus:sri, dest_offset=0x70100000, size=16k);
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}
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memory pfls0
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{
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mau = 8;
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size = 1M;
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type = rom;
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map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
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map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
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}
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memory pfls1
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{
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mau = 8;
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size = 1536K;
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type = rom;
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map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
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map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
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}
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memory dfls0
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{
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mau = 8;
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size = 1m+16k;
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type = reserved nvram;
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map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
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}
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memory edmem
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{
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mau = 8;
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size = 512K;
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type = ram;
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map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
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map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
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}
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#if (__VERSION__ >= 6003)
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#if (__VERSION__ >= 6003)
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section_setup :vtc:linear
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{
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heap "heap" (min_size = (1k), fixed, align = 8);
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}
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#endif
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section_setup :vtc:linear
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{
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start_address
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(
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symbol = "_START"
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);
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}
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|
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section_setup :vtc:linear
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{
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stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
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stack "istack_tc0" (min_size = 1k, fixed, align = 8);
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stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
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stack "istack_tc1" (min_size = 1k, fixed, align = 8);
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}
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|
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/*Section setup for the copy table*/
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section_setup :vtc:linear
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{
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copytable
|
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(
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align = 4,
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dest = linear,
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table
|
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{
|
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symbol = "_lc_ub_table_tc0";
|
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space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
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},
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table
|
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{
|
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symbol = "_lc_ub_table_tc1";
|
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space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
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}
|
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);
|
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}
|
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|
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/*Near data sections*/
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section_layout :vtc:abs18
|
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{
|
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group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
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{
|
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select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
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select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
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}
|
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|
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group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
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{
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select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
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select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
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}
|
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# if LCF_DEFAULT_HOST == LCF_CPU1
|
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group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
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# endif
|
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# if LCF_DEFAULT_HOST == LCF_CPU0
|
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group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
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# endif
|
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{
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select "(.zdata|.zdata*)";
|
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select "(.zbss|.zbss*)";
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}
|
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}
|
||||
|
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section_setup :vtc:linear
|
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{
|
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start_address
|
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(
|
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symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
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stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
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stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,374 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,374 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,374 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,374 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,374 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,374 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,374 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,374 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,374 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,374 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,374 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,374 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -20,7 +20,7 @@
|
||||
#include "headfile.h"
|
||||
#pragma section all "cpu1_dsram"
|
||||
|
||||
|
||||
uint8 test_arry1[5]; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
|
||||
void core1_main(void)
|
||||
@@ -29,7 +29,7 @@ void core1_main(void)
|
||||
IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
|
||||
|
||||
//<2F>û<EFBFBD><C3BB>ڴ˴<DAB4><CBB4><EFBFBD><EFBFBD>ø<EFBFBD><C3B8>ֳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
test_arry1[0] = 1;
|
||||
enableInterrupts();
|
||||
while (TRUE)
|
||||
{
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,374 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,374 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user