mirror of
https://gitee.com/seekfree/TC264_Library.git
synced 2026-06-04 03:32:56 +00:00
V1.0.1
对总钻风摄像头的场中断进行修改,判断标志位为0才采集下一幅图像,避免出现访问冲突 修改SPI初始化中的错误,引用了固定的SPI2基地址 修复STM中无法使用STM1的问题 修复gtm pwm中最大占空比只有GTM_ATOM0_PWM_DUTY_MAX设置有效的问题
This commit is contained in:
@@ -1,2 +1,9 @@
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V1.0.0
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<20><>ʼ<EFBFBD>汾
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<20><>ʼ<EFBFBD>汾
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V1.0.1
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<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
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<09><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
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<09><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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<09><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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@@ -281,7 +281,15 @@ void gtm_pwm_init(ATOM_PIN_enum pwmch, uint32 freq, uint32 duty)
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g_atomConfig.synchronousUpdateEnabled = TRUE;
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g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX);
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IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
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switch(atom_channel->atom)
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{
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case 0: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX); break;
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case 1: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM1_PWM_DUTY_MAX); break;
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case 2: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM2_PWM_DUTY_MAX); break;
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case 3: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM3_PWM_DUTY_MAX); break;
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}
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IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
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IfxGtm_Atom_Pwm_start(&g_atomDriver, TRUE);
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}
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@@ -279,7 +279,7 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
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moudle = IfxQspi_getAddress((IfxQspi_Index)spi_n);
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bacon.U = MODULE_QSPI2.BACON.U;
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bacon.U = moudle->BACON.U;
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bacon.B.DL = 7;
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bacon.B.IDLE = 1;
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@@ -300,11 +300,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
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i = 0;
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while(i < (len-1))
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{
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while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
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while(moudle->STATUS.B.TXFIFOLEVEL != 0);
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IfxQspi_write8(moudle, IfxQspi_ChannelId_0, modata, 1);
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while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
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while(moudle->STATUS.B.RXFIFOLEVEL == 0);
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if(NULL != midata) IfxQspi_read8(moudle,midata,1);
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else (void)MODULE_QSPI2.RXEXIT.U;
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else (void)moudle->RXEXIT.U;
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modata++;
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midata++;
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i++;
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@@ -314,11 +314,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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if(continuous) IfxQspi_writeBasicConfigurationEndStream(moudle, bacon.U);
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IfxQspi_writeTransmitFifo(moudle, *modata);
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while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
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while(moudle->STATUS.B.TXFIFOLEVEL != 0);
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while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
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while(moudle->STATUS.B.RXFIFOLEVEL == 0);
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if(NULL != midata) IfxQspi_read8(moudle,midata,1);
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else (void)MODULE_QSPI2.RXEXIT.U;
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else (void)moudle->RXEXIT.U;
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}
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@@ -35,7 +35,7 @@ void systick_delay(STMN_enum stmn, uint32 time)
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uint32 stm_clk;
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stm_clk = IfxStm_getFrequency(IfxStm_getAddress((IfxStm_Index)stmn));
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IfxStm_waitTicks(&MODULE_STM0, (uint32)((uint64)stm_clk*time/1000000000));
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IfxStm_waitTicks(IfxStm_getAddress((IfxStm_Index)stmn), (uint32)((uint64)stm_clk*time/1000000000));
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}
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@@ -325,8 +325,12 @@ void mt9v03x_vsync(void)
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{
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CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
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now_col = 0;
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DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
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dma_start(MT9V03X_DMA_CH);
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if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
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{
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DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
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dma_start(MT9V03X_DMA_CH);
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}
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}
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@@ -1,2 +1,9 @@
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V1.0.0
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<20><>ʼ<EFBFBD>汾
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<20><>ʼ<EFBFBD>汾
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V1.0.1
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<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
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<09><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
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<09><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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<09><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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@@ -281,7 +281,15 @@ void gtm_pwm_init(ATOM_PIN_enum pwmch, uint32 freq, uint32 duty)
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g_atomConfig.synchronousUpdateEnabled = TRUE;
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g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX);
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IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
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switch(atom_channel->atom)
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{
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case 0: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX); break;
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case 1: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM1_PWM_DUTY_MAX); break;
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case 2: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM2_PWM_DUTY_MAX); break;
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case 3: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM3_PWM_DUTY_MAX); break;
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}
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IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
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IfxGtm_Atom_Pwm_start(&g_atomDriver, TRUE);
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}
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@@ -279,7 +279,7 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
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moudle = IfxQspi_getAddress((IfxQspi_Index)spi_n);
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bacon.U = MODULE_QSPI2.BACON.U;
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bacon.U = moudle->BACON.U;
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bacon.B.DL = 7;
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bacon.B.IDLE = 1;
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@@ -300,11 +300,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
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i = 0;
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while(i < (len-1))
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{
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while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
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while(moudle->STATUS.B.TXFIFOLEVEL != 0);
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IfxQspi_write8(moudle, IfxQspi_ChannelId_0, modata, 1);
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while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
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while(moudle->STATUS.B.RXFIFOLEVEL == 0);
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if(NULL != midata) IfxQspi_read8(moudle,midata,1);
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else (void)MODULE_QSPI2.RXEXIT.U;
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else (void)moudle->RXEXIT.U;
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modata++;
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midata++;
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i++;
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@@ -314,11 +314,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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if(continuous) IfxQspi_writeBasicConfigurationEndStream(moudle, bacon.U);
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IfxQspi_writeTransmitFifo(moudle, *modata);
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while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
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while(moudle->STATUS.B.TXFIFOLEVEL != 0);
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while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
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while(moudle->STATUS.B.RXFIFOLEVEL == 0);
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if(NULL != midata) IfxQspi_read8(moudle,midata,1);
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else (void)MODULE_QSPI2.RXEXIT.U;
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else (void)moudle->RXEXIT.U;
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}
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@@ -35,7 +35,7 @@ void systick_delay(STMN_enum stmn, uint32 time)
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uint32 stm_clk;
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stm_clk = IfxStm_getFrequency(IfxStm_getAddress((IfxStm_Index)stmn));
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IfxStm_waitTicks(&MODULE_STM0, (uint32)((uint64)stm_clk*time/1000000000));
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IfxStm_waitTicks(IfxStm_getAddress((IfxStm_Index)stmn), (uint32)((uint64)stm_clk*time/1000000000));
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}
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@@ -325,8 +325,12 @@ void mt9v03x_vsync(void)
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{
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CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
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now_col = 0;
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DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
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dma_start(MT9V03X_DMA_CH);
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if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
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{
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DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
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dma_start(MT9V03X_DMA_CH);
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}
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}
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@@ -1,2 +1,9 @@
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V1.0.0
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<20><>ʼ<EFBFBD>汾
|
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<20><>ʼ<EFBFBD>汾
|
||||
|
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|
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V1.0.1
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
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<09><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
|
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<09><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
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<09><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
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@@ -281,7 +281,15 @@ void gtm_pwm_init(ATOM_PIN_enum pwmch, uint32 freq, uint32 duty)
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g_atomConfig.synchronousUpdateEnabled = TRUE;
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g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX);
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IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
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switch(atom_channel->atom)
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{
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case 0: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX); break;
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case 1: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM1_PWM_DUTY_MAX); break;
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case 2: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM2_PWM_DUTY_MAX); break;
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case 3: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM3_PWM_DUTY_MAX); break;
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}
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IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
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IfxGtm_Atom_Pwm_start(&g_atomDriver, TRUE);
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}
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@@ -279,7 +279,7 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
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moudle = IfxQspi_getAddress((IfxQspi_Index)spi_n);
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bacon.U = MODULE_QSPI2.BACON.U;
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bacon.U = moudle->BACON.U;
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bacon.B.DL = 7;
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bacon.B.IDLE = 1;
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@@ -300,11 +300,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
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i = 0;
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while(i < (len-1))
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{
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while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
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while(moudle->STATUS.B.TXFIFOLEVEL != 0);
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IfxQspi_write8(moudle, IfxQspi_ChannelId_0, modata, 1);
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while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
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while(moudle->STATUS.B.RXFIFOLEVEL == 0);
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if(NULL != midata) IfxQspi_read8(moudle,midata,1);
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else (void)MODULE_QSPI2.RXEXIT.U;
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else (void)moudle->RXEXIT.U;
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modata++;
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midata++;
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i++;
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@@ -314,11 +314,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
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if(continuous) IfxQspi_writeBasicConfigurationEndStream(moudle, bacon.U);
|
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IfxQspi_writeTransmitFifo(moudle, *modata);
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while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
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while(moudle->STATUS.B.TXFIFOLEVEL != 0);
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while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
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while(moudle->STATUS.B.RXFIFOLEVEL == 0);
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if(NULL != midata) IfxQspi_read8(moudle,midata,1);
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else (void)MODULE_QSPI2.RXEXIT.U;
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else (void)moudle->RXEXIT.U;
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}
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@@ -35,7 +35,7 @@ void systick_delay(STMN_enum stmn, uint32 time)
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uint32 stm_clk;
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stm_clk = IfxStm_getFrequency(IfxStm_getAddress((IfxStm_Index)stmn));
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IfxStm_waitTicks(&MODULE_STM0, (uint32)((uint64)stm_clk*time/1000000000));
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IfxStm_waitTicks(IfxStm_getAddress((IfxStm_Index)stmn), (uint32)((uint64)stm_clk*time/1000000000));
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}
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|
||||
@@ -325,8 +325,12 @@ void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
now_col = 0;
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -1,2 +1,9 @@
|
||||
V1.0.0
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
|
||||
|
||||
V1.0.1
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
<09><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
|
||||
<09><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
@@ -281,7 +281,15 @@ void gtm_pwm_init(ATOM_PIN_enum pwmch, uint32 freq, uint32 duty)
|
||||
g_atomConfig.synchronousUpdateEnabled = TRUE;
|
||||
|
||||
g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX);
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
switch(atom_channel->atom)
|
||||
{
|
||||
case 0: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX); break;
|
||||
case 1: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM1_PWM_DUTY_MAX); break;
|
||||
case 2: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM2_PWM_DUTY_MAX); break;
|
||||
case 3: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM3_PWM_DUTY_MAX); break;
|
||||
}
|
||||
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
IfxGtm_Atom_Pwm_start(&g_atomDriver, TRUE);
|
||||
}
|
||||
|
||||
|
||||
@@ -279,7 +279,7 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
|
||||
moudle = IfxQspi_getAddress((IfxQspi_Index)spi_n);
|
||||
|
||||
bacon.U = MODULE_QSPI2.BACON.U;
|
||||
bacon.U = moudle->BACON.U;
|
||||
|
||||
bacon.B.DL = 7;
|
||||
bacon.B.IDLE = 1;
|
||||
@@ -300,11 +300,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
i = 0;
|
||||
while(i < (len-1))
|
||||
{
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
IfxQspi_write8(moudle, IfxQspi_ChannelId_0, modata, 1);
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
modata++;
|
||||
midata++;
|
||||
i++;
|
||||
@@ -314,11 +314,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
if(continuous) IfxQspi_writeBasicConfigurationEndStream(moudle, bacon.U);
|
||||
IfxQspi_writeTransmitFifo(moudle, *modata);
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -35,7 +35,7 @@ void systick_delay(STMN_enum stmn, uint32 time)
|
||||
uint32 stm_clk;
|
||||
stm_clk = IfxStm_getFrequency(IfxStm_getAddress((IfxStm_Index)stmn));
|
||||
|
||||
IfxStm_waitTicks(&MODULE_STM0, (uint32)((uint64)stm_clk*time/1000000000));
|
||||
IfxStm_waitTicks(IfxStm_getAddress((IfxStm_Index)stmn), (uint32)((uint64)stm_clk*time/1000000000));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -325,8 +325,12 @@ void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
now_col = 0;
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -1,2 +1,9 @@
|
||||
V1.0.0
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
|
||||
|
||||
V1.0.1
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
<09><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
|
||||
<09><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
@@ -281,7 +281,15 @@ void gtm_pwm_init(ATOM_PIN_enum pwmch, uint32 freq, uint32 duty)
|
||||
g_atomConfig.synchronousUpdateEnabled = TRUE;
|
||||
|
||||
g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX);
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
switch(atom_channel->atom)
|
||||
{
|
||||
case 0: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX); break;
|
||||
case 1: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM1_PWM_DUTY_MAX); break;
|
||||
case 2: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM2_PWM_DUTY_MAX); break;
|
||||
case 3: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM3_PWM_DUTY_MAX); break;
|
||||
}
|
||||
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
IfxGtm_Atom_Pwm_start(&g_atomDriver, TRUE);
|
||||
}
|
||||
|
||||
|
||||
@@ -279,7 +279,7 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
|
||||
moudle = IfxQspi_getAddress((IfxQspi_Index)spi_n);
|
||||
|
||||
bacon.U = MODULE_QSPI2.BACON.U;
|
||||
bacon.U = moudle->BACON.U;
|
||||
|
||||
bacon.B.DL = 7;
|
||||
bacon.B.IDLE = 1;
|
||||
@@ -300,11 +300,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
i = 0;
|
||||
while(i < (len-1))
|
||||
{
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
IfxQspi_write8(moudle, IfxQspi_ChannelId_0, modata, 1);
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
modata++;
|
||||
midata++;
|
||||
i++;
|
||||
@@ -314,11 +314,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
if(continuous) IfxQspi_writeBasicConfigurationEndStream(moudle, bacon.U);
|
||||
IfxQspi_writeTransmitFifo(moudle, *modata);
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -35,7 +35,7 @@ void systick_delay(STMN_enum stmn, uint32 time)
|
||||
uint32 stm_clk;
|
||||
stm_clk = IfxStm_getFrequency(IfxStm_getAddress((IfxStm_Index)stmn));
|
||||
|
||||
IfxStm_waitTicks(&MODULE_STM0, (uint32)((uint64)stm_clk*time/1000000000));
|
||||
IfxStm_waitTicks(IfxStm_getAddress((IfxStm_Index)stmn), (uint32)((uint64)stm_clk*time/1000000000));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -325,8 +325,12 @@ void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
now_col = 0;
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -1,2 +1,9 @@
|
||||
V1.0.0
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
|
||||
|
||||
V1.0.1
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
<09><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
|
||||
<09><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
@@ -281,7 +281,15 @@ void gtm_pwm_init(ATOM_PIN_enum pwmch, uint32 freq, uint32 duty)
|
||||
g_atomConfig.synchronousUpdateEnabled = TRUE;
|
||||
|
||||
g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX);
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
switch(atom_channel->atom)
|
||||
{
|
||||
case 0: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX); break;
|
||||
case 1: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM1_PWM_DUTY_MAX); break;
|
||||
case 2: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM2_PWM_DUTY_MAX); break;
|
||||
case 3: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM3_PWM_DUTY_MAX); break;
|
||||
}
|
||||
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
IfxGtm_Atom_Pwm_start(&g_atomDriver, TRUE);
|
||||
}
|
||||
|
||||
|
||||
@@ -279,7 +279,7 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
|
||||
moudle = IfxQspi_getAddress((IfxQspi_Index)spi_n);
|
||||
|
||||
bacon.U = MODULE_QSPI2.BACON.U;
|
||||
bacon.U = moudle->BACON.U;
|
||||
|
||||
bacon.B.DL = 7;
|
||||
bacon.B.IDLE = 1;
|
||||
@@ -300,11 +300,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
i = 0;
|
||||
while(i < (len-1))
|
||||
{
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
IfxQspi_write8(moudle, IfxQspi_ChannelId_0, modata, 1);
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
modata++;
|
||||
midata++;
|
||||
i++;
|
||||
@@ -314,11 +314,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
if(continuous) IfxQspi_writeBasicConfigurationEndStream(moudle, bacon.U);
|
||||
IfxQspi_writeTransmitFifo(moudle, *modata);
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -35,7 +35,7 @@ void systick_delay(STMN_enum stmn, uint32 time)
|
||||
uint32 stm_clk;
|
||||
stm_clk = IfxStm_getFrequency(IfxStm_getAddress((IfxStm_Index)stmn));
|
||||
|
||||
IfxStm_waitTicks(&MODULE_STM0, (uint32)((uint64)stm_clk*time/1000000000));
|
||||
IfxStm_waitTicks(IfxStm_getAddress((IfxStm_Index)stmn), (uint32)((uint64)stm_clk*time/1000000000));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -325,8 +325,12 @@ void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
now_col = 0;
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -1,2 +1,9 @@
|
||||
V1.0.0
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
|
||||
|
||||
V1.0.1
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
<09><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
|
||||
<09><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
@@ -281,7 +281,15 @@ void gtm_pwm_init(ATOM_PIN_enum pwmch, uint32 freq, uint32 duty)
|
||||
g_atomConfig.synchronousUpdateEnabled = TRUE;
|
||||
|
||||
g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX);
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
switch(atom_channel->atom)
|
||||
{
|
||||
case 0: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX); break;
|
||||
case 1: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM1_PWM_DUTY_MAX); break;
|
||||
case 2: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM2_PWM_DUTY_MAX); break;
|
||||
case 3: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM3_PWM_DUTY_MAX); break;
|
||||
}
|
||||
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
IfxGtm_Atom_Pwm_start(&g_atomDriver, TRUE);
|
||||
}
|
||||
|
||||
|
||||
@@ -279,7 +279,7 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
|
||||
moudle = IfxQspi_getAddress((IfxQspi_Index)spi_n);
|
||||
|
||||
bacon.U = MODULE_QSPI2.BACON.U;
|
||||
bacon.U = moudle->BACON.U;
|
||||
|
||||
bacon.B.DL = 7;
|
||||
bacon.B.IDLE = 1;
|
||||
@@ -300,11 +300,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
i = 0;
|
||||
while(i < (len-1))
|
||||
{
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
IfxQspi_write8(moudle, IfxQspi_ChannelId_0, modata, 1);
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
modata++;
|
||||
midata++;
|
||||
i++;
|
||||
@@ -314,11 +314,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
if(continuous) IfxQspi_writeBasicConfigurationEndStream(moudle, bacon.U);
|
||||
IfxQspi_writeTransmitFifo(moudle, *modata);
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -35,7 +35,7 @@ void systick_delay(STMN_enum stmn, uint32 time)
|
||||
uint32 stm_clk;
|
||||
stm_clk = IfxStm_getFrequency(IfxStm_getAddress((IfxStm_Index)stmn));
|
||||
|
||||
IfxStm_waitTicks(&MODULE_STM0, (uint32)((uint64)stm_clk*time/1000000000));
|
||||
IfxStm_waitTicks(IfxStm_getAddress((IfxStm_Index)stmn), (uint32)((uint64)stm_clk*time/1000000000));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -325,8 +325,12 @@ void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
now_col = 0;
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -1,2 +1,9 @@
|
||||
V1.0.0
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
|
||||
|
||||
V1.0.1
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
<09><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
|
||||
<09><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
@@ -281,7 +281,15 @@ void gtm_pwm_init(ATOM_PIN_enum pwmch, uint32 freq, uint32 duty)
|
||||
g_atomConfig.synchronousUpdateEnabled = TRUE;
|
||||
|
||||
g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX);
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
switch(atom_channel->atom)
|
||||
{
|
||||
case 0: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX); break;
|
||||
case 1: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM1_PWM_DUTY_MAX); break;
|
||||
case 2: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM2_PWM_DUTY_MAX); break;
|
||||
case 3: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM3_PWM_DUTY_MAX); break;
|
||||
}
|
||||
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
IfxGtm_Atom_Pwm_start(&g_atomDriver, TRUE);
|
||||
}
|
||||
|
||||
|
||||
@@ -279,7 +279,7 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
|
||||
moudle = IfxQspi_getAddress((IfxQspi_Index)spi_n);
|
||||
|
||||
bacon.U = MODULE_QSPI2.BACON.U;
|
||||
bacon.U = moudle->BACON.U;
|
||||
|
||||
bacon.B.DL = 7;
|
||||
bacon.B.IDLE = 1;
|
||||
@@ -300,11 +300,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
i = 0;
|
||||
while(i < (len-1))
|
||||
{
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
IfxQspi_write8(moudle, IfxQspi_ChannelId_0, modata, 1);
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
modata++;
|
||||
midata++;
|
||||
i++;
|
||||
@@ -314,11 +314,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
if(continuous) IfxQspi_writeBasicConfigurationEndStream(moudle, bacon.U);
|
||||
IfxQspi_writeTransmitFifo(moudle, *modata);
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -35,7 +35,7 @@ void systick_delay(STMN_enum stmn, uint32 time)
|
||||
uint32 stm_clk;
|
||||
stm_clk = IfxStm_getFrequency(IfxStm_getAddress((IfxStm_Index)stmn));
|
||||
|
||||
IfxStm_waitTicks(&MODULE_STM0, (uint32)((uint64)stm_clk*time/1000000000));
|
||||
IfxStm_waitTicks(IfxStm_getAddress((IfxStm_Index)stmn), (uint32)((uint64)stm_clk*time/1000000000));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -325,8 +325,12 @@ void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
now_col = 0;
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -1,2 +1,9 @@
|
||||
V1.0.0
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
|
||||
|
||||
V1.0.1
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
<09><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
|
||||
<09><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
@@ -281,7 +281,15 @@ void gtm_pwm_init(ATOM_PIN_enum pwmch, uint32 freq, uint32 duty)
|
||||
g_atomConfig.synchronousUpdateEnabled = TRUE;
|
||||
|
||||
g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX);
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
switch(atom_channel->atom)
|
||||
{
|
||||
case 0: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX); break;
|
||||
case 1: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM1_PWM_DUTY_MAX); break;
|
||||
case 2: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM2_PWM_DUTY_MAX); break;
|
||||
case 3: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM3_PWM_DUTY_MAX); break;
|
||||
}
|
||||
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
IfxGtm_Atom_Pwm_start(&g_atomDriver, TRUE);
|
||||
}
|
||||
|
||||
|
||||
@@ -279,7 +279,7 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
|
||||
moudle = IfxQspi_getAddress((IfxQspi_Index)spi_n);
|
||||
|
||||
bacon.U = MODULE_QSPI2.BACON.U;
|
||||
bacon.U = moudle->BACON.U;
|
||||
|
||||
bacon.B.DL = 7;
|
||||
bacon.B.IDLE = 1;
|
||||
@@ -300,11 +300,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
i = 0;
|
||||
while(i < (len-1))
|
||||
{
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
IfxQspi_write8(moudle, IfxQspi_ChannelId_0, modata, 1);
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
modata++;
|
||||
midata++;
|
||||
i++;
|
||||
@@ -314,11 +314,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
if(continuous) IfxQspi_writeBasicConfigurationEndStream(moudle, bacon.U);
|
||||
IfxQspi_writeTransmitFifo(moudle, *modata);
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -35,7 +35,7 @@ void systick_delay(STMN_enum stmn, uint32 time)
|
||||
uint32 stm_clk;
|
||||
stm_clk = IfxStm_getFrequency(IfxStm_getAddress((IfxStm_Index)stmn));
|
||||
|
||||
IfxStm_waitTicks(&MODULE_STM0, (uint32)((uint64)stm_clk*time/1000000000));
|
||||
IfxStm_waitTicks(IfxStm_getAddress((IfxStm_Index)stmn), (uint32)((uint64)stm_clk*time/1000000000));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -325,8 +325,12 @@ void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
now_col = 0;
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -1,2 +1,9 @@
|
||||
V1.0.0
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
|
||||
|
||||
V1.0.1
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
<09><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
|
||||
<09><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
@@ -281,7 +281,15 @@ void gtm_pwm_init(ATOM_PIN_enum pwmch, uint32 freq, uint32 duty)
|
||||
g_atomConfig.synchronousUpdateEnabled = TRUE;
|
||||
|
||||
g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX);
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
switch(atom_channel->atom)
|
||||
{
|
||||
case 0: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX); break;
|
||||
case 1: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM1_PWM_DUTY_MAX); break;
|
||||
case 2: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM2_PWM_DUTY_MAX); break;
|
||||
case 3: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM3_PWM_DUTY_MAX); break;
|
||||
}
|
||||
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
IfxGtm_Atom_Pwm_start(&g_atomDriver, TRUE);
|
||||
}
|
||||
|
||||
|
||||
@@ -279,7 +279,7 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
|
||||
moudle = IfxQspi_getAddress((IfxQspi_Index)spi_n);
|
||||
|
||||
bacon.U = MODULE_QSPI2.BACON.U;
|
||||
bacon.U = moudle->BACON.U;
|
||||
|
||||
bacon.B.DL = 7;
|
||||
bacon.B.IDLE = 1;
|
||||
@@ -300,11 +300,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
i = 0;
|
||||
while(i < (len-1))
|
||||
{
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
IfxQspi_write8(moudle, IfxQspi_ChannelId_0, modata, 1);
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
modata++;
|
||||
midata++;
|
||||
i++;
|
||||
@@ -314,11 +314,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
if(continuous) IfxQspi_writeBasicConfigurationEndStream(moudle, bacon.U);
|
||||
IfxQspi_writeTransmitFifo(moudle, *modata);
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -35,7 +35,7 @@ void systick_delay(STMN_enum stmn, uint32 time)
|
||||
uint32 stm_clk;
|
||||
stm_clk = IfxStm_getFrequency(IfxStm_getAddress((IfxStm_Index)stmn));
|
||||
|
||||
IfxStm_waitTicks(&MODULE_STM0, (uint32)((uint64)stm_clk*time/1000000000));
|
||||
IfxStm_waitTicks(IfxStm_getAddress((IfxStm_Index)stmn), (uint32)((uint64)stm_clk*time/1000000000));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -325,8 +325,12 @@ void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
now_col = 0;
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -1,2 +1,9 @@
|
||||
V1.0.0
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
|
||||
|
||||
V1.0.1
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
<09><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
|
||||
<09><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
@@ -281,7 +281,15 @@ void gtm_pwm_init(ATOM_PIN_enum pwmch, uint32 freq, uint32 duty)
|
||||
g_atomConfig.synchronousUpdateEnabled = TRUE;
|
||||
|
||||
g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX);
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
switch(atom_channel->atom)
|
||||
{
|
||||
case 0: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX); break;
|
||||
case 1: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM1_PWM_DUTY_MAX); break;
|
||||
case 2: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM2_PWM_DUTY_MAX); break;
|
||||
case 3: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM3_PWM_DUTY_MAX); break;
|
||||
}
|
||||
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
IfxGtm_Atom_Pwm_start(&g_atomDriver, TRUE);
|
||||
}
|
||||
|
||||
|
||||
@@ -279,7 +279,7 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
|
||||
moudle = IfxQspi_getAddress((IfxQspi_Index)spi_n);
|
||||
|
||||
bacon.U = MODULE_QSPI2.BACON.U;
|
||||
bacon.U = moudle->BACON.U;
|
||||
|
||||
bacon.B.DL = 7;
|
||||
bacon.B.IDLE = 1;
|
||||
@@ -300,11 +300,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
i = 0;
|
||||
while(i < (len-1))
|
||||
{
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
IfxQspi_write8(moudle, IfxQspi_ChannelId_0, modata, 1);
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
modata++;
|
||||
midata++;
|
||||
i++;
|
||||
@@ -314,11 +314,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
if(continuous) IfxQspi_writeBasicConfigurationEndStream(moudle, bacon.U);
|
||||
IfxQspi_writeTransmitFifo(moudle, *modata);
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -35,7 +35,7 @@ void systick_delay(STMN_enum stmn, uint32 time)
|
||||
uint32 stm_clk;
|
||||
stm_clk = IfxStm_getFrequency(IfxStm_getAddress((IfxStm_Index)stmn));
|
||||
|
||||
IfxStm_waitTicks(&MODULE_STM0, (uint32)((uint64)stm_clk*time/1000000000));
|
||||
IfxStm_waitTicks(IfxStm_getAddress((IfxStm_Index)stmn), (uint32)((uint64)stm_clk*time/1000000000));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -325,8 +325,12 @@ void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
now_col = 0;
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -1,2 +1,9 @@
|
||||
V1.0.0
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
|
||||
|
||||
V1.0.1
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
<09><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
|
||||
<09><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
@@ -281,7 +281,15 @@ void gtm_pwm_init(ATOM_PIN_enum pwmch, uint32 freq, uint32 duty)
|
||||
g_atomConfig.synchronousUpdateEnabled = TRUE;
|
||||
|
||||
g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX);
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
switch(atom_channel->atom)
|
||||
{
|
||||
case 0: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX); break;
|
||||
case 1: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM1_PWM_DUTY_MAX); break;
|
||||
case 2: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM2_PWM_DUTY_MAX); break;
|
||||
case 3: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM3_PWM_DUTY_MAX); break;
|
||||
}
|
||||
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
IfxGtm_Atom_Pwm_start(&g_atomDriver, TRUE);
|
||||
}
|
||||
|
||||
|
||||
@@ -279,7 +279,7 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
|
||||
moudle = IfxQspi_getAddress((IfxQspi_Index)spi_n);
|
||||
|
||||
bacon.U = MODULE_QSPI2.BACON.U;
|
||||
bacon.U = moudle->BACON.U;
|
||||
|
||||
bacon.B.DL = 7;
|
||||
bacon.B.IDLE = 1;
|
||||
@@ -300,11 +300,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
i = 0;
|
||||
while(i < (len-1))
|
||||
{
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
IfxQspi_write8(moudle, IfxQspi_ChannelId_0, modata, 1);
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
modata++;
|
||||
midata++;
|
||||
i++;
|
||||
@@ -314,11 +314,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
if(continuous) IfxQspi_writeBasicConfigurationEndStream(moudle, bacon.U);
|
||||
IfxQspi_writeTransmitFifo(moudle, *modata);
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -35,7 +35,7 @@ void systick_delay(STMN_enum stmn, uint32 time)
|
||||
uint32 stm_clk;
|
||||
stm_clk = IfxStm_getFrequency(IfxStm_getAddress((IfxStm_Index)stmn));
|
||||
|
||||
IfxStm_waitTicks(&MODULE_STM0, (uint32)((uint64)stm_clk*time/1000000000));
|
||||
IfxStm_waitTicks(IfxStm_getAddress((IfxStm_Index)stmn), (uint32)((uint64)stm_clk*time/1000000000));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -325,8 +325,12 @@ void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
now_col = 0;
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -267,11 +267,7 @@
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
<storageModule addStartupFiles="false" moduleId="com.tasking.processor"/>
|
||||
<storageModule moduleId="com.tasking.toolInfo">
|
||||
<toolInfo>TASKING VX-toolset for TriCore: control program v6.3r1 Build 19041558</toolInfo>
|
||||
<toolInfo>TASKING VX-toolset for TriCore: object linker v6.3r1 Build 19041558</toolInfo>
|
||||
<toolInfo>TASKING VX-toolset for TriCore: assembler v6.3r1 Build 19041558</toolInfo>
|
||||
<toolInfo>TASKING program builder v6.3r1 Build 19041558</toolInfo>
|
||||
<toolInfo>TASKING VX-toolset for TriCore: C compiler v6.3r1 Build 19041558</toolInfo>
|
||||
</storageModule>
|
||||
</cconfiguration>
|
||||
<cconfiguration id="com.tasking.config.ctc.abs.release.2134260939">
|
||||
|
||||
@@ -1,2 +1,9 @@
|
||||
V1.0.0
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
|
||||
|
||||
V1.0.1
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
<09><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
|
||||
<09><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
@@ -281,7 +281,15 @@ void gtm_pwm_init(ATOM_PIN_enum pwmch, uint32 freq, uint32 duty)
|
||||
g_atomConfig.synchronousUpdateEnabled = TRUE;
|
||||
|
||||
g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX);
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
switch(atom_channel->atom)
|
||||
{
|
||||
case 0: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM0_PWM_DUTY_MAX); break;
|
||||
case 1: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM1_PWM_DUTY_MAX); break;
|
||||
case 2: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM2_PWM_DUTY_MAX); break;
|
||||
case 3: g_atomConfig.dutyCycle = (uint32)((uint64)duty * g_atomConfig.period / GTM_ATOM3_PWM_DUTY_MAX); break;
|
||||
}
|
||||
|
||||
IfxGtm_Atom_Pwm_init(&g_atomDriver, &g_atomConfig);
|
||||
IfxGtm_Atom_Pwm_start(&g_atomDriver, TRUE);
|
||||
}
|
||||
|
||||
|
||||
@@ -279,7 +279,7 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
|
||||
moudle = IfxQspi_getAddress((IfxQspi_Index)spi_n);
|
||||
|
||||
bacon.U = MODULE_QSPI2.BACON.U;
|
||||
bacon.U = moudle->BACON.U;
|
||||
|
||||
bacon.B.DL = 7;
|
||||
bacon.B.IDLE = 1;
|
||||
@@ -300,11 +300,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
i = 0;
|
||||
while(i < (len-1))
|
||||
{
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
IfxQspi_write8(moudle, IfxQspi_ChannelId_0, modata, 1);
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
modata++;
|
||||
midata++;
|
||||
i++;
|
||||
@@ -314,11 +314,11 @@ void spi_mosi(SPIN_enum spi_n, SPI_PIN_enum cs_pin, uint8 *modata, uint8 *midata
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
if(continuous) IfxQspi_writeBasicConfigurationEndStream(moudle, bacon.U);
|
||||
IfxQspi_writeTransmitFifo(moudle, *modata);
|
||||
while(MODULE_QSPI2.STATUS.B.TXFIFOLEVEL != 0);
|
||||
while(moudle->STATUS.B.TXFIFOLEVEL != 0);
|
||||
|
||||
while(MODULE_QSPI2.STATUS.B.RXFIFOLEVEL == 0);
|
||||
while(moudle->STATUS.B.RXFIFOLEVEL == 0);
|
||||
if(NULL != midata) IfxQspi_read8(moudle,midata,1);
|
||||
else (void)MODULE_QSPI2.RXEXIT.U;
|
||||
else (void)moudle->RXEXIT.U;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -35,7 +35,7 @@ void systick_delay(STMN_enum stmn, uint32 time)
|
||||
uint32 stm_clk;
|
||||
stm_clk = IfxStm_getFrequency(IfxStm_getAddress((IfxStm_Index)stmn));
|
||||
|
||||
IfxStm_waitTicks(&MODULE_STM0, (uint32)((uint64)stm_clk*time/1000000000));
|
||||
IfxStm_waitTicks(IfxStm_getAddress((IfxStm_Index)stmn), (uint32)((uint64)stm_clk*time/1000000000));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -325,8 +325,12 @@ void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
now_col = 0;
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, (void *)&mt9v03x_image[0]);
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -27,8 +27,6 @@ int core0_main(void)
|
||||
|
||||
//<2F>û<EFBFBD><C3BB>ڴ˴<DAB4><CBB4><EFBFBD><EFBFBD>ø<EFBFBD><C3B8>ֳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
|
||||
|
||||
enableInterrupts();
|
||||
|
||||
while (TRUE)
|
||||
|
||||
Reference in New Issue
Block a user