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https://gitee.com/seekfree/TC264_Library.git
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SEEKFREE_BUDING
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@@ -1,40 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>Seekfree_TC264_Opensource_Library</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>com.infineon.aurix.buildsystem.builders.booster</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>com.infineon.aurix.buildsystem.builders.autodiscovery</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.core.ccnature</nature>
|
||||
<nature>com.infineon.aurix.buildsystem.aurixnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
Binary file not shown.
@@ -1,10 +0,0 @@
|
||||
AURIX-LIBRARY-PATH=Libraries/iLLD\#Libraries/Infra\#Libraries/Service
|
||||
DEVICE-ID=TC26B
|
||||
DEVICE-ID-FULL=TC26xD_B-Step
|
||||
ILLD-SET=full
|
||||
IncludesAutodiscovery=true
|
||||
LIBRARIES-ROOT-PATH=Libraries
|
||||
NEVER-EXCLUDE-FROM-BUILD=/Libraries/iLLD/TC26B/Tricore/Cpu/CStart\#/Libraries/iLLD/TC26B/Tricore/Cpu/Trap\#/Configurations\#/Configurations/Debug
|
||||
PROJECT-VERSION=1.0
|
||||
aurixDevice=TC26xD_B-Step
|
||||
eclipse.preferences.version=1
|
||||
@@ -1,8 +0,0 @@
|
||||
eclipse.preferences.version=1
|
||||
encoding//Libraries/infineon_libraries/Infra/Sfr/TC26B/_Reg/IfxGtm_regdef.h=UTF-8
|
||||
encoding//Libraries/zf_common/zf_common_clock.c=UTF-8
|
||||
encoding//Libraries/zf_common/zf_common_clock.h=UTF-8
|
||||
encoding//Libraries/zf_device/zf_device_bmi270.c=UTF-8
|
||||
encoding//libraries/zf_common/zf_common_clock.c=UTF-8
|
||||
encoding//libraries/zf_common/zf_common_clock.h=UTF-8
|
||||
encoding//libraries/zf_device/zf_device_imu660ra.c=UTF-8
|
||||
@@ -1,449 +0,0 @@
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
// Specify a multi-core processor environment (mpe)
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
|
||||
select ".bss.cpu1_dsram|.bss.cpu1_dsram.*";
|
||||
select ".data.cpu1_dsram|.data.cpu1_dsram.*";
|
||||
select ".zdata.cpu1_dsram|.zdata.cpu1_dsram.*";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
|
||||
select ".bss.cpu0_dsram|.bss.cpu0_dsram.*";
|
||||
select ".data.cpu0_dsram|.data.cpu0_dsram.*";
|
||||
select ".zdata.cpu0_dsram|.zdata.cpu0_dsram.*";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
@@ -1,3 +0,0 @@
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Լ<EFBFBD><EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CODE<EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<EFBFBD><EFBFBD>Ҫ<EFBFBD>ٴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD>У<EFBFBD>ֱ<EFBFBD>ӽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CODE<EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
Ȼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɱ<EFBFBD><EFBFBD><EFBFBD>
|
||||
@@ -1,13 +0,0 @@
|
||||
TC264 Opensourec Library : An open source library of third party interfaces based on the official SDK
|
||||
Copyright (C) 2022 SEEKFREE <20><><EFBFBD>ɿƼ<C9BF>
|
||||
|
||||
TC264 Opensourec Library is free software:
|
||||
you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation,
|
||||
either version 3 of the License, or (at your option) any later version.
|
||||
|
||||
TC264 Opensourec Library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||
without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
See the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with TC264 Opensourec Library.
|
||||
If not, see <https://www.gnu.org/licenses/>.
|
||||
@@ -1,163 +0,0 @@
|
||||
V3.0.0
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>ʵ<EFBFBD><CAB5>
|
||||
<20><>ǿ<EFBFBD>˴<EFBFBD><CBB4><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD>ֲ<EFBFBD><D6B2> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>V3<56>⣬<EFBFBD><E2A3AC>ô<EFBFBD>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>κδ<CEBA><CEB4>뼴<EFBFBD><EBBCB4><EFBFBD>ڲ<EFBFBD>ͬ<EFBFBD>ĵ<EFBFBD>Ƭ<EFBFBD><C6AC><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5><EFBFBD><EFBFBD>ͬ<EFBFBD>Ĺ<EFBFBD><C4B9><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD>˲<EFBFBD><CBB2>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>㹦<EFBFBD><E3B9A6>
|
||||
V1.3.0
|
||||
<20><>icm20602<30>ij<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵ<EFBFBD><CFB5>˵<EFBFBD><CBB5>
|
||||
V1.2.10
|
||||
<20><><EFBFBD><EFBFBD>IMU963RA<52><41><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD>
|
||||
V1.2.9
|
||||
ɾ<><C9BE>SEEKFREE_IPS200_PARALLEL8<4C>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SEEKFREE_IPS200<30><30><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD>ԭ<EFBFBD>е<EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҳ<EFBFBD><D2B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>µ<EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><EFBFBD>spi<70>ײ<EFBFBD><D7B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˳<EFBFBD>ʱ<EFBFBD>ж<EFBFBD>cs<63><73><EFBFBD><EFBFBD>״̬<D7B4><CCAC>ȷ<EFBFBD><C8B7>spi<70><69><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD><C9BA>˳<EFBFBD><CBB3><EFBFBD>
|
||||
<20><>tft<66><74>ips114<31><34><EFBFBD><EFBFBD><EFBFBD>з<EFBFBD><D0B7>͵<EFBFBD>my_delayȥ<79><C8A5>
|
||||
V1.2.8
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ײ<EFBFBD><D7B2><EFBFBD><EFBFBD><EFBFBD>PCLK_MODE<44><45>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>λ
|
||||
|
||||
V1.2.7
|
||||
<20><EFBFBD>֮ǰ<D6AE><C7B0><EFBFBD>͵<EFBFBD><CDB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ײ<EFBFBD><D7B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>⣬<EFBFBD>ᵼ<EFBFBD><E1B5BC><EFBFBD><EFBFBD><EFBFBD>׳<EFBFBD><D7B3>ֲɼ<D6B2><C9BC><EFBFBD>λ<EFBFBD><CEBB>
|
||||
<20><><EFBFBD><EFBFBD>ż<EFBFBD><C5BC><EFBFBD>Ӵ<EFBFBD><D3B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͼ<EFBFBD><CDBC><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>Ӽ<EFBFBD><D3BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><F2B2A2B3>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DEB8><EFBFBD>
|
||||
|
||||
V1.2.6
|
||||
<20><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ײ㣬<D7B2><E3A3AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>÷<EFBFBD>ʽ
|
||||
<20><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ײ㣬<D7B2><E3A3AC><EFBFBD>Ӷ<EFBFBD>V2.1<EFBFBD>汾<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PCLK<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD>˫ƵGPS<50><53>λģ<CEBB><C4A3><EFBFBD>ĵײ<C4B5><D7B2><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.2.5
|
||||
<09>Ż<EFBFBD>Ӳ<EFBFBD><D3B2>SPI<50><49><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPI<50><49>Ļ<EFBFBD><C4BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPI<50><49>Ļˢ<C4BB><CBA2><EFBFBD>ٶȣ<D9B6>IPS1.14<EFBFBD><EFBFBD>Ļ<EFBFBD><EFBFBD>ʾ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>188*120<32>ɴ<EFBFBD>31֡<31><D6A1><EFBFBD><EFBFBD>ʾ160*120<32>ɴ<EFBFBD>37֡<37><D6A1>TFT1.8<EFBFBD><EFBFBD>Ļ<EFBFBD><EFBFBD>ʾ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>160*120<32>ɴ<EFBFBD>37֡<37><D6A1>
|
||||
|
||||
V1.2.4
|
||||
<09><EFBFBD>systick_delay_ms<6D><73><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱʱ<CAB1><CAB1><EFBFBD>ϳ<EFBFBD><CFB3><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱʱ<CAB1>䲻<EFBFBD><E4B2BB>ȷ<EFBFBD><C8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.2.3
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>н<EFBFBD>PCLK<4C><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD>ش<EFBFBD><D8B4><EFBFBD>
|
||||
<09><EFBFBD>systick<63><6B>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>us<75><73><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
|
||||
|
||||
V1.2.2
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷͼ<CDB7><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ż<EFBFBD><C5BC><EFBFBD>Դ<EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>³<EFBFBD>ʼ<EFBFBD><CABC>DMAʹ<41><CAB9><EFBFBD>´βɼ<CEB2>ͼ<EFBFBD><CDBC><EFBFBD>Զ<EFBFBD><D4B6>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD>ش<EFBFBD><D8B4><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD>ͷȥ<CDB7><C8A5><EFBFBD><EFBFBD>־λ<D6BE><CEBB><EFBFBD><EFBFBD><EFBFBD>ż<EFBFBD><C5BC><EFBFBD><EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DFBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֡<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.2.1
|
||||
<20><><EFBFBD><EFBFBD>printf<74>رյ<D8B1>ʱ<EFBFBD><EFBFBD><F2A3ACB1>뱨<EFBFBD><EBB1A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.2.0
|
||||
<20><><EFBFBD><EFBFBD>CH9141<34><31><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD>ö<EFBFBD>ٱ<EFBFBD><D9B1><EFBFBD>
|
||||
<20><EFBFBD> ɾ<><C9BE><EFBFBD><EFBFBD>ʱ<EFBFBD>ļ<EFBFBD>.bat ִ<><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD><D4B6>رմ<D8B1><D5B4><EFBFBD>
|
||||
<20><EFBFBD> ɾ<><C9BE><EFBFBD><EFBFBD>ʱ<EFBFBD>ļ<EFBFBD>.bat <20><><EFBFBD><EFBFBD>ɾ<EFBFBD><C9BE><EFBFBD>°汾<C2B0><E6B1BE><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD>
|
||||
<20>Ĺ<DEB8><C4B9><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD>֧<EFBFBD><D6A7><EFBFBD>°汾<C2B0><E6B1BE><EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.10
|
||||
<20><EFBFBD>ͨ<EFBFBD><CDA8>#pragma section all "cpux_dsram"ָ<><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>ʧЧ<CAA7><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.9
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD>ڵķ<DAB5><C4B7><EFBFBD>buff<66><66><EFBFBD>ӵ<EFBFBD>128<32>ֽ<EFBFBD>
|
||||
|
||||
V1.1.8
|
||||
<20><>isr_config.h<><68> INT_SERVICE<43><45><EFBFBD>ø<EFBFBD>Ϊʹ<CEAA><CAB9>ö<EFBFBD><C3B6>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD>illd<6C>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊinfineon_libraries
|
||||
<20><>TC264<36><34><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>
|
||||
<20><><EFBFBD><EFBFBD>main<69>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD>к<EFBFBD><D0BA>ij<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD>ϲſ<CFB2>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
|
||||
<20><EFBFBD>CLK_FREQ<45>궨<EFBFBD><EAB6A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΪCMU_CLK_FREQ
|
||||
DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַͨ<D6B7><CDA8>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD>鲻<EFBFBD><E9B2BB>ռ<EFBFBD><D5BC>RAM
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>pclk<6C><6B>Ϊ<EFBFBD>½<EFBFBD><C2BD>ش<EFBFBD><D8B4><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD>ڵ<EFBFBD>RTS<54><53><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.7
|
||||
<20><><EFBFBD>Ӵ<EFBFBD><D3B4>ڰ汾<DAB0><E6B1BE>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>ͱ<EFBFBD><CDB1><EFBFBD>ͨ<EFBFBD><CDA8>ö<EFBFBD><C3B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6><EFBFBD>
|
||||
|
||||
V1.1.6
|
||||
<20><>printf<74><EFBFBD>Ϊͨ<CEAA><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD>ΪADS<44>Ĺ<EFBFBD><C4B9>̣<EFBFBD>ADSֱ<53>ӵ<EFBFBD><D3B5>뼴<EFBFBD>ɱ<EFBFBD><C9B1><EFBFBD>
|
||||
|
||||
V1.1.5
|
||||
DMA_LINK<4E>ṹ<EFBFBD><E1B9B9>linked_list<73><74>Աȡ<D4B1><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>ɶ<EFBFBD><C9B6><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ָ<EFBFBD><D6B8>
|
||||
dma_link_list<73>ṹ<EFBFBD>嶨<EFBFBD><E5B6A8><EFBFBD><EFBFBD><EFBFBD>Ӷ<EFBFBD><D3B6><EFBFBD>
|
||||
|
||||
V1.1.4
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>ע<EFBFBD>ͱ<EFBFBD><CDB1><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>µ<EFBFBD>һ<EFBFBD><D2BB>ע<EFBFBD>ͱ<EFBFBD><CDB1>Զ<EFBFBD><D4B6>۵<EFBFBD><DBB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.3
|
||||
<20><EFBFBD>SPI spi_mosi<73><69><EFBFBD><EFBFBD><EFBFBD>ڽ<EFBFBD><DABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>յ<EFBFBD>ʱ<EFBFBD><EFBFBD><F2A3ACB3><EFBFBD><EFBFBD>쳣
|
||||
|
||||
V1.1.2
|
||||
<20><EFBFBD>ATOM_PWM<57><4D><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD><D5B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>쳣<EFBFBD><ECB3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.1
|
||||
<20><EFBFBD>uart_getchar<61><72><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD>ס<EFBFBD><D7A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.0
|
||||
<20><>ISR<53>ļ<EFBFBD><C4BC>ڵ<EFBFBD><DAB5>жϺ<D0B6><CFBA><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>enableInterrupts(); <20><>ʵ<EFBFBD><CAB5><EFBFBD>ж<EFBFBD>Ƕ<EFBFBD>Ĺ<D7B5><C4B9><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD>RDA5807<30><37>ȡRSSI<53><49><EFBFBD>ܺ<EFBFBD><DCBA><EFBFBD>
|
||||
<20><>DMA<4D><41><EFBFBD>Ӵ<EFBFBD><D3B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD><C3B5>ı<EFBFBD><C4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ERU_DMA_INT_SERVICE<43><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD>Ӧ<EFBFBD><D3A6>CPU<50><55>
|
||||
|
||||
V1.0.9
|
||||
<20><EFBFBD>RDA5807<30><37><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>֤<EFBFBD>ϵ<EFBFBD><CFB5><EFBFBD>1S<31>ڲ<EFBFBD><DAB2><EFBFBD>FMģ<4D><C4A3>
|
||||
|
||||
V1.0.8
|
||||
<20><EFBFBD>CCU61 ͨ<><CDA8>1<EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>ô<EFBFBD><C3B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><EFBFBD>CCU6<55><36><EFBFBD>ߵ<EFBFBD><DFB5>Ե<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD>ֹͣ<CDA3><D6B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߵ<EFBFBD><DFB5><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϵ<D0B6><CFB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><>CCU6<55><36><EFBFBD><EFBFBD>pit_close<73><65>pit_start<72><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڿ<EFBFBD><DABF>ƶ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>Ŀ<EFBFBD>ʼ<EFBFBD><CABC>ֹͣ
|
||||
<20><>CCU6<55><36><EFBFBD><EFBFBD>pit_disable_interrupt<70><74>pit_enable_interrupt<70><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڿ<EFBFBD><DABF><EFBFBD><EFBFBD>жϿ<D0B6><CFBF><EFBFBD>
|
||||
|
||||
V1.0.7
|
||||
<20><EFBFBD>ʹ<EFBFBD><CAB9>systick_getval<61><6C>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱʱ<CAB1>䳬<EFBFBD><E4B3AC>4<EFBFBD><34><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>⡣
|
||||
<20>Բ<EFBFBD><D4B2>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>#pragma warning<6E><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ż<EFBFBD><C5BB>ȼ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>־<EFBFBD><D6BE><EFBFBD>
|
||||
<20><EFBFBD>1.8<EFBFBD><EFBFBD>TFT<EFBFBD><EFBFBD>Ļ<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD>й<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD>ֵĴ<EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.6
|
||||
<20><><EFBFBD><EFBFBD>ADC<44><43><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD>õĺ궨<C4BA>壬ADC_SAMPLE_FREQUENCY<43><59><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ10Mhz<68><7A><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC><EFBFBD>µ<EFBFBD><C2B5>ٶ<EFBFBD><D9B6>нϴ<D0BD><CFB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.5
|
||||
ȡ<><C8A1>HEX<45><58><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.4
|
||||
Ĭ<>Ϲ<EFBFBD>ѡ<EFBFBD><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HEX<45>Ĺ<EFBFBD><C4B9><EFBFBD>
|
||||
<20><>Cpu1_Main.c<>е<EFBFBD>core1_main<69><6E><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϵĺ<CFB5><C4BA><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><EFBFBD>CPU1<55><EFBFBD><DEB7><EFBFBD>Ӧ<EFBFBD>жϵ<D0B6><CFB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
ɾ<><C9BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>еİ<D0B5><C4B0><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD>Ϣ
|
||||
<20><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD>ֱ<EFBFBD>ֻ<EFBFBD>ɼ<EFBFBD>һ<EFBFBD>ε<EFBFBD><CEB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD>RDA5807 FMģ<4D><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><EFBFBD>LSL<53>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>#pragma <20><>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߳<EFBFBD><DFB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>RAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ο<EFBFBD><CEBF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Specifies_Variable_Or_Code_Location_Demo
|
||||
//ʹ<><CAB9>#pragma section all "cpu0_dsram" <20><> #pragma section all restore<72><65><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram
|
||||
//<2F><><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>仰<EFBFBD>м伴<D0BC>ɣ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
#pragma section all "cpu0_dsram"
|
||||
uint8 test_arry[5]; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D>Ϊcpu1_dsram <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu1_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>CPUִ<55>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>õı<C3B5><C4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu1_dsram<61><6D><EFBFBD><EFBFBD>
|
||||
#pragma section all restore
|
||||
|
||||
//ʹ<><CAB9>#pragma section all "cpu0_psram" <20><> #pragma section all restore<72><65><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu0_psram
|
||||
//<2F><><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>仰<EFBFBD>м伴<D0BC>ɣ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
#pragma section all "cpu0_psram"
|
||||
void delay_tset(void) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu0_psram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4>
|
||||
{
|
||||
int i;
|
||||
i = 999;
|
||||
while(i--);
|
||||
}
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_psram<61><6D>Ϊcpu1_psram <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu1_psram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>CPUִ<55>У<EFBFBD><D0A3><EFBFBD><F2BDABBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>£<EFBFBD><C2A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ǵ<EFBFBD>flash<73><68><EFBFBD>ز<EFBFBD>ִ<EFBFBD><D6B4>
|
||||
//ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAM<41><4D><EFBFBD>У<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD>еij<D0B5><C4B3><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cache<68><EFBFBD><F3A3ACBB><EFBFBD><EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD>ٶȽ<D9B6><C8BD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ǾͿ<C7BE><CDBF>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAMִ<4D>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٶ<EFBFBD>
|
||||
#pragma section all restore
|
||||
|
||||
V1.0.3
|
||||
<20><>spi<70><69>uart<72><74>pit<69>в<EFBFBD><D0B2>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>volatile<6C><65><EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.2
|
||||
<20><EFBFBD>ģ<EFBFBD><C4A3>IICĬ<43><C4AC><EFBFBD><EFBFBD>ʱʱ<CAB1><CAB1>Ϊ20
|
||||
<20><><EFBFBD><EFBFBD> <20><>Ҫ<EFBFBD>ر<EFBFBD>ע<EFBFBD><D7A2>P20_2<5F>Dz<EFBFBD><C7B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĺ<EFBFBD><C4B9><EFBFBD> ע<><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ɼ<EFBFBD>DMA<4D><41>Ϊlink<6E><6B><EFBFBD>䣬<EFBFBD><E4A3AC><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>DMA<4D>жϴ<D0B6><CFB4><EFBFBD>
|
||||
<20><EFBFBD>Ĭ<EFBFBD>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD>IIC<49><43><EFBFBD>Ŷ<EFBFBD><C5B6><EFBFBD>
|
||||
<20><>6050<35><30> <20><>Ҫ<EFBFBD>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ģ<EFBFBD>飬<EFBFBD>ڳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD>ϵ<EFBFBD><CFB5><EFBFBD>ģ<EFBFBD><C4A3>IIC<49><43>ʼ<EFBFBD><CABC>
|
||||
<20><><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.1
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
<20><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
|
||||
<20><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.0
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
@@ -1,53 +0,0 @@
|
||||
/**********************************************************************************************************************
|
||||
* \file Ifx_Cfg.h
|
||||
* \brief Project configuration file.
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef IFX_CFG_H
|
||||
#define IFX_CFG_H 1
|
||||
|
||||
|
||||
/*********************************************************************************************************************/
|
||||
/*------------------------------------------Configuration for IfxScu_cfg.h-------------------------------------------*/
|
||||
/*********************************************************************************************************************/
|
||||
/* External oscillator frequency in Hz */
|
||||
#define IFX_CFG_SCU_XTAL_FREQUENCY (20000000) /* Allowed values are: 16000000, 20000000 or 40000000 */
|
||||
/* PLL frequency in Hz */
|
||||
#define IFX_CFG_SCU_PLL_FREQUENCY (200000000) /* Allowed values are: 80000000, 133000000, 160000000
|
||||
* or 200000000 */
|
||||
|
||||
/*********************************************************************************************************************/
|
||||
/*-----------------------------------Configuration for Software managed interrupt------------------------------------*/
|
||||
/*********************************************************************************************************************/
|
||||
/* #define IFX_USE_SW_MANAGED_INT */ /* Decomment this line if the project needs to use Software managed interrupts */
|
||||
|
||||
/*********************************************************************************************************************/
|
||||
/*---------------------------------Configuration for Trap Hook Functions' Extensions---------------------------------*/
|
||||
/*********************************************************************************************************************/
|
||||
/* #define IFX_CFG_EXTEND_TRAP_HOOKS */ /* Decomment this line if the project needs to extend trap hook functions */
|
||||
|
||||
#endif /* IFX_CFG_H */
|
||||
|
||||
@@ -1,76 +0,0 @@
|
||||
/**
|
||||
* \file CompilerDcc.c
|
||||
*
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* $Date: 2014-02-27 20:08:39 GMT$
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#include "Cpu/Std/Ifx_Types.h"
|
||||
#include "Compilers.h"
|
||||
|
||||
#if defined(__DCC__)
|
||||
/*!
|
||||
* \brief Initializes C variables
|
||||
*
|
||||
* This function is called in the startup. This function initialize the all variables in .data section
|
||||
* and clears the .bss section
|
||||
*
|
||||
* Parameters: Nil
|
||||
* Return: Nil
|
||||
*/
|
||||
void Ifx_C_Init(void)
|
||||
{
|
||||
extern void __init_main(void);
|
||||
|
||||
__init_main(); /* initialize data */
|
||||
}
|
||||
|
||||
|
||||
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
|
||||
/*Dummy main function
|
||||
* This function is required only for the Windriver, which looks for main while linking
|
||||
* ! DO NOT USE THIS FUNCTION !*/
|
||||
int main(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER */
|
||||
#endif
|
||||
@@ -1,170 +0,0 @@
|
||||
/**
|
||||
* \file CompilerDcc.h
|
||||
*
|
||||
* \version iLLD_New
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef COMPILERDCC_H
|
||||
#define COMPILERDCC_H 1
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
/*Linker definitions which are specific to Dcc */
|
||||
/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
|
||||
* to use the default compiler linker varaibles and startup */
|
||||
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
|
||||
|
||||
/*Start: Core 0 definitions ********************************************** */
|
||||
|
||||
/*C extern defintions */
|
||||
#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
|
||||
extern unsigned int __USTACK##cpu[]; /**< user stack end */ \
|
||||
extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
|
||||
extern unsigned int __INTTAB_CPU##cpu[]; /**< interrupt vector table */ \
|
||||
extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap vector table */ \
|
||||
extern unsigned int __CSA##cpu[]; /**< context save area begin */ \
|
||||
extern unsigned int __CSA##cpu##_END[]; /**< context save area end */
|
||||
|
||||
#define __USTACK(cpu) __USTACK##cpu
|
||||
#define __ISTACK(cpu) __ISTACK##cpu
|
||||
#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
|
||||
#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
|
||||
#define __CSA(cpu) __CSA##cpu
|
||||
#define __CSA_END(cpu) __CSA##cpu##_END
|
||||
|
||||
#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
|
||||
__asm("\t .weak __A8_MEM, __A9_MEM"); /**< ASM extern definitions */
|
||||
|
||||
/*Wrapper macros for the tool specific definitions */
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
|
||||
#else
|
||||
#define __INTTAB(cpu) __INTTAB_CPU##cpu
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT) */
|
||||
|
||||
#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
|
||||
|
||||
#define __SDATA1(cpu) _SMALL_DATA_
|
||||
#define __SDATA2(cpu) _LITERAL_DATA_
|
||||
#define __SDATA3(cpu) __A8_MEM
|
||||
#define __SDATA4(cpu) __A9_MEM
|
||||
|
||||
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
|
||||
|
||||
/******************************************************************************/
|
||||
#define IFX_INLINE static __inline__
|
||||
|
||||
/* FXIME check how to pack structure members */
|
||||
#define IFX_PACKED
|
||||
|
||||
#define COMPILER_NAME "DCC"
|
||||
#define COMPILER_VERSION __VERSION__
|
||||
|
||||
#define COMPILER_REVISION 0
|
||||
#define IFX_INTERRUPT_FAST IFX_INTERRUPT
|
||||
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
|
||||
#endif
|
||||
|
||||
#else
|
||||
/* *INDENT-OFF* */
|
||||
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
|
||||
#endif
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
|
||||
|
||||
#ifndef IFX_INTERRUPT_INTERNAL
|
||||
#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) \
|
||||
void __interrupt(prio) __vector_table(vectabNum) isr(void)
|
||||
#endif
|
||||
|
||||
/*Macro IFX_INTERRUPT_LEGACY is to be used for compiler version pror to 5.9.3.0*/
|
||||
#define IFX_INTERRUPT_LEGACY(isr, vectabNum, prio) \
|
||||
__asm ("\t.align\t 5\n\t\
|
||||
.section .int."#prio"\n \t.sectionlink .inttab"#vectabNum".intvec."#prio"\n\
|
||||
#$$bf\n\
|
||||
__intvec_tc"#vectabNum"_"#prio":\n\
|
||||
movh.a\t %a14,"#isr"@ha\n\
|
||||
lea\t %a14,[%a14]"#isr"@l\n\
|
||||
ji\t %a14\n\
|
||||
#$$ef\n\t\
|
||||
.section .intend."#prio"\n \t.sectionlink .text");\
|
||||
__interrupt__ void isr (void)
|
||||
|
||||
/* *INDENT-ON* */
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#define IFX_ALIGN(n) __attribute__ ((aligned(n)))
|
||||
|
||||
/******************************************************************************/
|
||||
/*Memory qualifiers*/
|
||||
#ifndef IFX_FAR_ABS
|
||||
#define IFX_FAR_ABS
|
||||
#endif
|
||||
|
||||
#ifndef IFX_NEAR_ABS
|
||||
#define IFX_NEAR_ABS
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A0
|
||||
#define IFX_REL_A0
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A1
|
||||
#define IFX_REL_A1
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A8
|
||||
#define IFX_REL_A8
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A9
|
||||
#define IFX_REL_A9
|
||||
#endif
|
||||
/******************************************************************************/
|
||||
|
||||
#endif /* COMPILERDCC_H */
|
||||
@@ -1,113 +0,0 @@
|
||||
/**
|
||||
* \file CompilerGhs.c
|
||||
*
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* $Date: 2014-02-27 20:08:40 GMT$
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#include "Cpu/Std/Ifx_Types.h"
|
||||
#include "Compilers.h"
|
||||
|
||||
#if defined(__ghs__) && !defined(WIN32)
|
||||
|
||||
typedef int ptrdiff_t;
|
||||
typedef unsigned int syze_t;
|
||||
typedef signed int signed_size_t;
|
||||
#define size_t syze_t
|
||||
|
||||
extern void *memcpy(void *s1, const void *s2, syze_t n);
|
||||
extern void *memset(void *s, int c, syze_t n);
|
||||
|
||||
/* rodata is absolute */
|
||||
typedef const char rodata_ptr[];
|
||||
# define PIRBASE 0
|
||||
|
||||
#define CONST_FUNCP *const
|
||||
|
||||
/*!
|
||||
* \brief Initializes C variables.
|
||||
*
|
||||
* This function is called in the startup. This function initialize the all variables in .data section
|
||||
* and clears the .bss section
|
||||
*
|
||||
* Parameters: Nil
|
||||
* Return: Nil
|
||||
*/
|
||||
void Ifx_C_Init(void)
|
||||
{
|
||||
/*----------------------------------------------------------------------*/
|
||||
/* */
|
||||
/* Clear BSS */
|
||||
/* */
|
||||
/*----------------------------------------------------------------------*/
|
||||
{ /* The .secinfo section is in text; declare functions to force PIC */
|
||||
|
||||
#pragma ghs rodata
|
||||
extern rodata_ptr __ghsbinfo_clear;
|
||||
#pragma ghs rodata
|
||||
extern rodata_ptr __ghseinfo_clear;
|
||||
|
||||
void **b = (void **) ((char *)__ghsbinfo_clear);
|
||||
void **e = (void **) ((char *)__ghseinfo_clear);
|
||||
|
||||
while (b != e) {
|
||||
void * t; /* target pointer */
|
||||
ptrdiff_t v; /* value to set */
|
||||
size_t n; /* set n bytes */
|
||||
t = (char *)(*b++);
|
||||
v = *((ptrdiff_t *) b); b++;
|
||||
n = *((size_t *) b); b++;
|
||||
memset(t, v, n);
|
||||
}
|
||||
}
|
||||
|
||||
/*----------------*/
|
||||
/* initialize iob */
|
||||
/*----------------*/
|
||||
{
|
||||
#pragma weak __gh_iob_init
|
||||
extern void __gh_iob_init(void);
|
||||
static void (CONST_FUNCP iob_init_funcp)(void) = __gh_iob_init;
|
||||
/* if cciob.c is loaded, initialize _iob for stdin,stdout,stderr */
|
||||
if (iob_init_funcp) __gh_iob_init();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -1,173 +0,0 @@
|
||||
/**
|
||||
* \file CompilerGhs.h
|
||||
*
|
||||
* \version iLLD_New
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef COMPILERGHS_H
|
||||
#define COMPILERGHS_H 1
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
// #include <stddef.h>
|
||||
|
||||
/*Linker definitions which are specific to Ghs */
|
||||
/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
|
||||
* to use the default compiler linker varaibles and startup */
|
||||
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
|
||||
|
||||
/*Start: Common definitions ********************************************** */
|
||||
#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
|
||||
extern unsigned int __A0_MEM[]; /**< center of A0 addressable area */ \
|
||||
extern unsigned int __A1_MEM[]; /**< center of A1 addressable area */ \
|
||||
extern unsigned int __A8_MEM[]; /**< center of A8 addressable area */ \
|
||||
extern unsigned int __A9_MEM[]; /**< center of A9 addressable area */
|
||||
|
||||
/*End: Common definitions ************************************************ */
|
||||
|
||||
/*Start: Core 0 definitions ********************************************** */
|
||||
|
||||
/*C extern defintions */
|
||||
#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
|
||||
extern unsigned int __USTACK##cpu[]; /**< user stack end */ \
|
||||
extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
|
||||
extern unsigned int __INTTAB_CPU##cpu[]; /**< Interrupt vector table */ \
|
||||
extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap table */ \
|
||||
extern unsigned int __CSA##cpu[]; /**< context save area 1 begin */ \
|
||||
extern unsigned int __CSA##cpu##_END[]; /**< context save area 1 begin */
|
||||
|
||||
#define __USTACK(cpu) __USTACK##cpu
|
||||
#define __ISTACK(cpu) __ISTACK##cpu
|
||||
#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
|
||||
#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
|
||||
#define __CSA(cpu) __CSA##cpu
|
||||
#define __CSA_END(cpu) __CSA##cpu##_END
|
||||
|
||||
/*Wrapper macros for the tool specific definitions */
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
|
||||
#else
|
||||
#define __INTTAB(cpu) __INTTAB_CPU##cpu
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT) */
|
||||
|
||||
#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
|
||||
|
||||
#define __SDATA1(cpu) __A0_MEM
|
||||
#define __SDATA2(cpu) __A1_MEM
|
||||
#define __SDATA3(cpu) __A8_MEM
|
||||
#define __SDATA4(cpu) __A9_MEM
|
||||
|
||||
/* MHWS+
|
||||
#define __SDATA1(cpu) __A0_MEM
|
||||
#define __SDATA2(cpu) __A1_MEM
|
||||
#define __SDATA3(cpu) __A8_MEM
|
||||
#define __SDATA4(cpu) __A9_MEM
|
||||
MHWS- */
|
||||
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
|
||||
|
||||
/******************************************************************************/
|
||||
#ifndef IFX_INLINE
|
||||
#define IFX_INLINE static inline __attribute__ ((always_inline)) /*Makes the function always inlined */
|
||||
#endif
|
||||
|
||||
#define IFX_PACKED __packed
|
||||
|
||||
#define COMPILER_NAME "GHS"
|
||||
#define COMPILER_VERSION __GHS_VERSION_NUMBER
|
||||
|
||||
#define COMPILER_REVISION __GHS_REVISION_VALUE
|
||||
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
|
||||
#endif
|
||||
|
||||
#else
|
||||
/* *INDENT-OFF* */
|
||||
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
|
||||
#endif
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
|
||||
|
||||
#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) \
|
||||
__attribute__((section(".intvec_tc"#vectabNum"_"#prio))) void iVecEntry##vectabNum##_##prio(void) \
|
||||
{ \
|
||||
__asm__("movh.a a14, %hi("#isr") \n" \
|
||||
"lea a14, [a14]%lo("#isr")\n" \
|
||||
"ji a14"); \
|
||||
} \
|
||||
__interrupt void isr(void)
|
||||
|
||||
/* *INDENT-ON* */
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#define IFX_ALIGN(n) __attribute__ ((aligned(n)))
|
||||
|
||||
/******************************************************************************/
|
||||
/*Memory qualifiers*/
|
||||
#ifndef IFX_FAR_ABS
|
||||
#define IFX_FAR_ABS __attribute__((fardata))
|
||||
#endif
|
||||
|
||||
#ifndef IFX_NEAR_ABS
|
||||
#define IFX_NEAR_ABS
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A0
|
||||
#define IFX_REL_A0
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A1
|
||||
#define IFX_REL_A1
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A8
|
||||
#define IFX_REL_A8
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A9
|
||||
#define IFX_REL_A9
|
||||
#endif
|
||||
/******************************************************************************/
|
||||
|
||||
#endif /* COMPILERGHS_H */
|
||||
@@ -1,153 +0,0 @@
|
||||
/**
|
||||
* \file CompilerGnuc.c
|
||||
*
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* $Date: 2014-02-27 20:08:40 GMT$
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#include "Cpu/Std/Ifx_Types.h"
|
||||
#include "Compilers.h"
|
||||
|
||||
#if defined(__HIGHTEC__) && !defined(WIN32)
|
||||
/*!
|
||||
* \brief Data s C variables.
|
||||
*/
|
||||
extern uint32 __clear_table[]; /**< clear table entry */
|
||||
extern uint32 __copy_table[]; /**< copy table entry */
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
uint8 *ucPtr;
|
||||
uint16 *usPtr;
|
||||
uint32 *uiPtr;
|
||||
unsigned long long *ullPtr;
|
||||
} IfxStart_CTablePtr;
|
||||
|
||||
/*!
|
||||
* \brief Initializes C variables.
|
||||
*
|
||||
* This function is called in the startup. This function initialize the all variables in .data section
|
||||
* and clears the .bss section
|
||||
*
|
||||
* Parameters: Nil
|
||||
* Return: Nil
|
||||
*/
|
||||
void Ifx_C_Init(void)
|
||||
{
|
||||
IfxStart_CTablePtr pBlockDest, pBlockSrc;
|
||||
uint32 uiLength, uiCnt;
|
||||
uint32 *pTable;
|
||||
/* clear table */
|
||||
pTable = (uint32 *)&__clear_table;
|
||||
|
||||
while (pTable)
|
||||
{
|
||||
pBlockDest.uiPtr = (uint32 *)*pTable++;
|
||||
uiLength = *pTable++;
|
||||
|
||||
/* we are finished when length == -1 */
|
||||
if (uiLength == 0xFFFFFFFF)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
uiCnt = uiLength / 8;
|
||||
|
||||
while (uiCnt--)
|
||||
{
|
||||
*pBlockDest.ullPtr++ = 0;
|
||||
}
|
||||
|
||||
if (uiLength & 0x4)
|
||||
{
|
||||
*pBlockDest.uiPtr++ = 0;
|
||||
}
|
||||
|
||||
if (uiLength & 0x2)
|
||||
{
|
||||
*pBlockDest.usPtr++ = 0;
|
||||
}
|
||||
|
||||
if (uiLength & 0x1)
|
||||
{
|
||||
*pBlockDest.ucPtr = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* copy table */
|
||||
pTable = (uint32 *)&__copy_table;
|
||||
|
||||
while (pTable)
|
||||
{
|
||||
pBlockSrc.uiPtr = (uint32 *)*pTable++;
|
||||
pBlockDest.uiPtr = (uint32 *)*pTable++;
|
||||
uiLength = *pTable++;
|
||||
|
||||
/* we are finished when length == -1 */
|
||||
if (uiLength == 0xFFFFFFFF)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
uiCnt = uiLength / 8;
|
||||
|
||||
while (uiCnt--)
|
||||
{
|
||||
*pBlockDest.ullPtr++ = *pBlockSrc.ullPtr++;
|
||||
}
|
||||
|
||||
if (uiLength & 0x4)
|
||||
{
|
||||
*pBlockDest.uiPtr++ = *pBlockSrc.uiPtr++;
|
||||
}
|
||||
|
||||
if (uiLength & 0x2)
|
||||
{
|
||||
*pBlockDest.usPtr++ = *pBlockSrc.usPtr++;
|
||||
}
|
||||
|
||||
if (uiLength & 0x1)
|
||||
{
|
||||
*pBlockDest.ucPtr = *pBlockSrc.ucPtr;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -1,186 +0,0 @@
|
||||
/**
|
||||
* \file CompilerGnuc.h
|
||||
*
|
||||
* \version iLLD_New
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef COMPILERGNUC_H
|
||||
#define COMPILERGNUC_H 1
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
/*Linker definitions which are specific to Gnuc */
|
||||
/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
|
||||
* to use the default compiler linker varaibles and startup */
|
||||
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
|
||||
|
||||
/*Start: Common definitions ********************************************** */
|
||||
#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
|
||||
extern unsigned int __A0_MEM[]; /**< center of A0 addressable area */ \
|
||||
extern unsigned int __A1_MEM[]; /**< center of A1 addressable area */ \
|
||||
extern unsigned int __A8_MEM[]; /**< center of A8 addressable area */ \
|
||||
extern unsigned int __A9_MEM[]; /**< center of A9 addressable area */
|
||||
|
||||
/*End: Common definitions ************************************************ */
|
||||
|
||||
/*Start: Core 0 definitions ********************************************** */
|
||||
|
||||
/*C extern defintions */
|
||||
#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
|
||||
extern unsigned int __USTACK##cpu[]; /**< user stack end */ \
|
||||
extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
|
||||
extern unsigned int __INTTAB_CPU##cpu[]; /**< Interrupt vector table */ \
|
||||
extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap table */ \
|
||||
extern unsigned int __CSA##cpu[]; /**< context save area 1 begin */ \
|
||||
extern unsigned int __CSA##cpu##_END[]; /**< context save area 1 begin */
|
||||
|
||||
#define __USTACK(cpu) __USTACK##cpu
|
||||
#define __ISTACK(cpu) __ISTACK##cpu
|
||||
#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
|
||||
#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
|
||||
#define __CSA(cpu) __CSA##cpu
|
||||
#define __CSA_END(cpu) __CSA##cpu##_END
|
||||
|
||||
/*Wrapper macros for the tool specific definitions */
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
|
||||
#else
|
||||
#define __INTTAB(cpu) __INTTAB_CPU##cpu
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT) */
|
||||
|
||||
#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
|
||||
|
||||
#define __SDATA1(cpu) __A0_MEM
|
||||
#define __SDATA2(cpu) __A1_MEM
|
||||
#define __SDATA3(cpu) __A8_MEM
|
||||
#define __SDATA4(cpu) __A9_MEM
|
||||
|
||||
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
|
||||
|
||||
/******************************************************************************/
|
||||
#ifndef IFX_INLINE
|
||||
#define IFX_INLINE static inline __attribute__ ((always_inline)) /*Makes the function always inlined */
|
||||
#endif
|
||||
|
||||
#define IFX_PACKED __attribute__ ((packed))
|
||||
|
||||
#define COMPILER_NAME "GNUC"
|
||||
#define COMPILER_VERSION __VERSION__
|
||||
|
||||
#define COMPILER_REVISION 0
|
||||
|
||||
#define IFX_INTERRUPT_FAST IFX_INTERRUPT
|
||||
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
|
||||
#endif
|
||||
|
||||
#else
|
||||
/* *INDENT-OFF* */
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
|
||||
#endif
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
|
||||
|
||||
#ifndef IFX_INTERRUPT_INTERNAL
|
||||
#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) \
|
||||
__asm__ (".ifndef .intr.entry.include \n"\
|
||||
".altmacro \n"\
|
||||
".macro .int_entry.2 intEntryLabel, name # define the section and inttab entry code \n"\
|
||||
" .pushsection .\\intEntryLabel,\"ax\",@progbits \n"\
|
||||
" __\\intEntryLabel : \n"\
|
||||
" svlcx \n"\
|
||||
" movh.a %a14, hi:\\name \n"\
|
||||
" lea %a14, [%a14]lo:\\name \n"\
|
||||
" ji %a14 \n"\
|
||||
" .popsection \n"\
|
||||
".endm \n"\
|
||||
".macro .int_entry.1 prio,vectabNum,u,name \n"\
|
||||
".int_entry.2 intvec_tc\\vectabNum\\u\\prio,(name) # build the unique name \n"\
|
||||
".endm \n"\
|
||||
" \n"\
|
||||
".macro .intr.entry name,vectabNum,prio \n"\
|
||||
".int_entry.1 %(prio),%(vectabNum),_,name # evaluate the priority and the cpu number \n"\
|
||||
".endm \n"\
|
||||
".intr.entry.include: \n"\
|
||||
".endif \n"\
|
||||
".intr.entry "#isr","#vectabNum","#prio );\
|
||||
IFX_EXTERN void __attribute__ ((interrupt_handler)) isr(); \
|
||||
void isr (void)
|
||||
#endif /* IFX_INTERRUPT_INTERNAL */
|
||||
|
||||
/* *INDENT-ON* */
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#define IFX_ALIGN(n) __attribute__ ((aligned(n)))
|
||||
|
||||
/******************************************************************************/
|
||||
/*Memory qualifiers*/
|
||||
#ifndef IFX_FAR_ABS
|
||||
#define IFX_FAR_ABS __attribute__((fardata))
|
||||
#endif
|
||||
|
||||
#ifndef IFX_NEAR_ABS
|
||||
#define IFX_NEAR_ABS
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A0
|
||||
#define IFX_REL_A0
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A1
|
||||
#define IFX_REL_A1
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A8
|
||||
#define IFX_REL_A8
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A9
|
||||
#define IFX_REL_A9
|
||||
#endif
|
||||
/******************************************************************************/
|
||||
|
||||
#endif /* COMPILERGNUC_H */
|
||||
@@ -1,65 +0,0 @@
|
||||
/**
|
||||
* \file CompilerTasking.c
|
||||
*
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* $Date: 2014-02-27 20:08:41 GMT$
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#include "Cpu/Std/Ifx_Types.h"
|
||||
#include "Compilers.h"
|
||||
|
||||
#if defined(__TASKING__)
|
||||
/*!
|
||||
* \brief Initializes C variables
|
||||
*
|
||||
* This function is called in the startup. This function initialize the all variables in .data section
|
||||
* and clears the .bss section
|
||||
*
|
||||
* Parameters: Nil
|
||||
* Return: Nil
|
||||
*/
|
||||
void Ifx_C_Init(void)
|
||||
{
|
||||
extern void _c_init(void);
|
||||
|
||||
_c_init(); /* initialize data */
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -1,165 +0,0 @@
|
||||
/**
|
||||
* \file CompilerTasking.h
|
||||
*
|
||||
* \version iLLD_New
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef COMPILERTASKING_H
|
||||
#define COMPILERTASKING_H 1
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
/*Linker definitions which are specific to Tasking */
|
||||
/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
|
||||
* to use the default compiler linker varaibles and startup */
|
||||
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
|
||||
|
||||
#ifndef __cplusplus
|
||||
/*Start: Common definitions ********************************************** */
|
||||
#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
|
||||
__asm("\t .extern _SMALL_DATA_, _LITERAL_DATA_, _A8_DATA_, _A9_DATA_");
|
||||
|
||||
/*End: Common definitions ********************************************** */
|
||||
|
||||
/*Start: Core 0 definitions ********************************************** */
|
||||
|
||||
#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
|
||||
__asm("\t .extern __USTACK"#cpu); /**< user stack end is required as asm to be used with setreg macro */ \
|
||||
extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
|
||||
extern unsigned int __INTTAB_CPU##cpu[]; /**< interrupt vector table */ \
|
||||
extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap vector table */ \
|
||||
extern unsigned int __CSA##cpu[]; /**< context save area begin */ \
|
||||
extern unsigned int __CSA##cpu##_END[]; /**< context save area end */
|
||||
#endif
|
||||
|
||||
#define __USTACK(cpu) __USTACK##cpu
|
||||
#define __ISTACK(cpu) __ISTACK##cpu
|
||||
#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
|
||||
#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
|
||||
#define __CSA(cpu) __CSA##cpu
|
||||
#define __CSA_END(cpu) __CSA##cpu##_END
|
||||
|
||||
/*Wrapper macros for the tool specific definitions */
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
|
||||
#else
|
||||
#define __INTTAB(cpu) __INTTAB_CPU##cpu
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT) */
|
||||
|
||||
#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
|
||||
|
||||
#define __SDATA1(cpu) _SMALL_DATA_
|
||||
#define __SDATA2(cpu) _LITERAL_DATA_
|
||||
#define __SDATA3(cpu) _A8_DATA_
|
||||
#define __SDATA4(cpu) _A9_DATA_
|
||||
|
||||
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
|
||||
|
||||
/******************************************************************************/
|
||||
#ifdef __cplusplus
|
||||
#define IFX_INLINE static inline
|
||||
#else
|
||||
#define IFX_INLINE inline
|
||||
#endif
|
||||
|
||||
/* FXIME check how to pack structure members */
|
||||
#define IFX_PACKED
|
||||
|
||||
#define COMPILER_NAME "TASKING"
|
||||
#define COMPILER_VERSION __VERSION__
|
||||
|
||||
/* Note that __REVISION__ is only available for tasking compiler! */
|
||||
#define COMPILER_REVISION __REVISION__
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
|
||||
#endif
|
||||
|
||||
#else
|
||||
/* *INDENT-OFF* */
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
|
||||
#endif
|
||||
#define IFX_INTERRUPT_FAST(isr, vectabNum, prio) void __interrupt_fast(prio) __vector_table(vectabNum) isr(void)
|
||||
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
|
||||
|
||||
#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) void __interrupt(prio) __vector_table(vectabNum) isr(void)
|
||||
|
||||
/* *INDENT-ON* */
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#define IFX_ALIGN(n) __attribute__ ((__align(n)))
|
||||
|
||||
/******************************************************************************/
|
||||
/*Memory qualifiers*/
|
||||
#ifndef IFX_FAR_ABS
|
||||
#define IFX_FAR_ABS __far
|
||||
#endif
|
||||
|
||||
#ifndef IFX_NEAR_ABS
|
||||
#define IFX_NEAR_ABS __near
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A0
|
||||
#define IFX_REL_A0 __a0
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A1
|
||||
#define IFX_REL_A1 __a1
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A8
|
||||
#define IFX_REL_A8 __a8
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A9
|
||||
#define IFX_REL_A9 __a9
|
||||
#endif
|
||||
/******************************************************************************/
|
||||
|
||||
#endif /* COMPILERTASKING_H */
|
||||
@@ -1,144 +0,0 @@
|
||||
/**
|
||||
* \file Compilers.h
|
||||
*
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* $Date: 2014-04-07 12:13:19 GMT$
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef COMPILERS_H
|
||||
#define COMPILERS_H 1
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#include "Ifx_Cfg.h"
|
||||
|
||||
/*this file shall not be modified by the user, IFX_XXXX defines shall be defined in Ifx_Cfg.h */
|
||||
#ifndef IFX_STATIC
|
||||
#define IFX_STATIC static
|
||||
#endif
|
||||
|
||||
#ifndef IFX_CONST
|
||||
#define IFX_CONST const
|
||||
#endif
|
||||
#ifndef CONST_CFG
|
||||
#define CONST_CFG const /* configuration constants are stored in ROM */
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define IFX_EXTERN extern "C"
|
||||
#else
|
||||
#define IFX_EXTERN extern
|
||||
#endif
|
||||
|
||||
#ifndef NULL_PTR
|
||||
#ifdef __cplusplus
|
||||
#define NULL_PTR (0)
|
||||
#else /*#ifdef __cplusplus */
|
||||
#define NULL_PTR ((void *)0)
|
||||
#endif /*#ifdef __cplusplus */
|
||||
#endif /*#ifndef NULL_PTR */
|
||||
|
||||
#ifndef CFG_LONG_SIZE_T
|
||||
#define CFG_LONG_SIZE_T (0)
|
||||
#endif
|
||||
|
||||
#if defined(__DCC__)
|
||||
#include "CompilerDcc.h"
|
||||
|
||||
#elif defined(__HIGHTEC__)
|
||||
#include "CompilerGnuc.h"
|
||||
|
||||
#elif defined(__TASKING__)
|
||||
#include "CompilerTasking.h"
|
||||
|
||||
#elif defined(__ghs__)
|
||||
#include "CompilerGhs.h"
|
||||
|
||||
#elif defined(__MSVC__)
|
||||
#include "CompilerMsvc.h"
|
||||
|
||||
#else
|
||||
|
||||
/** \addtogroup IfxLld_Cpu_Std_Interrupt
|
||||
* \{ */
|
||||
/** \brief Macro to define Interrupt Service Routine.
|
||||
* This macro makes following definitions:\n
|
||||
* 1) Define linker section as .intvec_tc<vector number>_<interrupt priority>.\n
|
||||
* 2) define compiler specific attribute for the interrupt functions.\n
|
||||
* 3) define the Interrupt service routine as Isr function.\n
|
||||
* To get details about usage of this macro, refer \ref IfxLld_Cpu_Irq_Usage
|
||||
*
|
||||
* \param isr Name of the Isr function.
|
||||
* \param vectabNum Vector table number.
|
||||
* \param prio Interrupt priority. Refer Usage of Interrupt Macro for more details.
|
||||
*/
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio)
|
||||
|
||||
/** \} */
|
||||
#error "Compiler unsupported"
|
||||
#endif
|
||||
|
||||
#if defined(__HIGHTEC__)
|
||||
#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section #sec aw 4)
|
||||
#define DATA_SECTION(sec) _Pragma(#sec)
|
||||
#define END_DATA_SECTION DATA_SECTION(section)
|
||||
#elif defined(__TASKING__)
|
||||
#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section farbss #sec)
|
||||
#define DATA_SECTION(sec) _Pragma(#sec)
|
||||
#define END_DATA_SECTION DATA_SECTION(section farbss align restore) \
|
||||
DATA_SECTION(section farbss)
|
||||
#elif defined(__DCC__)
|
||||
#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section #sec WX)
|
||||
#define DATA_SECTION(sec) _Pragma(#sec)
|
||||
#define END_DATA_SECTION DATA_SECTION(section DATA X)
|
||||
#elif defined(__ghs__)
|
||||
#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section #sec WX)
|
||||
#define DATA_SECTION(sec) _Pragma(#sec)
|
||||
#define END_DATA_SECTION DATA_SECTION(section DATA X)
|
||||
#else
|
||||
#error "Please specify compiler."
|
||||
#endif
|
||||
|
||||
/* Functions prototypes */
|
||||
/******************************************************************************/
|
||||
void Ifx_C_Init(void);
|
||||
/******************************************************************************/
|
||||
|
||||
|
||||
#endif /* COMPILERS_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,468 +0,0 @@
|
||||
/**
|
||||
* \file IfxAsclin_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_Cfg Asclin address
|
||||
* \ingroup IfxLld_Asclin
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Asclin_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_Cfg_Asclin0 2-ASCLIN0
|
||||
* \ingroup IfxLld_Asclin_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_Cfg_Asclin1 2-ASCLIN1
|
||||
* \ingroup IfxLld_Asclin_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_Cfg_Asclin2 2-ASCLIN2
|
||||
* \ingroup IfxLld_Asclin_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_Cfg_Asclin3 2-ASCLIN3
|
||||
* \ingroup IfxLld_Asclin_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXASCLIN_REG_H
|
||||
#define IFXASCLIN_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxAsclin_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief ASCLIN object */
|
||||
#define MODULE_ASCLIN0 /*lint --e(923)*/ (*(Ifx_ASCLIN*)0xF0000600u)
|
||||
|
||||
/** \brief ASCLIN object */
|
||||
#define MODULE_ASCLIN1 /*lint --e(923)*/ (*(Ifx_ASCLIN*)0xF0000700u)
|
||||
|
||||
/** \brief ASCLIN object */
|
||||
#define MODULE_ASCLIN2 /*lint --e(923)*/ (*(Ifx_ASCLIN*)0xF0000800u)
|
||||
|
||||
/** \brief ASCLIN object */
|
||||
#define MODULE_ASCLIN3 /*lint --e(923)*/ (*(Ifx_ASCLIN*)0xF0000900u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_Cfg_Asclin0
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define ASCLIN0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00006FCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define ASCLIN0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00006F8u)
|
||||
|
||||
/** \brief 14, Bit Configuration Register */
|
||||
#define ASCLIN0_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000614u)
|
||||
|
||||
/** \brief 24, Baud Rate Detection Register */
|
||||
#define ASCLIN0_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000624u)
|
||||
|
||||
/** \brief 20, Baud Rate Generation Register */
|
||||
#define ASCLIN0_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000620u)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define ASCLIN0_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000600u)
|
||||
|
||||
/** \brief 4C, Clock Selection Register */
|
||||
#define ASCLIN0_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000064Cu)
|
||||
|
||||
/** \brief 1C, Data Configuration Register */
|
||||
#define ASCLIN0_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000061Cu)
|
||||
|
||||
/** \brief 34, Flags Register */
|
||||
#define ASCLIN0_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000634u)
|
||||
|
||||
/** \brief 3C, Flags Clear Register */
|
||||
#define ASCLIN0_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000063Cu)
|
||||
|
||||
/** \brief 40, Flags Enable Register */
|
||||
#define ASCLIN0_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000640u)
|
||||
|
||||
/** \brief 38, Flags Set Register */
|
||||
#define ASCLIN0_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000638u)
|
||||
|
||||
/** \brief 18, Frame Control Register */
|
||||
#define ASCLIN0_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000618u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define ASCLIN0_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000608u)
|
||||
|
||||
/** \brief 4, Input and Output Control Register */
|
||||
#define ASCLIN0_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000604u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define ASCLIN0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00006F4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define ASCLIN0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00006F0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define ASCLIN0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00006ECu)
|
||||
|
||||
/** \brief 2C, LIN Break Timer Register */
|
||||
#define ASCLIN0_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000062Cu)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN0_LIN_BTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN0_LIN_BTIMER.
|
||||
*/
|
||||
#define ASCLIN0_LINBTIMER (ASCLIN0_LIN_BTIMER)
|
||||
|
||||
/** \brief 28, LIN Control Register */
|
||||
#define ASCLIN0_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000628u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN0_LIN_CON.
|
||||
* To use register names with standard convension, please use ASCLIN0_LIN_CON.
|
||||
*/
|
||||
#define ASCLIN0_LINCON (ASCLIN0_LIN_CON)
|
||||
|
||||
/** \brief 30, LIN Header Timer Register */
|
||||
#define ASCLIN0_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000630u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN0_LIN_HTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN0_LIN_HTIMER.
|
||||
*/
|
||||
#define ASCLIN0_LINHTIMER (ASCLIN0_LIN_HTIMER)
|
||||
|
||||
/** \brief E8, OCDS Control and Status */
|
||||
#define ASCLIN0_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00006E8u)
|
||||
|
||||
/** \brief 48, Receive Data Register */
|
||||
#define ASCLIN0_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000648u)
|
||||
|
||||
/** \brief 50, Receive Data Debug Register */
|
||||
#define ASCLIN0_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000650u)
|
||||
|
||||
/** \brief 10, RX FIFO Configuration Register */
|
||||
#define ASCLIN0_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000610u)
|
||||
|
||||
/** \brief 44, Transmit Data Register */
|
||||
#define ASCLIN0_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000644u)
|
||||
|
||||
/** \brief C, TX FIFO Configuration Register */
|
||||
#define ASCLIN0_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000060Cu)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_Cfg_Asclin1
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define ASCLIN1_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00007FCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define ASCLIN1_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00007F8u)
|
||||
|
||||
/** \brief 14, Bit Configuration Register */
|
||||
#define ASCLIN1_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000714u)
|
||||
|
||||
/** \brief 24, Baud Rate Detection Register */
|
||||
#define ASCLIN1_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000724u)
|
||||
|
||||
/** \brief 20, Baud Rate Generation Register */
|
||||
#define ASCLIN1_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000720u)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define ASCLIN1_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000700u)
|
||||
|
||||
/** \brief 4C, Clock Selection Register */
|
||||
#define ASCLIN1_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000074Cu)
|
||||
|
||||
/** \brief 1C, Data Configuration Register */
|
||||
#define ASCLIN1_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000071Cu)
|
||||
|
||||
/** \brief 34, Flags Register */
|
||||
#define ASCLIN1_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000734u)
|
||||
|
||||
/** \brief 3C, Flags Clear Register */
|
||||
#define ASCLIN1_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000073Cu)
|
||||
|
||||
/** \brief 40, Flags Enable Register */
|
||||
#define ASCLIN1_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000740u)
|
||||
|
||||
/** \brief 38, Flags Set Register */
|
||||
#define ASCLIN1_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000738u)
|
||||
|
||||
/** \brief 18, Frame Control Register */
|
||||
#define ASCLIN1_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000718u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define ASCLIN1_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000708u)
|
||||
|
||||
/** \brief 4, Input and Output Control Register */
|
||||
#define ASCLIN1_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000704u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define ASCLIN1_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00007F4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define ASCLIN1_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00007F0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define ASCLIN1_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00007ECu)
|
||||
|
||||
/** \brief 2C, LIN Break Timer Register */
|
||||
#define ASCLIN1_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000072Cu)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN1_LIN_BTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN1_LIN_BTIMER.
|
||||
*/
|
||||
#define ASCLIN1_LINBTIMER (ASCLIN1_LIN_BTIMER)
|
||||
|
||||
/** \brief 28, LIN Control Register */
|
||||
#define ASCLIN1_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000728u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN1_LIN_CON.
|
||||
* To use register names with standard convension, please use ASCLIN1_LIN_CON.
|
||||
*/
|
||||
#define ASCLIN1_LINCON (ASCLIN1_LIN_CON)
|
||||
|
||||
/** \brief 30, LIN Header Timer Register */
|
||||
#define ASCLIN1_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000730u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN1_LIN_HTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN1_LIN_HTIMER.
|
||||
*/
|
||||
#define ASCLIN1_LINHTIMER (ASCLIN1_LIN_HTIMER)
|
||||
|
||||
/** \brief E8, OCDS Control and Status */
|
||||
#define ASCLIN1_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00007E8u)
|
||||
|
||||
/** \brief 48, Receive Data Register */
|
||||
#define ASCLIN1_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000748u)
|
||||
|
||||
/** \brief 50, Receive Data Debug Register */
|
||||
#define ASCLIN1_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000750u)
|
||||
|
||||
/** \brief 10, RX FIFO Configuration Register */
|
||||
#define ASCLIN1_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000710u)
|
||||
|
||||
/** \brief 44, Transmit Data Register */
|
||||
#define ASCLIN1_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000744u)
|
||||
|
||||
/** \brief C, TX FIFO Configuration Register */
|
||||
#define ASCLIN1_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000070Cu)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_Cfg_Asclin2
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define ASCLIN2_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00008FCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define ASCLIN2_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00008F8u)
|
||||
|
||||
/** \brief 14, Bit Configuration Register */
|
||||
#define ASCLIN2_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000814u)
|
||||
|
||||
/** \brief 24, Baud Rate Detection Register */
|
||||
#define ASCLIN2_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000824u)
|
||||
|
||||
/** \brief 20, Baud Rate Generation Register */
|
||||
#define ASCLIN2_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000820u)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define ASCLIN2_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000800u)
|
||||
|
||||
/** \brief 4C, Clock Selection Register */
|
||||
#define ASCLIN2_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000084Cu)
|
||||
|
||||
/** \brief 1C, Data Configuration Register */
|
||||
#define ASCLIN2_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000081Cu)
|
||||
|
||||
/** \brief 34, Flags Register */
|
||||
#define ASCLIN2_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000834u)
|
||||
|
||||
/** \brief 3C, Flags Clear Register */
|
||||
#define ASCLIN2_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000083Cu)
|
||||
|
||||
/** \brief 40, Flags Enable Register */
|
||||
#define ASCLIN2_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000840u)
|
||||
|
||||
/** \brief 38, Flags Set Register */
|
||||
#define ASCLIN2_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000838u)
|
||||
|
||||
/** \brief 18, Frame Control Register */
|
||||
#define ASCLIN2_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000818u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define ASCLIN2_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000808u)
|
||||
|
||||
/** \brief 4, Input and Output Control Register */
|
||||
#define ASCLIN2_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000804u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define ASCLIN2_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00008F4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define ASCLIN2_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00008F0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define ASCLIN2_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00008ECu)
|
||||
|
||||
/** \brief 2C, LIN Break Timer Register */
|
||||
#define ASCLIN2_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000082Cu)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN2_LIN_BTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN2_LIN_BTIMER.
|
||||
*/
|
||||
#define ASCLIN2_LINBTIMER (ASCLIN2_LIN_BTIMER)
|
||||
|
||||
/** \brief 28, LIN Control Register */
|
||||
#define ASCLIN2_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000828u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN2_LIN_CON.
|
||||
* To use register names with standard convension, please use ASCLIN2_LIN_CON.
|
||||
*/
|
||||
#define ASCLIN2_LINCON (ASCLIN2_LIN_CON)
|
||||
|
||||
/** \brief 30, LIN Header Timer Register */
|
||||
#define ASCLIN2_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000830u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN2_LIN_HTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN2_LIN_HTIMER.
|
||||
*/
|
||||
#define ASCLIN2_LINHTIMER (ASCLIN2_LIN_HTIMER)
|
||||
|
||||
/** \brief E8, OCDS Control and Status */
|
||||
#define ASCLIN2_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00008E8u)
|
||||
|
||||
/** \brief 48, Receive Data Register */
|
||||
#define ASCLIN2_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000848u)
|
||||
|
||||
/** \brief 50, Receive Data Debug Register */
|
||||
#define ASCLIN2_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000850u)
|
||||
|
||||
/** \brief 10, RX FIFO Configuration Register */
|
||||
#define ASCLIN2_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000810u)
|
||||
|
||||
/** \brief 44, Transmit Data Register */
|
||||
#define ASCLIN2_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000844u)
|
||||
|
||||
/** \brief C, TX FIFO Configuration Register */
|
||||
#define ASCLIN2_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000080Cu)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_Cfg_Asclin3
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define ASCLIN3_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00009FCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define ASCLIN3_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00009F8u)
|
||||
|
||||
/** \brief 14, Bit Configuration Register */
|
||||
#define ASCLIN3_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000914u)
|
||||
|
||||
/** \brief 24, Baud Rate Detection Register */
|
||||
#define ASCLIN3_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000924u)
|
||||
|
||||
/** \brief 20, Baud Rate Generation Register */
|
||||
#define ASCLIN3_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000920u)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define ASCLIN3_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000900u)
|
||||
|
||||
/** \brief 4C, Clock Selection Register */
|
||||
#define ASCLIN3_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000094Cu)
|
||||
|
||||
/** \brief 1C, Data Configuration Register */
|
||||
#define ASCLIN3_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000091Cu)
|
||||
|
||||
/** \brief 34, Flags Register */
|
||||
#define ASCLIN3_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000934u)
|
||||
|
||||
/** \brief 3C, Flags Clear Register */
|
||||
#define ASCLIN3_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000093Cu)
|
||||
|
||||
/** \brief 40, Flags Enable Register */
|
||||
#define ASCLIN3_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000940u)
|
||||
|
||||
/** \brief 38, Flags Set Register */
|
||||
#define ASCLIN3_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000938u)
|
||||
|
||||
/** \brief 18, Frame Control Register */
|
||||
#define ASCLIN3_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000918u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define ASCLIN3_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000908u)
|
||||
|
||||
/** \brief 4, Input and Output Control Register */
|
||||
#define ASCLIN3_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000904u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define ASCLIN3_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00009F4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define ASCLIN3_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00009F0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define ASCLIN3_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00009ECu)
|
||||
|
||||
/** \brief 2C, LIN Break Timer Register */
|
||||
#define ASCLIN3_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000092Cu)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN3_LIN_BTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN3_LIN_BTIMER.
|
||||
*/
|
||||
#define ASCLIN3_LINBTIMER (ASCLIN3_LIN_BTIMER)
|
||||
|
||||
/** \brief 28, LIN Control Register */
|
||||
#define ASCLIN3_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000928u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN3_LIN_CON.
|
||||
* To use register names with standard convension, please use ASCLIN3_LIN_CON.
|
||||
*/
|
||||
#define ASCLIN3_LINCON (ASCLIN3_LIN_CON)
|
||||
|
||||
/** \brief 30, LIN Header Timer Register */
|
||||
#define ASCLIN3_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000930u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN3_LIN_HTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN3_LIN_HTIMER.
|
||||
*/
|
||||
#define ASCLIN3_LINHTIMER (ASCLIN3_LIN_HTIMER)
|
||||
|
||||
/** \brief E8, OCDS Control and Status */
|
||||
#define ASCLIN3_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00009E8u)
|
||||
|
||||
/** \brief 48, Receive Data Register */
|
||||
#define ASCLIN3_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000948u)
|
||||
|
||||
/** \brief 50, Receive Data Debug Register */
|
||||
#define ASCLIN3_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000950u)
|
||||
|
||||
/** \brief 10, RX FIFO Configuration Register */
|
||||
#define ASCLIN3_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000910u)
|
||||
|
||||
/** \brief 44, Transmit Data Register */
|
||||
#define ASCLIN3_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000944u)
|
||||
|
||||
/** \brief C, TX FIFO Configuration Register */
|
||||
#define ASCLIN3_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000090Cu)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXASCLIN_REG_H */
|
||||
@@ -1,699 +0,0 @@
|
||||
/**
|
||||
* \file IfxAsclin_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Asclin Asclin
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Asclin
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_union Union
|
||||
* \ingroup IfxLld_Asclin
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_struct Struct
|
||||
* \ingroup IfxLld_Asclin
|
||||
*
|
||||
*/
|
||||
#ifndef IFXASCLIN_REGDEF_H
|
||||
#define IFXASCLIN_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_ASCLIN_ACCEN0_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_ASCLIN_ACCEN0_Bits;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef struct _Ifx_ASCLIN_ACCEN1_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_ACCEN1_Bits;
|
||||
|
||||
/** \brief Bit Configuration Register */
|
||||
typedef struct _Ifx_ASCLIN_BITCON_Bits
|
||||
{
|
||||
unsigned int PRESCALER:12; /**< \brief [11:0] Prescaling of the Fractional Divider (rw) */
|
||||
unsigned int reserved_12:4; /**< \brief \internal Reserved */
|
||||
unsigned int OVERSAMPLING:4; /**< \brief [19:16] Oversampling Factor (rw) */
|
||||
unsigned int reserved_20:4; /**< \brief \internal Reserved */
|
||||
unsigned int SAMPLEPOINT:4; /**< \brief [27:24] Sample Point Position (rw) */
|
||||
unsigned int reserved_28:3; /**< \brief \internal Reserved */
|
||||
unsigned int SM:1; /**< \brief [31:31] Sample Mode (rw) */
|
||||
} Ifx_ASCLIN_BITCON_Bits;
|
||||
|
||||
/** \brief Baud Rate Detection Register */
|
||||
typedef struct _Ifx_ASCLIN_BRD_Bits
|
||||
{
|
||||
unsigned int LOWERLIMIT:8; /**< \brief [7:0] Lower Limit (rw) */
|
||||
unsigned int UPPERLIMIT:8; /**< \brief [15:8] Upper Limit (rw) */
|
||||
unsigned int MEASURED:12; /**< \brief [27:16] Measured Value of the Denominator (rh) */
|
||||
unsigned int reserved_28:4; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_BRD_Bits;
|
||||
|
||||
/** \brief Baud Rate Generation Register */
|
||||
typedef struct _Ifx_ASCLIN_BRG_Bits
|
||||
{
|
||||
unsigned int DENOMINATOR:12; /**< \brief [11:0] Denominator (rw) */
|
||||
unsigned int reserved_12:4; /**< \brief \internal Reserved */
|
||||
unsigned int NUMERATOR:12; /**< \brief [27:16] Numerator (rw) */
|
||||
unsigned int reserved_28:4; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_BRG_Bits;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef struct _Ifx_ASCLIN_CLC_Bits
|
||||
{
|
||||
unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
|
||||
unsigned int reserved_2:1; /**< \brief \internal Reserved */
|
||||
unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_CLC_Bits;
|
||||
|
||||
/** \brief Clock Selection Register */
|
||||
typedef struct _Ifx_ASCLIN_CSR_Bits
|
||||
{
|
||||
unsigned int CLKSEL:5; /**< \brief [4:0] Baud Rate Logic Clock Select (rw) */
|
||||
unsigned int reserved_5:26; /**< \brief \internal Reserved */
|
||||
unsigned int CON:1; /**< \brief [31:31] Clock On Flag (rh) */
|
||||
} Ifx_ASCLIN_CSR_Bits;
|
||||
|
||||
/** \brief Data Configuration Register */
|
||||
typedef struct _Ifx_ASCLIN_DATCON_Bits
|
||||
{
|
||||
unsigned int DATLEN:4; /**< \brief [3:0] Data Length (rw) */
|
||||
unsigned int reserved_4:9; /**< \brief \internal Reserved */
|
||||
unsigned int HO:1; /**< \brief [13:13] Header Only (rw) */
|
||||
unsigned int RM:1; /**< \brief [14:14] Response Mode (rw) */
|
||||
unsigned int CSM:1; /**< \brief [15:15] Checksum Mode (rw) */
|
||||
unsigned int RESPONSE:8; /**< \brief [23:16] Response Timeout Threshold Value (rw) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_DATCON_Bits;
|
||||
|
||||
/** \brief Flags Register */
|
||||
typedef struct _Ifx_ASCLIN_FLAGS_Bits
|
||||
{
|
||||
unsigned int TH:1; /**< \brief [0:0] Transmit Header End Flag (rh) */
|
||||
unsigned int TR:1; /**< \brief [1:1] Transmit Response End Flag (rh) */
|
||||
unsigned int RH:1; /**< \brief [2:2] Receive Header End Flag (rh) */
|
||||
unsigned int RR:1; /**< \brief [3:3] Receive Response End Flag (rh) */
|
||||
unsigned int reserved_4:1; /**< \brief \internal Reserved */
|
||||
unsigned int FED:1; /**< \brief [5:5] Falling Edge from Level 1 to Level 0 Detected (rh) */
|
||||
unsigned int RED:1; /**< \brief [6:6] Rising Edge from Level 0 to Level 1 Detected (rh) */
|
||||
unsigned int reserved_7:6; /**< \brief \internal Reserved */
|
||||
unsigned int TWRQ:1; /**< \brief [13:13] Transmit Wake Request Flag (rh) */
|
||||
unsigned int THRQ:1; /**< \brief [14:14] Transmit Header Request Flag (rh) */
|
||||
unsigned int TRRQ:1; /**< \brief [15:15] Transmit Response Request Flag (rh) */
|
||||
unsigned int PE:1; /**< \brief [16:16] Parity Error Flag (rh) */
|
||||
unsigned int TC:1; /**< \brief [17:17] Transmission Completed Flag (rh) */
|
||||
unsigned int FE:1; /**< \brief [18:18] Framing Error Flag (rh) */
|
||||
unsigned int HT:1; /**< \brief [19:19] Header Timeout Flag (rh) */
|
||||
unsigned int RT:1; /**< \brief [20:20] Response Timeout Flag (rh) */
|
||||
unsigned int BD:1; /**< \brief [21:21] Break Detected Flag (rh) */
|
||||
unsigned int LP:1; /**< \brief [22:22] LIN Parity Error Flag (rh) */
|
||||
unsigned int LA:1; /**< \brief [23:23] LIN Autobaud Detection Error Flag (rh) */
|
||||
unsigned int LC:1; /**< \brief [24:24] LIN Checksum Error Flag (rh) */
|
||||
unsigned int CE:1; /**< \brief [25:25] Collision Detection Error Flag (rh) */
|
||||
unsigned int RFO:1; /**< \brief [26:26] Receive FIFO Overflow Flag (rh) */
|
||||
unsigned int RFU:1; /**< \brief [27:27] Receive FIFO Underflow Flag (rh) */
|
||||
unsigned int RFL:1; /**< \brief [28:28] Receive FIFO Level Flag (rh) */
|
||||
unsigned int reserved_29:1; /**< \brief \internal Reserved */
|
||||
unsigned int TFO:1; /**< \brief [30:30] Transmit FIFO Overflow Flag (rh) */
|
||||
unsigned int TFL:1; /**< \brief [31:31] Transmit FIFO Level Flag (rh) */
|
||||
} Ifx_ASCLIN_FLAGS_Bits;
|
||||
|
||||
/** \brief Flags Clear Register */
|
||||
typedef struct _Ifx_ASCLIN_FLAGSCLEAR_Bits
|
||||
{
|
||||
unsigned int THC:1; /**< \brief [0:0] Flag Clear Bit (w) */
|
||||
unsigned int TRC:1; /**< \brief [1:1] Flag Clear Bit (w) */
|
||||
unsigned int RHC:1; /**< \brief [2:2] Flag Clear Bit (w) */
|
||||
unsigned int RRC:1; /**< \brief [3:3] Flag Clear Bit (w) */
|
||||
unsigned int reserved_4:1; /**< \brief \internal Reserved */
|
||||
unsigned int FEDC:1; /**< \brief [5:5] Flag Clear Bit (w) */
|
||||
unsigned int REDC:1; /**< \brief [6:6] Flag Clear Bit (w) */
|
||||
unsigned int reserved_7:6; /**< \brief \internal Reserved */
|
||||
unsigned int TWRQC:1; /**< \brief [13:13] Flag Clear Bit (w) */
|
||||
unsigned int THRQC:1; /**< \brief [14:14] Flag Clear Bit (w) */
|
||||
unsigned int TRRQC:1; /**< \brief [15:15] Flag Clear Bit (w) */
|
||||
unsigned int PEC:1; /**< \brief [16:16] Flag Clear Bit (w) */
|
||||
unsigned int TCC:1; /**< \brief [17:17] Flag Clear Bit (w) */
|
||||
unsigned int FEC:1; /**< \brief [18:18] Flag Clear Bit (w) */
|
||||
unsigned int HTC:1; /**< \brief [19:19] Flag Clear Bit (w) */
|
||||
unsigned int RTC:1; /**< \brief [20:20] Flag Clear Bit (w) */
|
||||
unsigned int BDC:1; /**< \brief [21:21] Flag Clear Bit (w) */
|
||||
unsigned int LPC:1; /**< \brief [22:22] Flag Clear Bit (w) */
|
||||
unsigned int LAC:1; /**< \brief [23:23] Flag Clear Bit (w) */
|
||||
unsigned int LCC:1; /**< \brief [24:24] Flag Clear Bit (w) */
|
||||
unsigned int CEC:1; /**< \brief [25:25] Flag Clear Bit (w) */
|
||||
unsigned int RFOC:1; /**< \brief [26:26] Flag Clear Bit (w) */
|
||||
unsigned int RFUC:1; /**< \brief [27:27] Flag Clear Bit (w) */
|
||||
unsigned int RFLC:1; /**< \brief [28:28] Flag Clear Bit (w) */
|
||||
unsigned int reserved_29:1; /**< \brief \internal Reserved */
|
||||
unsigned int TFOC:1; /**< \brief [30:30] Flag Clear Bit (w) */
|
||||
unsigned int TFLC:1; /**< \brief [31:31] Flag Clear Bit (w) */
|
||||
} Ifx_ASCLIN_FLAGSCLEAR_Bits;
|
||||
|
||||
/** \brief Flags Enable Register */
|
||||
typedef struct _Ifx_ASCLIN_FLAGSENABLE_Bits
|
||||
{
|
||||
unsigned int THE:1; /**< \brief [0:0] Flag Enable Bit (rw) */
|
||||
unsigned int TRE:1; /**< \brief [1:1] Flag Enable Bit (rw) */
|
||||
unsigned int RHE:1; /**< \brief [2:2] Flag Enable Bit (rw) */
|
||||
unsigned int RRE:1; /**< \brief [3:3] Flag Enable Bit (rw) */
|
||||
unsigned int reserved_4:1; /**< \brief \internal Reserved */
|
||||
unsigned int FEDE:1; /**< \brief [5:5] Flag Enable Bit (rw) */
|
||||
unsigned int REDE:1; /**< \brief [6:6] Flag Enable Bit (rw) */
|
||||
unsigned int reserved_7:9; /**< \brief \internal Reserved */
|
||||
unsigned int PEE:1; /**< \brief [16:16] Flag Enable Bit (rw) */
|
||||
unsigned int TCE:1; /**< \brief [17:17] Flag Enable Bit (rw) */
|
||||
unsigned int FEE:1; /**< \brief [18:18] Flag Enable Bit (rw) */
|
||||
unsigned int HTE:1; /**< \brief [19:19] Flag Enable Bit (rw) */
|
||||
unsigned int RTE:1; /**< \brief [20:20] Flag Enable Bit (rw) */
|
||||
unsigned int BDE:1; /**< \brief [21:21] Flag Enable Bit (rw) */
|
||||
unsigned int LPE:1; /**< \brief [22:22] Flag Enable Bit (rw) */
|
||||
unsigned int ABE:1; /**< \brief [23:23] Flag Enable Bit (rw) */
|
||||
unsigned int LCE:1; /**< \brief [24:24] Flag Enable Bit (rw) */
|
||||
unsigned int CEE:1; /**< \brief [25:25] Flag Enable Bit (rw) */
|
||||
unsigned int RFOE:1; /**< \brief [26:26] Flag Enable Bit (rw) */
|
||||
unsigned int RFUE:1; /**< \brief [27:27] Flag Enable Bit (rw) */
|
||||
unsigned int RFLE:1; /**< \brief [28:28] Flag Enable Bit (rw) */
|
||||
unsigned int reserved_29:1; /**< \brief \internal Reserved */
|
||||
unsigned int TFOE:1; /**< \brief [30:30] Flag Enable Bit (rw) */
|
||||
unsigned int TFLE:1; /**< \brief [31:31] Flag Enable Bit (rw) */
|
||||
} Ifx_ASCLIN_FLAGSENABLE_Bits;
|
||||
|
||||
/** \brief Flags Set Register */
|
||||
typedef struct _Ifx_ASCLIN_FLAGSSET_Bits
|
||||
{
|
||||
unsigned int THS:1; /**< \brief [0:0] Flag Set Bit (w) */
|
||||
unsigned int TRS:1; /**< \brief [1:1] Flag Set Bit (w) */
|
||||
unsigned int RHS:1; /**< \brief [2:2] Flag Set Bit (w) */
|
||||
unsigned int RRS:1; /**< \brief [3:3] Flag Set Bit (w) */
|
||||
unsigned int reserved_4:1; /**< \brief \internal Reserved */
|
||||
unsigned int FEDS:1; /**< \brief [5:5] Flag Set Bit (w) */
|
||||
unsigned int REDS:1; /**< \brief [6:6] Flag Set Bit (w) */
|
||||
unsigned int reserved_7:6; /**< \brief \internal Reserved */
|
||||
unsigned int TWRQS:1; /**< \brief [13:13] Flag Set Bit (w) */
|
||||
unsigned int THRQS:1; /**< \brief [14:14] Flag Set Bit (w) */
|
||||
unsigned int TRRQS:1; /**< \brief [15:15] Flag Set Bit (w) */
|
||||
unsigned int PES:1; /**< \brief [16:16] Flag Set Bit (w) */
|
||||
unsigned int TCS:1; /**< \brief [17:17] Flag Set Bit (w) */
|
||||
unsigned int FES:1; /**< \brief [18:18] Flag Set Bit (w) */
|
||||
unsigned int HTS:1; /**< \brief [19:19] Flag Set Bit (w) */
|
||||
unsigned int RTS:1; /**< \brief [20:20] Flag Set Bit (w) */
|
||||
unsigned int BDS:1; /**< \brief [21:21] Flag Set Bit (w) */
|
||||
unsigned int LPS:1; /**< \brief [22:22] Flag Set Bit (w) */
|
||||
unsigned int LAS:1; /**< \brief [23:23] Flag Set Bit (w) */
|
||||
unsigned int LCS:1; /**< \brief [24:24] Flag Set Bit (w) */
|
||||
unsigned int CES:1; /**< \brief [25:25] Flag Set Bit (w) */
|
||||
unsigned int RFOS:1; /**< \brief [26:26] Flag Set Bit (w) */
|
||||
unsigned int RFUS:1; /**< \brief [27:27] Flag Set Bit (w) */
|
||||
unsigned int RFLS:1; /**< \brief [28:28] Flag Set Bit (w) */
|
||||
unsigned int reserved_29:1; /**< \brief \internal Reserved */
|
||||
unsigned int TFOS:1; /**< \brief [30:30] Flag Set Bit (w) */
|
||||
unsigned int TFLS:1; /**< \brief [31:31] Flag Set Bit (w) */
|
||||
} Ifx_ASCLIN_FLAGSSET_Bits;
|
||||
|
||||
/** \brief Frame Control Register */
|
||||
typedef struct _Ifx_ASCLIN_FRAMECON_Bits
|
||||
{
|
||||
unsigned int reserved_0:6; /**< \brief \internal Reserved */
|
||||
unsigned int IDLE:3; /**< \brief [8:6] Duration of the IDLE delay (rw) */
|
||||
unsigned int STOP:3; /**< \brief [11:9] Number of Stop Bits (rw) */
|
||||
unsigned int LEAD:3; /**< \brief [14:12] Duration of the Leading Delay (rw) */
|
||||
unsigned int reserved_15:1; /**< \brief \internal Reserved */
|
||||
unsigned int MODE:2; /**< \brief [17:16] Mode Selection (rw) */
|
||||
unsigned int reserved_18:10; /**< \brief \internal Reserved */
|
||||
unsigned int MSB:1; /**< \brief [28:28] Shift Direction (rw) */
|
||||
unsigned int CEN:1; /**< \brief [29:29] Collision Detection Enable (rw) */
|
||||
unsigned int PEN:1; /**< \brief [30:30] Parity Enable (rw) */
|
||||
unsigned int ODD:1; /**< \brief [31:31] Parity Type (rw) */
|
||||
} Ifx_ASCLIN_FRAMECON_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_ASCLIN_ID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_ASCLIN_ID_Bits;
|
||||
|
||||
/** \brief Input and Output Control Register */
|
||||
typedef struct _Ifx_ASCLIN_IOCR_Bits
|
||||
{
|
||||
unsigned int ALTI:3; /**< \brief [2:0] Alternate Input Select (rw) */
|
||||
unsigned int reserved_3:1; /**< \brief \internal Reserved */
|
||||
unsigned int DEPTH:6; /**< \brief [9:4] Digital Glitch Filter Depth (rw) */
|
||||
unsigned int reserved_10:6; /**< \brief \internal Reserved */
|
||||
unsigned int CTS:2; /**< \brief [17:16] CTS Select (rw) */
|
||||
unsigned int reserved_18:7; /**< \brief \internal Reserved */
|
||||
unsigned int RCPOL:1; /**< \brief [25:25] RTS CTS Polarity (rw) */
|
||||
unsigned int CPOL:1; /**< \brief [26:26] Clock Polarity in Synchronous Mode (rw) */
|
||||
unsigned int SPOL:1; /**< \brief [27:27] Slave Polarity in Synchronous Mode (rw) */
|
||||
unsigned int LB:1; /**< \brief [28:28] Loop Back Mode (rw) */
|
||||
unsigned int CTSEN:1; /**< \brief [29:29] Input Signal CTS Enable (rw) */
|
||||
unsigned int RXM:1; /**< \brief [30:30] Receive Monitor (rh) */
|
||||
unsigned int TXM:1; /**< \brief [31:31] Transmit Monitor (rh) */
|
||||
} Ifx_ASCLIN_IOCR_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef struct _Ifx_ASCLIN_KRST0_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_KRST0_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef struct _Ifx_ASCLIN_KRST1_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_KRST1_Bits;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef struct _Ifx_ASCLIN_KRSTCLR_Bits
|
||||
{
|
||||
unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_KRSTCLR_Bits;
|
||||
|
||||
/** \brief LIN Break Timer Register */
|
||||
typedef struct _Ifx_ASCLIN_LIN_BTIMER_Bits
|
||||
{
|
||||
unsigned int BREAK:6; /**< \brief [5:0] Break Pulse Generation and Detection (rw) */
|
||||
unsigned int reserved_6:26; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_LIN_BTIMER_Bits;
|
||||
|
||||
/** \brief LIN Control Register */
|
||||
typedef struct _Ifx_ASCLIN_LIN_CON_Bits
|
||||
{
|
||||
unsigned int reserved_0:23; /**< \brief \internal Reserved */
|
||||
unsigned int CSI:1; /**< \brief [23:23] Checksum Injection (rw) */
|
||||
unsigned int reserved_24:1; /**< \brief \internal Reserved */
|
||||
unsigned int CSEN:1; /**< \brief [25:25] Hardware Checksum Enable (rw) */
|
||||
unsigned int MS:1; /**< \brief [26:26] Master Slave Mode (rw) */
|
||||
unsigned int ABD:1; /**< \brief [27:27] Autobaud Detection (rw) */
|
||||
unsigned int reserved_28:4; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_LIN_CON_Bits;
|
||||
|
||||
/** \brief LIN Header Timer Register */
|
||||
typedef struct _Ifx_ASCLIN_LIN_HTIMER_Bits
|
||||
{
|
||||
unsigned int HEADER:8; /**< \brief [7:0] Header Timeout Threshold Value (rw) */
|
||||
unsigned int reserved_8:24; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_LIN_HTIMER_Bits;
|
||||
|
||||
/** \brief OCDS Control and Status */
|
||||
typedef struct _Ifx_ASCLIN_OCS_Bits
|
||||
{
|
||||
unsigned int reserved_0:24; /**< \brief \internal Reserved */
|
||||
unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
|
||||
unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
|
||||
unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
|
||||
unsigned int reserved_30:2; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_OCS_Bits;
|
||||
|
||||
/** \brief Receive Data Register */
|
||||
typedef struct _Ifx_ASCLIN_RXDATA_Bits
|
||||
{
|
||||
unsigned int DATA:32; /**< \brief [31:0] Data (rh) */
|
||||
} Ifx_ASCLIN_RXDATA_Bits;
|
||||
|
||||
/** \brief Receive Data Debug Register */
|
||||
typedef struct _Ifx_ASCLIN_RXDATAD_Bits
|
||||
{
|
||||
unsigned int DATA:32; /**< \brief [31:0] Data (rh) */
|
||||
} Ifx_ASCLIN_RXDATAD_Bits;
|
||||
|
||||
/** \brief RX FIFO Configuration Register */
|
||||
typedef struct _Ifx_ASCLIN_RXFIFOCON_Bits
|
||||
{
|
||||
unsigned int FLUSH:1; /**< \brief [0:0] Flush the receive FIFO (w) */
|
||||
unsigned int ENI:1; /**< \brief [1:1] Receive FIFO Inlet Enable (rwh) */
|
||||
unsigned int reserved_2:4; /**< \brief \internal Reserved */
|
||||
unsigned int OUTW:2; /**< \brief [7:6] Receive FIFO Outlet Width (rw) */
|
||||
unsigned int INTLEVEL:4; /**< \brief [11:8] FIFO Interrupt Level (rw) */
|
||||
unsigned int reserved_12:4; /**< \brief \internal Reserved */
|
||||
unsigned int FILL:5; /**< \brief [20:16] FIFO Filling Level (rh) */
|
||||
unsigned int reserved_21:10; /**< \brief \internal Reserved */
|
||||
unsigned int BUF:1; /**< \brief [31:31] Receive Buffer Mode (rw) */
|
||||
} Ifx_ASCLIN_RXFIFOCON_Bits;
|
||||
|
||||
/** \brief Transmit Data Register */
|
||||
typedef struct _Ifx_ASCLIN_TXDATA_Bits
|
||||
{
|
||||
unsigned int DATA:32; /**< \brief [31:0] Data (w) */
|
||||
} Ifx_ASCLIN_TXDATA_Bits;
|
||||
|
||||
/** \brief TX FIFO Configuration Register */
|
||||
typedef struct _Ifx_ASCLIN_TXFIFOCON_Bits
|
||||
{
|
||||
unsigned int FLUSH:1; /**< \brief [0:0] Flush the transmit FIFO (w) */
|
||||
unsigned int ENO:1; /**< \brief [1:1] Transmit FIFO Outlet Enable (rw) */
|
||||
unsigned int reserved_2:4; /**< \brief \internal Reserved */
|
||||
unsigned int INW:2; /**< \brief [7:6] Transmit FIFO Inlet Width (rw) */
|
||||
unsigned int INTLEVEL:4; /**< \brief [11:8] FIFO Interrupt Level (rw) */
|
||||
unsigned int reserved_12:4; /**< \brief \internal Reserved */
|
||||
unsigned int FILL:5; /**< \brief [20:16] FIFO Filling Level (rh) */
|
||||
unsigned int reserved_21:11; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_TXFIFOCON_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_ACCEN0;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_ACCEN1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_ACCEN1;
|
||||
|
||||
/** \brief Bit Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_BITCON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_BITCON;
|
||||
|
||||
/** \brief Baud Rate Detection Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_BRD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_BRD;
|
||||
|
||||
/** \brief Baud Rate Generation Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_BRG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_BRG;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_CLC;
|
||||
|
||||
/** \brief Clock Selection Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_CSR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_CSR;
|
||||
|
||||
/** \brief Data Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_DATCON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_DATCON;
|
||||
|
||||
/** \brief Flags Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_FLAGS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_FLAGS;
|
||||
|
||||
/** \brief Flags Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_FLAGSCLEAR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_FLAGSCLEAR;
|
||||
|
||||
/** \brief Flags Enable Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_FLAGSENABLE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_FLAGSENABLE;
|
||||
|
||||
/** \brief Flags Set Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_FLAGSSET_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_FLAGSSET;
|
||||
|
||||
/** \brief Frame Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_FRAMECON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_FRAMECON;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_ID;
|
||||
|
||||
/** \brief Input and Output Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_IOCR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_IOCR;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_KRST0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_KRST0;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_KRST1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_KRST1;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_KRSTCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_KRSTCLR;
|
||||
|
||||
/** \brief LIN Break Timer Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_LIN_BTIMER_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_LIN_BTIMER;
|
||||
|
||||
/** \brief LIN Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_LIN_CON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_LIN_CON;
|
||||
|
||||
/** \brief LIN Header Timer Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_LIN_HTIMER_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_LIN_HTIMER;
|
||||
|
||||
/** \brief OCDS Control and Status */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_OCS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_OCS;
|
||||
|
||||
/** \brief Receive Data Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_RXDATA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_RXDATA;
|
||||
|
||||
/** \brief Receive Data Debug Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_RXDATAD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_RXDATAD;
|
||||
|
||||
/** \brief RX FIFO Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_RXFIFOCON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_RXFIFOCON;
|
||||
|
||||
/** \brief Transmit Data Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_TXDATA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_TXDATA;
|
||||
|
||||
/** \brief TX FIFO Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_TXFIFOCON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_TXFIFOCON;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L1
|
||||
* \{ */
|
||||
|
||||
/** \brief LIN */
|
||||
typedef volatile struct _Ifx_ASCLIN_LIN
|
||||
{
|
||||
Ifx_ASCLIN_LIN_CON CON; /**< \brief 0, LIN Control Register */
|
||||
Ifx_ASCLIN_LIN_BTIMER BTIMER; /**< \brief 4, LIN Break Timer Register */
|
||||
Ifx_ASCLIN_LIN_HTIMER HTIMER; /**< \brief 8, LIN Header Timer Register */
|
||||
} Ifx_ASCLIN_LIN;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief ASCLIN object */
|
||||
typedef volatile struct _Ifx_ASCLIN
|
||||
{
|
||||
Ifx_ASCLIN_CLC CLC; /**< \brief 0, Clock Control Register */
|
||||
Ifx_ASCLIN_IOCR IOCR; /**< \brief 4, Input and Output Control Register */
|
||||
Ifx_ASCLIN_ID ID; /**< \brief 8, Module Identification Register */
|
||||
Ifx_ASCLIN_TXFIFOCON TXFIFOCON; /**< \brief C, TX FIFO Configuration Register */
|
||||
Ifx_ASCLIN_RXFIFOCON RXFIFOCON; /**< \brief 10, RX FIFO Configuration Register */
|
||||
Ifx_ASCLIN_BITCON BITCON; /**< \brief 14, Bit Configuration Register */
|
||||
Ifx_ASCLIN_FRAMECON FRAMECON; /**< \brief 18, Frame Control Register */
|
||||
Ifx_ASCLIN_DATCON DATCON; /**< \brief 1C, Data Configuration Register */
|
||||
Ifx_ASCLIN_BRG BRG; /**< \brief 20, Baud Rate Generation Register */
|
||||
Ifx_ASCLIN_BRD BRD; /**< \brief 24, Baud Rate Detection Register */
|
||||
Ifx_ASCLIN_LIN LIN; /**< \brief 28, LIN */
|
||||
Ifx_ASCLIN_FLAGS FLAGS; /**< \brief 34, Flags Register */
|
||||
Ifx_ASCLIN_FLAGSSET FLAGSSET; /**< \brief 38, Flags Set Register */
|
||||
Ifx_ASCLIN_FLAGSCLEAR FLAGSCLEAR; /**< \brief 3C, Flags Clear Register */
|
||||
Ifx_ASCLIN_FLAGSENABLE FLAGSENABLE; /**< \brief 40, Flags Enable Register */
|
||||
Ifx_ASCLIN_TXDATA TXDATA; /**< \brief 44, Transmit Data Register */
|
||||
Ifx_ASCLIN_RXDATA RXDATA; /**< \brief 48, Receive Data Register */
|
||||
Ifx_ASCLIN_CSR CSR; /**< \brief 4C, Clock Selection Register */
|
||||
Ifx_ASCLIN_RXDATAD RXDATAD; /**< \brief 50, Receive Data Debug Register */
|
||||
unsigned char reserved_54[148]; /**< \brief 54, \internal Reserved */
|
||||
Ifx_ASCLIN_OCS OCS; /**< \brief E8, OCDS Control and Status */
|
||||
Ifx_ASCLIN_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
|
||||
Ifx_ASCLIN_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
|
||||
Ifx_ASCLIN_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
|
||||
Ifx_ASCLIN_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
|
||||
Ifx_ASCLIN_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
|
||||
} Ifx_ASCLIN;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXASCLIN_REGDEF_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,269 +0,0 @@
|
||||
/**
|
||||
* \file IfxCbs_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Cbs_Cfg Cbs address
|
||||
* \ingroup IfxLld_Cbs
|
||||
*
|
||||
* \defgroup IfxLld_Cbs_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Cbs_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Cbs_Cfg_Cbs 2-CBS
|
||||
* \ingroup IfxLld_Cbs_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXCBS_REG_H
|
||||
#define IFXCBS_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxCbs_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Cbs_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief CBS object */
|
||||
#define MODULE_CBS /*lint --e(923)*/ (*(Ifx_CBS*)0xF0000400u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Cbs_Cfg_Cbs
|
||||
* \{ */
|
||||
|
||||
/** \brief 68, Communication Mode Data Register */
|
||||
#define CBS_COMDATA /*lint --e(923)*/ (*(volatile Ifx_CBS_COMDATA*)0xF0000468u)
|
||||
|
||||
/** \brief 88, Internally Controlled Trace Source Register */
|
||||
#define CBS_ICTSA /*lint --e(923)*/ (*(volatile Ifx_CBS_ICTSA*)0xF0000488u)
|
||||
|
||||
/** \brief 8C, Internally Controlled Trace Destination Register */
|
||||
#define CBS_ICTTA /*lint --e(923)*/ (*(volatile Ifx_CBS_ICTTA*)0xF000048Cu)
|
||||
|
||||
/** \brief 84, Internal Mode Status and Control Register */
|
||||
#define CBS_INTMOD /*lint --e(923)*/ (*(volatile Ifx_CBS_INTMOD*)0xF0000484u)
|
||||
|
||||
/** \brief 6C, IOClient Status and Control Register */
|
||||
#define CBS_IOSR /*lint --e(923)*/ (*(volatile Ifx_CBS_IOSR*)0xF000046Cu)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define CBS_JDPID /*lint --e(923)*/ (*(volatile Ifx_CBS_JDPID*)0xF0000408u)
|
||||
|
||||
/** \brief 64, JTAG Device Identification Register */
|
||||
#define CBS_JTAGID /*lint --e(923)*/ (*(volatile Ifx_CBS_JTAGID*)0xF0000464u)
|
||||
|
||||
/** \brief 7C, OSCU Control Register */
|
||||
#define CBS_OCNTRL /*lint --e(923)*/ (*(volatile Ifx_CBS_OCNTRL*)0xF000047Cu)
|
||||
|
||||
/** \brief 78, OCDS Enable Control Register */
|
||||
#define CBS_OEC /*lint --e(923)*/ (*(volatile Ifx_CBS_OEC*)0xF0000478u)
|
||||
|
||||
/** \brief C, OCDS Interface Mode Register */
|
||||
#define CBS_OIFM /*lint --e(923)*/ (*(volatile Ifx_CBS_OIFM*)0xF000040Cu)
|
||||
|
||||
/** \brief 80, OSCU Status Register */
|
||||
#define CBS_OSTATE /*lint --e(923)*/ (*(volatile Ifx_CBS_OSTATE*)0xF0000480u)
|
||||
|
||||
/** \brief B0, TG Capture for Cores - BRKOUT */
|
||||
#define CBS_TCCB /*lint --e(923)*/ (*(volatile Ifx_CBS_TCCB*)0xF00004B0u)
|
||||
|
||||
/** \brief B4, TG Capture for Cores - HALT */
|
||||
#define CBS_TCCH /*lint --e(923)*/ (*(volatile Ifx_CBS_TCCH*)0xF00004B4u)
|
||||
|
||||
/** \brief 1C, TG Capture for TG Input Pins */
|
||||
#define CBS_TCIP /*lint --e(923)*/ (*(volatile Ifx_CBS_TCIP*)0xF000041Cu)
|
||||
|
||||
/** \brief BC, TG Capture for MCDS */
|
||||
#define CBS_TCM /*lint --e(923)*/ (*(volatile Ifx_CBS_TCM*)0xF00004BCu)
|
||||
|
||||
/** \brief B8, TG Capture for OTGB0/1 */
|
||||
#define CBS_TCTGB /*lint --e(923)*/ (*(volatile Ifx_CBS_TCTGB*)0xF00004B8u)
|
||||
|
||||
/** \brief 74, TG Capture for TG Lines */
|
||||
#define CBS_TCTL /*lint --e(923)*/ (*(volatile Ifx_CBS_TCTL*)0xF0000474u)
|
||||
|
||||
/** \brief 10, TG Input Pins Routing */
|
||||
#define CBS_TIPR /*lint --e(923)*/ (*(volatile Ifx_CBS_TIPR*)0xF0000410u)
|
||||
|
||||
/** \brief 94, TG Line 1 Suspend Targets */
|
||||
#define CBS_TL1ST /*lint --e(923)*/ (*(volatile Ifx_CBS_TL1ST*)0xF0000494u)
|
||||
|
||||
/** \brief 90, TG Line Control */
|
||||
#define CBS_TLC /*lint --e(923)*/ (*(volatile Ifx_CBS_TLC*)0xF0000490u)
|
||||
|
||||
/** \brief 40, TG Line Counter Control */
|
||||
#define CBS_TLCC0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCC*)0xF0000440u)
|
||||
|
||||
/** \brief 44, TG Line Counter Control */
|
||||
#define CBS_TLCC1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCC*)0xF0000444u)
|
||||
|
||||
/** \brief 98, TG Line Capture and Hold Enable */
|
||||
#define CBS_TLCHE /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCHE*)0xF0000498u)
|
||||
|
||||
/** \brief 9C, TG Line Capture and Hold Clear */
|
||||
#define CBS_TLCHS /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCHS*)0xF000049Cu)
|
||||
|
||||
/** \brief 50, TG Line Counter Value */
|
||||
#define CBS_TLCV0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCV*)0xF0000450u)
|
||||
|
||||
/** \brief 54, TG Line Counter Value */
|
||||
#define CBS_TLCV1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCV*)0xF0000454u)
|
||||
|
||||
/** \brief 70, TG Line State */
|
||||
#define CBS_TLS /*lint --e(923)*/ (*(volatile Ifx_CBS_TLS*)0xF0000470u)
|
||||
|
||||
/** \brief A8, TG Line Timer */
|
||||
#define CBS_TLT /*lint --e(923)*/ (*(volatile Ifx_CBS_TLT*)0xF00004A8u)
|
||||
|
||||
/** \brief AC, TG Lines for Trigger to Host */
|
||||
#define CBS_TLTTH /*lint --e(923)*/ (*(volatile Ifx_CBS_TLTTH*)0xF00004ACu)
|
||||
|
||||
/** \brief 18, TG Output Pins Pulse Stretcher */
|
||||
#define CBS_TOPPS /*lint --e(923)*/ (*(volatile Ifx_CBS_TOPPS*)0xF0000418u)
|
||||
|
||||
/** \brief 14, TG Output Pins Routing */
|
||||
#define CBS_TOPR /*lint --e(923)*/ (*(volatile Ifx_CBS_TOPR*)0xF0000414u)
|
||||
|
||||
/** \brief 20, TG Routing for CPU */
|
||||
#define CBS_TRC0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRC*)0xF0000420u)
|
||||
|
||||
/** \brief 24, TG Routing for CPU */
|
||||
#define CBS_TRC1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRC*)0xF0000424u)
|
||||
|
||||
/** \brief C0, TG Routing Events of CPU */
|
||||
#define CBS_TREC0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TREC*)0xF00004C0u)
|
||||
|
||||
/** \brief C4, TG Routing Events of CPU */
|
||||
#define CBS_TREC1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TREC*)0xF00004C4u)
|
||||
|
||||
/** \brief 100, Trigger to Host Register */
|
||||
#define CBS_TRIG0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000500u)
|
||||
|
||||
/** \brief 104, Trigger to Host Register */
|
||||
#define CBS_TRIG1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000504u)
|
||||
|
||||
/** \brief 128, Trigger to Host Register */
|
||||
#define CBS_TRIG10 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000528u)
|
||||
|
||||
/** \brief 12C, Trigger to Host Register */
|
||||
#define CBS_TRIG11 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000052Cu)
|
||||
|
||||
/** \brief 130, Trigger to Host Register */
|
||||
#define CBS_TRIG12 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000530u)
|
||||
|
||||
/** \brief 134, Trigger to Host Register */
|
||||
#define CBS_TRIG13 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000534u)
|
||||
|
||||
/** \brief 138, Trigger to Host Register */
|
||||
#define CBS_TRIG14 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000538u)
|
||||
|
||||
/** \brief 13C, Trigger to Host Register */
|
||||
#define CBS_TRIG15 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000053Cu)
|
||||
|
||||
/** \brief 140, Trigger to Host Register */
|
||||
#define CBS_TRIG16 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000540u)
|
||||
|
||||
/** \brief 144, Trigger to Host Register */
|
||||
#define CBS_TRIG17 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000544u)
|
||||
|
||||
/** \brief 148, Trigger to Host Register */
|
||||
#define CBS_TRIG18 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000548u)
|
||||
|
||||
/** \brief 14C, Trigger to Host Register */
|
||||
#define CBS_TRIG19 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000054Cu)
|
||||
|
||||
/** \brief 108, Trigger to Host Register */
|
||||
#define CBS_TRIG2 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000508u)
|
||||
|
||||
/** \brief 150, Trigger to Host Register */
|
||||
#define CBS_TRIG20 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000550u)
|
||||
|
||||
/** \brief 154, Trigger to Host Register */
|
||||
#define CBS_TRIG21 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000554u)
|
||||
|
||||
/** \brief 10C, Trigger to Host Register */
|
||||
#define CBS_TRIG3 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000050Cu)
|
||||
|
||||
/** \brief 110, Trigger to Host Register */
|
||||
#define CBS_TRIG4 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000510u)
|
||||
|
||||
/** \brief 114, Trigger to Host Register */
|
||||
#define CBS_TRIG5 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000514u)
|
||||
|
||||
/** \brief 118, Trigger to Host Register */
|
||||
#define CBS_TRIG6 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000518u)
|
||||
|
||||
/** \brief 11C, Trigger to Host Register */
|
||||
#define CBS_TRIG7 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000051Cu)
|
||||
|
||||
/** \brief 120, Trigger to Host Register */
|
||||
#define CBS_TRIG8 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000520u)
|
||||
|
||||
/** \brief 124, Trigger to Host Register */
|
||||
#define CBS_TRIG9 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000524u)
|
||||
|
||||
/** \brief A4, Clear Trigger to Host Register */
|
||||
#define CBS_TRIGC /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIGC*)0xF00004A4u)
|
||||
|
||||
/** \brief A0, Set Trigger to Host Register */
|
||||
#define CBS_TRIGS /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIGS*)0xF00004A0u)
|
||||
|
||||
/** \brief 3C, TG Routing for MCDS Control */
|
||||
#define CBS_TRMC /*lint --e(923)*/ (*(volatile Ifx_CBS_TRMC*)0xF000043Cu)
|
||||
|
||||
/** \brief DC, TG Routing for MCDS Triggers */
|
||||
#define CBS_TRMT /*lint --e(923)*/ (*(volatile Ifx_CBS_TRMT*)0xF00004DCu)
|
||||
|
||||
/** \brief 60, TG Routing for Special Signals */
|
||||
#define CBS_TRSS /*lint --e(923)*/ (*(volatile Ifx_CBS_TRSS*)0xF0000460u)
|
||||
|
||||
/** \brief E4, TG Routing for OTGB Bits [15:8] */
|
||||
#define CBS_TRTGB0_H /*lint --e(923)*/ (*(volatile Ifx_CBS_TRTGB_H*)0xF00004E4u)
|
||||
|
||||
/** Alias (User Manual Name) for CBS_TRTGB0_H.
|
||||
* To use register names with standard convension, please use CBS_TRTGB0_H.
|
||||
*/
|
||||
#define CBS_TRTGB0H (CBS_TRTGB0_H)
|
||||
|
||||
/** \brief E0, TG Routing for OTGB Bits [7:0] */
|
||||
#define CBS_TRTGB0_L /*lint --e(923)*/ (*(volatile Ifx_CBS_TRTGB_L*)0xF00004E0u)
|
||||
|
||||
/** Alias (User Manual Name) for CBS_TRTGB0_L.
|
||||
* To use register names with standard convension, please use CBS_TRTGB0_L.
|
||||
*/
|
||||
#define CBS_TRTGB0L (CBS_TRTGB0_L)
|
||||
|
||||
/** \brief EC, TG Routing for OTGB Bits [15:8] */
|
||||
#define CBS_TRTGB1_H /*lint --e(923)*/ (*(volatile Ifx_CBS_TRTGB_H*)0xF00004ECu)
|
||||
|
||||
/** Alias (User Manual Name) for CBS_TRTGB1_H.
|
||||
* To use register names with standard convension, please use CBS_TRTGB1_H.
|
||||
*/
|
||||
#define CBS_TRTGB1H (CBS_TRTGB1_H)
|
||||
|
||||
/** \brief E8, TG Routing for OTGB Bits [7:0] */
|
||||
#define CBS_TRTGB1_L /*lint --e(923)*/ (*(volatile Ifx_CBS_TRTGB_L*)0xF00004E8u)
|
||||
|
||||
/** Alias (User Manual Name) for CBS_TRTGB1_L.
|
||||
* To use register names with standard convension, please use CBS_TRTGB1_L.
|
||||
*/
|
||||
#define CBS_TRTGB1L (CBS_TRTGB1_L)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXCBS_REG_H */
|
||||
@@ -1,957 +0,0 @@
|
||||
/**
|
||||
* \file IfxCbs_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Cbs Cbs
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Cbs_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Cbs
|
||||
*
|
||||
* \defgroup IfxLld_Cbs_union Union
|
||||
* \ingroup IfxLld_Cbs
|
||||
*
|
||||
* \defgroup IfxLld_Cbs_struct Struct
|
||||
* \ingroup IfxLld_Cbs
|
||||
*
|
||||
*/
|
||||
#ifndef IFXCBS_REGDEF_H
|
||||
#define IFXCBS_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Cbs_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Communication Mode Data Register */
|
||||
typedef struct _Ifx_CBS_COMDATA_Bits
|
||||
{
|
||||
unsigned int DATA:32; /**< \brief [31:0] Read/Write Data (rw) */
|
||||
} Ifx_CBS_COMDATA_Bits;
|
||||
|
||||
/** \brief Internally Controlled Trace Source Register */
|
||||
typedef struct _Ifx_CBS_ICTSA_Bits
|
||||
{
|
||||
unsigned int ADDR:32; /**< \brief [31:0] Source Address (rw) */
|
||||
} Ifx_CBS_ICTSA_Bits;
|
||||
|
||||
/** \brief Internally Controlled Trace Destination Register */
|
||||
typedef struct _Ifx_CBS_ICTTA_Bits
|
||||
{
|
||||
unsigned int ADDR:32; /**< \brief [31:0] Destination Address (rw) */
|
||||
} Ifx_CBS_ICTTA_Bits;
|
||||
|
||||
/** \brief Internal Mode Status and Control Register */
|
||||
typedef struct _Ifx_CBS_INTMOD_Bits
|
||||
{
|
||||
unsigned int SET_CRS:1; /**< \brief [0:0] Set Read Sync Flag (w) */
|
||||
unsigned int SET_CWS:1; /**< \brief [1:1] Set Write Sync Flag (w) */
|
||||
unsigned int SET_CS:1; /**< \brief [2:2] Set Communication Synchronization Flag (w) */
|
||||
unsigned int CLR_CS:1; /**< \brief [3:3] Clear Communication Synchronization Flag (w) */
|
||||
unsigned int CHANNEL_P:1; /**< \brief [4:4] CHANNEL Write Protection (w) */
|
||||
unsigned int CHANNEL:3; /**< \brief [7:5] Channel Indication (rw) */
|
||||
unsigned int reserved_8:8; /**< \brief \internal Reserved */
|
||||
unsigned int SET_INT_MOD:1; /**< \brief [16:16] Enter Internal Mode (w) */
|
||||
unsigned int reserved_17:1; /**< \brief \internal Reserved */
|
||||
unsigned int SET_INT_TRC:1; /**< \brief [18:18] Enable Internally Controlled Triggered Transfer (w) */
|
||||
unsigned int CLR_INT_TRC:1; /**< \brief [19:19] Disable Internally Controlled Triggered Transfer (w) */
|
||||
unsigned int TRC_MOD_P:1; /**< \brief [20:20] TRC_MOD Write Protection (w) */
|
||||
unsigned int TRC_MOD:2; /**< \brief [22:21] Data Size Definition for Triggered Transfer (rw) */
|
||||
unsigned int reserved_23:1; /**< \brief \internal Reserved */
|
||||
unsigned int INT_MOD:1; /**< \brief [24:24] Internal Mode Enabled Flag (rh) */
|
||||
unsigned int INT_TRC:1; /**< \brief [25:25] Internally Controlled Triggered Transfer Enable (rh) */
|
||||
unsigned int reserved_26:6; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_INTMOD_Bits;
|
||||
|
||||
/** \brief IOClient Status and Control Register */
|
||||
typedef struct _Ifx_CBS_IOSR_Bits
|
||||
{
|
||||
unsigned int reserved_0:4; /**< \brief \internal Reserved */
|
||||
unsigned int CRSYNC:1; /**< \brief [4:4] Communication Mode Read Sync Flag (rh) */
|
||||
unsigned int CWSYNC:1; /**< \brief [5:5] Communication Mode Write Sync Flag (rh) */
|
||||
unsigned int CW_ACK:1; /**< \brief [6:6] Communication Mode Write Acknowledge (w) */
|
||||
unsigned int COM_SYNC:1; /**< \brief [7:7] Communication Mode Synchronization Flag (rh) */
|
||||
unsigned int HOSTED:1; /**< \brief [8:8] Tool Interface in Use (rh) */
|
||||
unsigned int reserved_9:3; /**< \brief \internal Reserved */
|
||||
unsigned int CHANNEL:3; /**< \brief [14:12] Channel Indication (rh) */
|
||||
unsigned int reserved_15:17; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_IOSR_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_CBS_JDPID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_CBS_JDPID_Bits;
|
||||
|
||||
/** \brief JTAG Device Identification Register */
|
||||
typedef struct _Ifx_CBS_JTAGID_Bits
|
||||
{
|
||||
unsigned int JTAG_ID:32; /**< \brief [31:0] JTAG Device ID (rw) */
|
||||
} Ifx_CBS_JTAGID_Bits;
|
||||
|
||||
/** \brief OSCU Control Register */
|
||||
typedef struct _Ifx_CBS_OCNTRL_Bits
|
||||
{
|
||||
unsigned int OC0_P:1; /**< \brief [0:0] OC0 Write Protection (w) */
|
||||
unsigned int OC0:1; /**< \brief [1:1] Set/Clear OCDS Control Bits Bus Domain (w) */
|
||||
unsigned int OC1_P:1; /**< \brief [2:2] OC1 Write Protection (w) */
|
||||
unsigned int OC1:1; /**< \brief [3:3] Set/Clear OCDS Control Bits Bus Domain (w) */
|
||||
unsigned int OC2_P:1; /**< \brief [4:4] OC2 Write Protection (w) */
|
||||
unsigned int OC2:1; /**< \brief [5:5] Set/Clear OCDS Control Bits Bus Domain (w) */
|
||||
unsigned int OC3_P:1; /**< \brief [6:6] OC3 Write Protection (w) */
|
||||
unsigned int OC3:1; /**< \brief [7:7] Set/Clear OCDS Control Bits Bus Domain (w) */
|
||||
unsigned int OC4_P:1; /**< \brief [8:8] OC4 Write Protection (w) */
|
||||
unsigned int OC4:1; /**< \brief [9:9] Set/Clear OCDS Control Bits Bus Domain (w) */
|
||||
unsigned int OC5_P:1; /**< \brief [10:10] OC5 Write Protection (w) */
|
||||
unsigned int OC5:1; /**< \brief [11:11] Set/Clear OCDS Control Bits Bus Domain (w) */
|
||||
unsigned int WDTSUS_P:1; /**< \brief [12:12] WDTSUS Write Protection (w) */
|
||||
unsigned int WDTSUS:1; /**< \brief [13:13] Set/Clear Watchdog Timer Suspension Control (w) */
|
||||
unsigned int STABLE_P:1; /**< \brief [14:14] STABLE Write Protection (w) */
|
||||
unsigned int STABLE:1; /**< \brief [15:15] Initialize Application Reset Indication (w) */
|
||||
unsigned int OJC0_P:1; /**< \brief [16:16] OJC0 Write Protection (w) */
|
||||
unsigned int OJC0:1; /**< \brief [17:17] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
unsigned int OJC1_P:1; /**< \brief [18:18] OJC1 Write Protection (w) */
|
||||
unsigned int OJC1:1; /**< \brief [19:19] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
unsigned int OJC2_P:1; /**< \brief [20:20] OJC2 Write Protection (w) */
|
||||
unsigned int OJC2:1; /**< \brief [21:21] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
unsigned int OJC3_P:1; /**< \brief [22:22] OJC3 Write Protection (w) */
|
||||
unsigned int OJC3:1; /**< \brief [23:23] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
unsigned int OJC4_P:1; /**< \brief [24:24] OJC4 Write Protection (w) */
|
||||
unsigned int OJC4:1; /**< \brief [25:25] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
unsigned int OJC5_P:1; /**< \brief [26:26] OJC5 Write Protection (w) */
|
||||
unsigned int OJC5:1; /**< \brief [27:27] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
unsigned int OJC6_P:1; /**< \brief [28:28] OJC6 Write Protection (w) */
|
||||
unsigned int OJC6:1; /**< \brief [29:29] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
unsigned int OJC7_P:1; /**< \brief [30:30] OJC7 Write Protection (w) */
|
||||
unsigned int OJC7:1; /**< \brief [31:31] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
} Ifx_CBS_OCNTRL_Bits;
|
||||
|
||||
/** \brief OCDS Enable Control Register */
|
||||
typedef struct _Ifx_CBS_OEC_Bits
|
||||
{
|
||||
unsigned int PAT:8; /**< \brief [7:0] OCDS Enabling Pattern (w) */
|
||||
unsigned int DS:1; /**< \brief [8:8] Disable OCDS (w) */
|
||||
unsigned int OCO:1; /**< \brief [9:9] OCDS Clock Off (w) */
|
||||
unsigned int reserved_10:6; /**< \brief \internal Reserved */
|
||||
unsigned int IF_LCK_P:1; /**< \brief [16:16] IF_LCK Write Protection (w) */
|
||||
unsigned int IF_LCK:1; /**< \brief [17:17] Set/Clear Interface Locked Indication (w) */
|
||||
unsigned int AUT_OK_P:1; /**< \brief [18:18] AUT_OK Write Protection (w) */
|
||||
unsigned int AUT_OK:1; /**< \brief [19:19] Set/Clear the Authorization OK Indication (w) */
|
||||
unsigned int reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_OEC_Bits;
|
||||
|
||||
/** \brief OCDS Interface Mode Register */
|
||||
typedef struct _Ifx_CBS_OIFM_Bits
|
||||
{
|
||||
unsigned int DAPMODE:3; /**< \brief [2:0] DAP Interface Mode (rw) */
|
||||
unsigned int DAPRST:1; /**< \brief [3:3] DAP Protocol Clear (rwh) */
|
||||
unsigned int reserved_4:4; /**< \brief \internal Reserved */
|
||||
unsigned int F_JTAG:1; /**< \brief [8:8] Forced JTAG Mode (rw) */
|
||||
unsigned int N_JTAG:1; /**< \brief [9:9] No Switch to JTAG (rw) */
|
||||
unsigned int reserved_10:2; /**< \brief \internal Reserved */
|
||||
unsigned int PADCTL:4; /**< \brief [15:12] Pad Control for Debug Interface Pins (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_OIFM_Bits;
|
||||
|
||||
/** \brief OSCU Status Register */
|
||||
typedef struct _Ifx_CBS_OSTATE_Bits
|
||||
{
|
||||
unsigned int OEN:1; /**< \brief [0:0] OCDS Enabled Flag (rh) */
|
||||
unsigned int OC0:1; /**< \brief [1:1] OCDS Control Bits System Bus Domain (rh) */
|
||||
unsigned int OC1:1; /**< \brief [2:2] OCDS Control Bits System Bus Domain (rh) */
|
||||
unsigned int OC2:1; /**< \brief [3:3] OCDS Control Bits System Bus Domain (rh) */
|
||||
unsigned int ENIDIS:1; /**< \brief [4:4] OCDS ENDINIT Protection Override (rh) */
|
||||
unsigned int EECTRC:1; /**< \brief [5:5] On Chip Trace Enable (rh) */
|
||||
unsigned int EECDIS:1; /**< \brief [6:6] Emulation Logic Disable (rh) */
|
||||
unsigned int WDTSUS:1; /**< \brief [7:7] Control of Watchdog Timer Suspension (rh) */
|
||||
unsigned int HARR:1; /**< \brief [8:8] Halt after Reset Request (rh) */
|
||||
unsigned int OJC1:1; /**< \brief [9:9] OCDS Control Bits IOClient Domain (rh) */
|
||||
unsigned int OJC2:1; /**< \brief [10:10] OCDS Control Bits IOClient Domain (rh) */
|
||||
unsigned int OJC3:1; /**< \brief [11:11] OCDS Control Bits IOClient Domain (rh) */
|
||||
unsigned int RSTCL0:1; /**< \brief [12:12] OCDS System Reset Request (rh) */
|
||||
unsigned int RSTCL1:1; /**< \brief [13:13] OCDS Debug Reset Request (rh) */
|
||||
unsigned int OJC6:1; /**< \brief [14:14] OCDS Control Bits IOClient Domain (rh) */
|
||||
unsigned int RSTCL3:1; /**< \brief [15:15] OCDS Application Reset Request (rh) */
|
||||
unsigned int IF_LCK:1; /**< \brief [16:16] Interface Locked Indication (rh) */
|
||||
unsigned int AUT_OK:1; /**< \brief [17:17] Authorization OK Indication (rh) */
|
||||
unsigned int STABLE:1; /**< \brief [18:18] Application Reset Indication (rh) */
|
||||
unsigned int OCO:1; /**< \brief [19:19] OCDS debug resource Clock On Indication (rh) */
|
||||
unsigned int reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_OSTATE_Bits;
|
||||
|
||||
/** \brief TG Capture for Cores - BRKOUT */
|
||||
typedef struct _Ifx_CBS_TCCB_Bits
|
||||
{
|
||||
unsigned int C0:1; /**< \brief [0:0] Capture of BRKOUT Signal of CPU0 (rh) */
|
||||
unsigned int C1:1; /**< \brief [1:1] Capture of BRKOUT Signal of CPU1 (rh) */
|
||||
unsigned int C2:1; /**< \brief [2:2] Capture of BRKOUT Signal of CPU2 (rh) */
|
||||
unsigned int reserved_3:28; /**< \brief \internal Reserved */
|
||||
unsigned int HSM:1; /**< \brief [31:31] Capture of BRKOUT Signal of (rh) */
|
||||
} Ifx_CBS_TCCB_Bits;
|
||||
|
||||
/** \brief TG Capture for Cores - HALT */
|
||||
typedef struct _Ifx_CBS_TCCH_Bits
|
||||
{
|
||||
unsigned int C0:1; /**< \brief [0:0] Capture of HALT Signal of CPU0 (rh) */
|
||||
unsigned int C1:1; /**< \brief [1:1] Capture of HALT Signal of CPU1 (rh) */
|
||||
unsigned int C2:1; /**< \brief [2:2] Capture of HALT Signal of CPU2 (rh) */
|
||||
unsigned int reserved_3:28; /**< \brief \internal Reserved */
|
||||
unsigned int HSM:1; /**< \brief [31:31] Capture of HALT Signal of (rh) */
|
||||
} Ifx_CBS_TCCH_Bits;
|
||||
|
||||
/** \brief TG Capture for TG Input Pins */
|
||||
typedef struct _Ifx_CBS_TCIP_Bits
|
||||
{
|
||||
unsigned int P0:1; /**< \brief [0:0] Capture of Trigger Input Pin 0 (rh) */
|
||||
unsigned int P1:1; /**< \brief [1:1] Capture of Trigger Input Pin 1 (rh) */
|
||||
unsigned int P2:1; /**< \brief [2:2] Capture of Trigger Input Pin 2 (rh) */
|
||||
unsigned int P3:1; /**< \brief [3:3] Capture of Trigger Input Pin 3 (rh) */
|
||||
unsigned int P4:1; /**< \brief [4:4] Capture of Trigger Input Pin 4 (rh) */
|
||||
unsigned int P5:1; /**< \brief [5:5] Capture of Trigger Input Pin 5 (rh) */
|
||||
unsigned int P6:1; /**< \brief [6:6] Capture of Trigger Input Pin 6 (rh) */
|
||||
unsigned int P7:1; /**< \brief [7:7] Capture of Trigger Input Pin 7 (rh) */
|
||||
unsigned int reserved_8:24; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TCIP_Bits;
|
||||
|
||||
/** \brief TG Capture for MCDS */
|
||||
typedef struct _Ifx_CBS_TCM_Bits
|
||||
{
|
||||
unsigned int BRK:1; /**< \brief [0:0] Capture of MCDS break_out (rh) */
|
||||
unsigned int SUS:1; /**< \brief [1:1] Capture of MCDS suspend_out (rh) */
|
||||
unsigned int reserved_2:6; /**< \brief \internal Reserved */
|
||||
unsigned int T0:1; /**< \brief [8:8] Capture of MCDS trig_out 0 (rh) */
|
||||
unsigned int T1:1; /**< \brief [9:9] Capture of MCDS trig_out 1 (rh) */
|
||||
unsigned int T2:1; /**< \brief [10:10] Capture of MCDS trig_out 2 (rh) */
|
||||
unsigned int T3:1; /**< \brief [11:11] Capture of MCDS trig_out 3 (rh) */
|
||||
unsigned int reserved_12:20; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TCM_Bits;
|
||||
|
||||
/** \brief TG Capture for OTGB0/1 */
|
||||
typedef struct _Ifx_CBS_TCTGB_Bits
|
||||
{
|
||||
unsigned int OTGB0:16; /**< \brief [15:0] Capture Bits for OTGB0 (rh) */
|
||||
unsigned int OTGB1:16; /**< \brief [31:16] Capture Bits for OTGB1 (rh) */
|
||||
} Ifx_CBS_TCTGB_Bits;
|
||||
|
||||
/** \brief TG Capture for TG Lines */
|
||||
typedef struct _Ifx_CBS_TCTL_Bits
|
||||
{
|
||||
unsigned int reserved_0:1; /**< \brief \internal Reserved */
|
||||
unsigned int TL1:1; /**< \brief [1:1] Capture of Trigger Line 1 (rh) */
|
||||
unsigned int TL2:1; /**< \brief [2:2] Capture of Trigger Line 2 (rh) */
|
||||
unsigned int TL3:1; /**< \brief [3:3] Capture of Trigger Line 3 (rh) */
|
||||
unsigned int TL4:1; /**< \brief [4:4] Capture of Trigger Line 4 (rh) */
|
||||
unsigned int TL5:1; /**< \brief [5:5] Capture of Trigger Line 5 (rh) */
|
||||
unsigned int TL6:1; /**< \brief [6:6] Capture of Trigger Line 6 (rh) */
|
||||
unsigned int TL7:1; /**< \brief [7:7] Capture of Trigger Line 7 (rh) */
|
||||
unsigned int reserved_8:24; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TCTL_Bits;
|
||||
|
||||
/** \brief TG Input Pins Routing */
|
||||
typedef struct _Ifx_CBS_TIPR_Bits
|
||||
{
|
||||
unsigned int PIN0:4; /**< \brief [3:0] Trigger Pin 0 to Trigger Line Routing (rw) */
|
||||
unsigned int PIN1:4; /**< \brief [7:4] Trigger Pin 1 to Trigger Line Routing (rw) */
|
||||
unsigned int PIN2:4; /**< \brief [11:8] Trigger Pin 2 to Trigger Line Routing (rw) */
|
||||
unsigned int PIN3:4; /**< \brief [15:12] Trigger Pin 3 to Trigger Line Routing (rw) */
|
||||
unsigned int PIN4:4; /**< \brief [19:16] Trigger Pin 4 to Trigger Line Routing (rw) */
|
||||
unsigned int PIN5:4; /**< \brief [23:20] Trigger Pin 5 to Trigger Line Routing (rw) */
|
||||
unsigned int PIN6:4; /**< \brief [27:24] Trigger Pin 6 to Trigger Line Routing (rw) */
|
||||
unsigned int PIN7:4; /**< \brief [31:28] Trigger Pin 7 to Trigger Line Routing (rw) */
|
||||
} Ifx_CBS_TIPR_Bits;
|
||||
|
||||
/** \brief TG Line 1 Suspend Targets */
|
||||
typedef struct _Ifx_CBS_TL1ST_Bits
|
||||
{
|
||||
unsigned int C0:1; /**< \brief [0:0] CPU0 as Suspend Target (rw) */
|
||||
unsigned int C1:1; /**< \brief [1:1] CPU1 as Suspend Target (rw) */
|
||||
unsigned int C2:1; /**< \brief [2:2] CPU2 as Suspend Target (rw) */
|
||||
unsigned int reserved_3:25; /**< \brief \internal Reserved */
|
||||
unsigned int HSS:1; /**< \brief [28:28] HSSL as Suspend Target (rw) */
|
||||
unsigned int DMA:1; /**< \brief [29:29] DMA as Suspend Target (rw) */
|
||||
unsigned int reserved_30:1; /**< \brief \internal Reserved */
|
||||
unsigned int HSM:1; /**< \brief [31:31] as Suspend Target (rw) */
|
||||
} Ifx_CBS_TL1ST_Bits;
|
||||
|
||||
/** \brief TG Line Control */
|
||||
typedef struct _Ifx_CBS_TLC_Bits
|
||||
{
|
||||
unsigned int reserved_0:4; /**< \brief \internal Reserved */
|
||||
unsigned int TLSP1:4; /**< \brief [7:4] TG Line Signal Processing (rw) */
|
||||
unsigned int TLSP2:4; /**< \brief [11:8] TG Line Signal Processing (rw) */
|
||||
unsigned int TLSP3:4; /**< \brief [15:12] TG Line Signal Processing (rw) */
|
||||
unsigned int TLSP4:4; /**< \brief [19:16] TG Line Signal Processing (rw) */
|
||||
unsigned int TLSP5:4; /**< \brief [23:20] TG Line Signal Processing (rw) */
|
||||
unsigned int TLSP6:4; /**< \brief [27:24] TG Line Signal Processing (rw) */
|
||||
unsigned int TLSP7:4; /**< \brief [31:28] TG Line Signal Processing (rw) */
|
||||
} Ifx_CBS_TLC_Bits;
|
||||
|
||||
/** \brief TG Line Counter Control */
|
||||
typedef struct _Ifx_CBS_TLCC_Bits
|
||||
{
|
||||
unsigned int TGL:4; /**< \brief [3:0] Trigger Line to Counter Routing (rw) */
|
||||
unsigned int LE:3; /**< \brief [6:4] Level or Edge Counting (rw) */
|
||||
unsigned int reserved_7:1; /**< \brief \internal Reserved */
|
||||
unsigned int CLR:2; /**< \brief [9:8] Clear and Enable Counter(s) (w) */
|
||||
unsigned int reserved_10:2; /**< \brief \internal Reserved */
|
||||
unsigned int STOP:2; /**< \brief [13:12] Stop Counter(s) (w) */
|
||||
unsigned int reserved_14:18; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TLCC_Bits;
|
||||
|
||||
/** \brief TG Line Capture and Hold Enable */
|
||||
typedef struct _Ifx_CBS_TLCHE_Bits
|
||||
{
|
||||
unsigned int reserved_0:1; /**< \brief \internal Reserved */
|
||||
unsigned int TL1:1; /**< \brief [1:1] Capture and Hold Enable for Trigger Line 1 (rw) */
|
||||
unsigned int TL2:1; /**< \brief [2:2] Capture and Hold Enable for Trigger Line 2 (rw) */
|
||||
unsigned int TL3:1; /**< \brief [3:3] Capture and Hold Enable for Trigger Line 3 (rw) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TLCHE_Bits;
|
||||
|
||||
/** \brief TG Line Capture and Hold Clear */
|
||||
typedef struct _Ifx_CBS_TLCHS_Bits
|
||||
{
|
||||
unsigned int reserved_0:1; /**< \brief \internal Reserved */
|
||||
unsigned int TL1:1; /**< \brief [1:1] Capture and Hold Clear for Trigger Line 1 (w) */
|
||||
unsigned int TL2:1; /**< \brief [2:2] Capture and Hold Clear for Trigger Line 2 (w) */
|
||||
unsigned int TL3:1; /**< \brief [3:3] Capture and Hold Clear for Trigger Line 3 (w) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TLCHS_Bits;
|
||||
|
||||
/** \brief TG Line Counter Value */
|
||||
typedef struct _Ifx_CBS_TLCV_Bits
|
||||
{
|
||||
unsigned int CV:31; /**< \brief [30:0] Count Value (rh) */
|
||||
unsigned int SO:1; /**< \brief [31:31] Sticky Overflow Bit (rh) */
|
||||
} Ifx_CBS_TLCV_Bits;
|
||||
|
||||
/** \brief TG Line State */
|
||||
typedef struct _Ifx_CBS_TLS_Bits
|
||||
{
|
||||
unsigned int reserved_0:1; /**< \brief \internal Reserved */
|
||||
unsigned int TL1:1; /**< \brief [1:1] Current State of Trigger Line 1 (rh) */
|
||||
unsigned int TL2:1; /**< \brief [2:2] Current State of Trigger Line 2 (rh) */
|
||||
unsigned int TL3:1; /**< \brief [3:3] Current State of Trigger Line 3 (rh) */
|
||||
unsigned int TL4:1; /**< \brief [4:4] Current State of Trigger Line 4 (rh) */
|
||||
unsigned int TL5:1; /**< \brief [5:5] Current State of Trigger Line 5 (rh) */
|
||||
unsigned int TL6:1; /**< \brief [6:6] Current State of Trigger Line 6 (rh) */
|
||||
unsigned int TL7:1; /**< \brief [7:7] Current State of Trigger Line 7 (rh) */
|
||||
unsigned int reserved_8:24; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TLS_Bits;
|
||||
|
||||
/** \brief TG Line Timer */
|
||||
typedef struct _Ifx_CBS_TLT_Bits
|
||||
{
|
||||
unsigned int TGL:4; /**< \brief [3:0] Timer to Trigger Line Routing (rw) */
|
||||
unsigned int VTZ:1; /**< \brief [4:4] TG Line Value when Timer Value is Zero (rw) */
|
||||
unsigned int reserved_5:11; /**< \brief \internal Reserved */
|
||||
unsigned int TIM:16; /**< \brief [31:16] Timer Value (rwh) */
|
||||
} Ifx_CBS_TLT_Bits;
|
||||
|
||||
/** \brief TG Lines for Trigger to Host */
|
||||
typedef struct _Ifx_CBS_TLTTH_Bits
|
||||
{
|
||||
unsigned int reserved_0:2; /**< \brief \internal Reserved */
|
||||
unsigned int TL1:2; /**< \brief [3:2] TG Line Enabling for Trigger to Host (TRIG) (rw) */
|
||||
unsigned int TL2:2; /**< \brief [5:4] TG Line Enabling for Trigger to Host (TRIG) (rw) */
|
||||
unsigned int TL3:2; /**< \brief [7:6] TG Line Enabling for Trigger to Host (TRIG) (rw) */
|
||||
unsigned int TL4:2; /**< \brief [9:8] TG Line Enabling for Trigger to Host (TRIG) (rw) */
|
||||
unsigned int TL5:2; /**< \brief [11:10] TG Line Enabling for Trigger to Host (TRIG) (rw) */
|
||||
unsigned int TL6:2; /**< \brief [13:12] TG Line Enabling for Trigger to Host (TRIG) (rw) */
|
||||
unsigned int TL7:2; /**< \brief [15:14] TG Line Enabling for Trigger to Host (TRIG) (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TLTTH_Bits;
|
||||
|
||||
/** \brief TG Output Pins Pulse Stretcher */
|
||||
typedef struct _Ifx_CBS_TOPPS_Bits
|
||||
{
|
||||
unsigned int PIN0:2; /**< \brief [1:0] Pulse Stretch Control for Trigger Pin 0 (rw) */
|
||||
unsigned int PIN1:2; /**< \brief [3:2] Pulse Stretch Control for Trigger Pin 1 (rw) */
|
||||
unsigned int PIN2:2; /**< \brief [5:4] Pulse Stretch Control for Trigger Pin 2 (rw) */
|
||||
unsigned int PIN3:2; /**< \brief [7:6] Pulse Stretch Control for Trigger Pin 3 (rw) */
|
||||
unsigned int PIN4:2; /**< \brief [9:8] Pulse Stretch Control for Trigger Pin 4 (rw) */
|
||||
unsigned int PIN5:2; /**< \brief [11:10] Pulse Stretch Control for Trigger Pin 5 (rw) */
|
||||
unsigned int PIN6:2; /**< \brief [13:12] Pulse Stretch Control for Trigger Pin 6 (rw) */
|
||||
unsigned int PIN7:2; /**< \brief [15:14] Pulse Stretch Control for Trigger Pin 7 (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TOPPS_Bits;
|
||||
|
||||
/** \brief TG Output Pins Routing */
|
||||
typedef struct _Ifx_CBS_TOPR_Bits
|
||||
{
|
||||
unsigned int PIN0:4; /**< \brief [3:0] Trigger Line to Trigger Pin 0 Routing (rw) */
|
||||
unsigned int PIN1:4; /**< \brief [7:4] Trigger Line to Trigger Pin 1 Routing (rw) */
|
||||
unsigned int PIN2:4; /**< \brief [11:8] Trigger Line to Trigger Pin 2 Routing (rw) */
|
||||
unsigned int PIN3:4; /**< \brief [15:12] Trigger Line to Trigger Pin 3 Routing (rw) */
|
||||
unsigned int PIN4:4; /**< \brief [19:16] Trigger Line to Trigger Pin 4 Routing (rw) */
|
||||
unsigned int PIN5:4; /**< \brief [23:20] Trigger Line to Trigger Pin 5 Routing (rw) */
|
||||
unsigned int PIN6:4; /**< \brief [27:24] Trigger Line to Trigger Pin 6 Routing (rw) */
|
||||
unsigned int PIN7:4; /**< \brief [31:28] Trigger Line to Trigger Pin 7 Routing (rw) */
|
||||
} Ifx_CBS_TOPR_Bits;
|
||||
|
||||
/** \brief TG Routing for CPU */
|
||||
typedef struct _Ifx_CBS_TRC_Bits
|
||||
{
|
||||
unsigned int HALT:4; /**< \brief [3:0] HALT to Trigger Line Routing (rw) */
|
||||
unsigned int BRKOUT:4; /**< \brief [7:4] BRKOUT to Trigger Line Routing (rw) */
|
||||
unsigned int BT1:1; /**< \brief [8:8] BRKOUT to Trigger Line 1 Routing (rw) */
|
||||
unsigned int reserved_9:11; /**< \brief \internal Reserved */
|
||||
unsigned int BRKIN:4; /**< \brief [23:20] Trigger Line to BRKIN Routing (rw) */
|
||||
unsigned int SUSIN:4; /**< \brief [27:24] Trigger Line to SUSIN Routing (rw) */
|
||||
unsigned int reserved_28:4; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TRC_Bits;
|
||||
|
||||
/** \brief TG Routing Events of CPU */
|
||||
typedef struct _Ifx_CBS_TREC_Bits
|
||||
{
|
||||
unsigned int TR0EV:4; /**< \brief [3:0] TRxEVT to Trigger Line Routing (rw) */
|
||||
unsigned int reserved_4:4; /**< \brief \internal Reserved */
|
||||
unsigned int TR2EV:4; /**< \brief [11:8] TRxEVT to Trigger Line Routing (rw) */
|
||||
unsigned int reserved_12:4; /**< \brief \internal Reserved */
|
||||
unsigned int TR4EV:4; /**< \brief [19:16] TRxEVT to Trigger Line Routing (rw) */
|
||||
unsigned int reserved_20:4; /**< \brief \internal Reserved */
|
||||
unsigned int TR6EV:4; /**< \brief [27:24] TRxEVT to Trigger Line Routing (rw) */
|
||||
unsigned int reserved_28:4; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TREC_Bits;
|
||||
|
||||
/** \brief Trigger to Host Register */
|
||||
typedef struct _Ifx_CBS_TRIG_Bits
|
||||
{
|
||||
unsigned int TRGx_0:1; /**< \brief [0:0] Service Request Bits (rh) */
|
||||
unsigned int TRGx_1:1; /**< \brief [1:1] Service Request Bits (rh) */
|
||||
unsigned int TRGx_2:1; /**< \brief [2:2] Service Request Bits (rh) */
|
||||
unsigned int TRGx_3:1; /**< \brief [3:3] Service Request Bits (rh) */
|
||||
unsigned int TRGx_4:1; /**< \brief [4:4] Service Request Bits (rh) */
|
||||
unsigned int TRGx_5:1; /**< \brief [5:5] Service Request Bits (rh) */
|
||||
unsigned int TRGx_6:1; /**< \brief [6:6] Service Request Bits (rh) */
|
||||
unsigned int TRGx_7:1; /**< \brief [7:7] Service Request Bits (rh) */
|
||||
unsigned int TRGx_8:1; /**< \brief [8:8] Service Request Bits (rh) */
|
||||
unsigned int TRGx_9:1; /**< \brief [9:9] Service Request Bits (rh) */
|
||||
unsigned int TRGx_10:1; /**< \brief [10:10] Service Request Bits (rh) */
|
||||
unsigned int TRGx_11:1; /**< \brief [11:11] Service Request Bits (rh) */
|
||||
unsigned int TRGx_12:1; /**< \brief [12:12] Service Request Bits (rh) */
|
||||
unsigned int TRGx_13:1; /**< \brief [13:13] Service Request Bits (rh) */
|
||||
unsigned int TRGx_14:1; /**< \brief [14:14] Service Request Bits (rh) */
|
||||
unsigned int TRGx_15:1; /**< \brief [15:15] Service Request Bits (rh) */
|
||||
unsigned int TRGx_16:1; /**< \brief [16:16] Service Request Bits (rh) */
|
||||
unsigned int TRGx_17:1; /**< \brief [17:17] Service Request Bits (rh) */
|
||||
unsigned int TRGx_18:1; /**< \brief [18:18] Service Request Bits (rh) */
|
||||
unsigned int TRGx_19:1; /**< \brief [19:19] Service Request Bits (rh) */
|
||||
unsigned int TRGx_20:1; /**< \brief [20:20] Service Request Bits (rh) */
|
||||
unsigned int TRGx_21:1; /**< \brief [21:21] Service Request Bits (rh) */
|
||||
unsigned int TRGx_22:1; /**< \brief [22:22] Service Request Bits (rh) */
|
||||
unsigned int TRGx_23:1; /**< \brief [23:23] Service Request Bits (rh) */
|
||||
unsigned int x:8; /**< \brief [31:24] TRIG register number (rh) */
|
||||
} Ifx_CBS_TRIG_Bits;
|
||||
|
||||
/** \brief Clear Trigger to Host Register */
|
||||
typedef struct _Ifx_CBS_TRIGC_Bits
|
||||
{
|
||||
unsigned int TRGx_0:1; /**< \brief [0:0] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_1:1; /**< \brief [1:1] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_2:1; /**< \brief [2:2] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_3:1; /**< \brief [3:3] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_4:1; /**< \brief [4:4] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_5:1; /**< \brief [5:5] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_6:1; /**< \brief [6:6] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_7:1; /**< \brief [7:7] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_8:1; /**< \brief [8:8] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_9:1; /**< \brief [9:9] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_10:1; /**< \brief [10:10] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_11:1; /**< \brief [11:11] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_12:1; /**< \brief [12:12] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_13:1; /**< \brief [13:13] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_14:1; /**< \brief [14:14] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_15:1; /**< \brief [15:15] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_16:1; /**< \brief [16:16] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_17:1; /**< \brief [17:17] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_18:1; /**< \brief [18:18] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_19:1; /**< \brief [19:19] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_20:1; /**< \brief [20:20] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_21:1; /**< \brief [21:21] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_22:1; /**< \brief [22:22] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_23:1; /**< \brief [23:23] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int x:8; /**< \brief [31:24] Index of most important register TRIGx (rh) */
|
||||
} Ifx_CBS_TRIGC_Bits;
|
||||
|
||||
/** \brief Set Trigger to Host Register */
|
||||
typedef struct _Ifx_CBS_TRIGS_Bits
|
||||
{
|
||||
unsigned int BITNUM:13; /**< \brief [12:0] Service Request Bit Number to Set (w) */
|
||||
unsigned int reserved_13:19; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TRIGS_Bits;
|
||||
|
||||
/** \brief TG Routing for MCDS Control */
|
||||
typedef struct _Ifx_CBS_TRMC_Bits
|
||||
{
|
||||
unsigned int reserved_0:4; /**< \brief \internal Reserved */
|
||||
unsigned int BRKOUT:4; /**< \brief [7:4] MCDS break_out to Trigger Line Routing (rw) */
|
||||
unsigned int SUSOUT:4; /**< \brief [11:8] MCDS suspend_out to Trigger Line Routing (rw) */
|
||||
unsigned int reserved_12:8; /**< \brief \internal Reserved */
|
||||
unsigned int BRKIN:4; /**< \brief [23:20] Trigger Line to MCDS break_in Routing (rw) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TRMC_Bits;
|
||||
|
||||
/** \brief TG Routing for MCDS Triggers */
|
||||
typedef struct _Ifx_CBS_TRMT_Bits
|
||||
{
|
||||
unsigned int TG0:4; /**< \brief [3:0] MCDS trig_out 0 to Trigger Line Routing (rw) */
|
||||
unsigned int TG1:4; /**< \brief [7:4] MCDS trig_out 1 to Trigger Line Routing (rw) */
|
||||
unsigned int TG2:4; /**< \brief [11:8] MCDS trig_out 2 to Trigger Line Routing (rw) */
|
||||
unsigned int TG3:4; /**< \brief [15:12] MCDS trig_out 3 to Trigger Line Routing (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TRMT_Bits;
|
||||
|
||||
/** \brief TG Routing for Special Signals */
|
||||
typedef struct _Ifx_CBS_TRSS_Bits
|
||||
{
|
||||
unsigned int TT:4; /**< \brief [3:0] Trigger Line to Cerberus’ Triggered Transfer Routing (rw) */
|
||||
unsigned int reserved_4:12; /**< \brief \internal Reserved */
|
||||
unsigned int SRC0:4; /**< \brief [19:16] Trigger Line to SRC0 Interrupt Routing (rw) */
|
||||
unsigned int SRC1:4; /**< \brief [23:20] Trigger Line to SRC1 Interrupt Routing (rw) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TRSS_Bits;
|
||||
|
||||
/** \brief TG Routing for OTGB Bits [15:8] */
|
||||
typedef struct _Ifx_CBS_TRTGB_H_Bits
|
||||
{
|
||||
unsigned int TG8:4; /**< \brief [3:0] (rw) */
|
||||
unsigned int TG9:4; /**< \brief [7:4] (rw) */
|
||||
unsigned int TG10:4; /**< \brief [11:8] (rw) */
|
||||
unsigned int TG11:4; /**< \brief [15:12] (rw) */
|
||||
unsigned int TG12:4; /**< \brief [19:16] (rw) */
|
||||
unsigned int TG13:4; /**< \brief [23:20] (rw) */
|
||||
unsigned int TG14:4; /**< \brief [27:24] (rw) */
|
||||
unsigned int TG15:4; /**< \brief [31:28] (rw) */
|
||||
} Ifx_CBS_TRTGB_H_Bits;
|
||||
|
||||
/** \brief TG Routing for OTGB Bits [7:0] */
|
||||
typedef struct _Ifx_CBS_TRTGB_L_Bits
|
||||
{
|
||||
unsigned int TG0:4; /**< \brief [3:0] (rw) */
|
||||
unsigned int TG1:4; /**< \brief [7:4] (rw) */
|
||||
unsigned int TG2:4; /**< \brief [11:8] (rw) */
|
||||
unsigned int TG3:4; /**< \brief [15:12] (rw) */
|
||||
unsigned int TG4:4; /**< \brief [19:16] (rw) */
|
||||
unsigned int TG5:4; /**< \brief [23:20] (rw) */
|
||||
unsigned int TG6:4; /**< \brief [27:24] (rw) */
|
||||
unsigned int TG7:4; /**< \brief [31:28] (rw) */
|
||||
} Ifx_CBS_TRTGB_L_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Cbs_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Communication Mode Data Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_COMDATA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_COMDATA;
|
||||
|
||||
/** \brief Internally Controlled Trace Source Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_ICTSA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_ICTSA;
|
||||
|
||||
/** \brief Internally Controlled Trace Destination Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_ICTTA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_ICTTA;
|
||||
|
||||
/** \brief Internal Mode Status and Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_INTMOD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_INTMOD;
|
||||
|
||||
/** \brief IOClient Status and Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_IOSR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_IOSR;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_JDPID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_JDPID;
|
||||
|
||||
/** \brief JTAG Device Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_JTAGID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_JTAGID;
|
||||
|
||||
/** \brief OSCU Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_OCNTRL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_OCNTRL;
|
||||
|
||||
/** \brief OCDS Enable Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_OEC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_OEC;
|
||||
|
||||
/** \brief OCDS Interface Mode Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_OIFM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_OIFM;
|
||||
|
||||
/** \brief OSCU Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_OSTATE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_OSTATE;
|
||||
|
||||
/** \brief TG Capture for Cores - BRKOUT */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TCCB_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TCCB;
|
||||
|
||||
/** \brief TG Capture for Cores - HALT */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TCCH_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TCCH;
|
||||
|
||||
/** \brief TG Capture for TG Input Pins */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TCIP_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TCIP;
|
||||
|
||||
/** \brief TG Capture for MCDS */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TCM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TCM;
|
||||
|
||||
/** \brief TG Capture for OTGB0/1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TCTGB_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TCTGB;
|
||||
|
||||
/** \brief TG Capture for TG Lines */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TCTL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TCTL;
|
||||
|
||||
/** \brief TG Input Pins Routing */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TIPR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TIPR;
|
||||
|
||||
/** \brief TG Line 1 Suspend Targets */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TL1ST_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TL1ST;
|
||||
|
||||
/** \brief TG Line Control */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLC;
|
||||
|
||||
/** \brief TG Line Counter Control */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLCC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLCC;
|
||||
|
||||
/** \brief TG Line Capture and Hold Enable */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLCHE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLCHE;
|
||||
|
||||
/** \brief TG Line Capture and Hold Clear */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLCHS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLCHS;
|
||||
|
||||
/** \brief TG Line Counter Value */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLCV_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLCV;
|
||||
|
||||
/** \brief TG Line State */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLS;
|
||||
|
||||
/** \brief TG Line Timer */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLT;
|
||||
|
||||
/** \brief TG Lines for Trigger to Host */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLTTH_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLTTH;
|
||||
|
||||
/** \brief TG Output Pins Pulse Stretcher */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TOPPS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TOPPS;
|
||||
|
||||
/** \brief TG Output Pins Routing */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TOPR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TOPR;
|
||||
|
||||
/** \brief TG Routing for CPU */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRC;
|
||||
|
||||
/** \brief TG Routing Events of CPU */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TREC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TREC;
|
||||
|
||||
/** \brief Trigger to Host Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRIG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRIG;
|
||||
|
||||
/** \brief Clear Trigger to Host Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRIGC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRIGC;
|
||||
|
||||
/** \brief Set Trigger to Host Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRIGS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRIGS;
|
||||
|
||||
/** \brief TG Routing for MCDS Control */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRMC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRMC;
|
||||
|
||||
/** \brief TG Routing for MCDS Triggers */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRMT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRMT;
|
||||
|
||||
/** \brief TG Routing for Special Signals */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRSS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRSS;
|
||||
|
||||
/** \brief TG Routing for OTGB Bits [15:8] */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRTGB_H_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRTGB_H;
|
||||
|
||||
/** \brief TG Routing for OTGB Bits [7:0] */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRTGB_L_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRTGB_L;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Cbs_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L1
|
||||
* \{ */
|
||||
|
||||
/** \brief TG Routing for OTGB */
|
||||
typedef volatile struct _Ifx_CBS_TRTGB
|
||||
{
|
||||
Ifx_CBS_TRTGB_L L; /**< \brief 0, TG Routing for OTGB Bits [7:0] */
|
||||
Ifx_CBS_TRTGB_H H; /**< \brief 4, TG Routing for OTGB Bits [15:8] */
|
||||
} Ifx_CBS_TRTGB;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Cbs_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief CBS object */
|
||||
typedef volatile struct _Ifx_CBS
|
||||
{
|
||||
unsigned char reserved_0[8]; /**< \brief 0, \internal Reserved */
|
||||
Ifx_CBS_JDPID JDPID; /**< \brief 8, Module Identification Register */
|
||||
Ifx_CBS_OIFM OIFM; /**< \brief C, OCDS Interface Mode Register */
|
||||
Ifx_CBS_TIPR TIPR; /**< \brief 10, TG Input Pins Routing */
|
||||
Ifx_CBS_TOPR TOPR; /**< \brief 14, TG Output Pins Routing */
|
||||
Ifx_CBS_TOPPS TOPPS; /**< \brief 18, TG Output Pins Pulse Stretcher */
|
||||
Ifx_CBS_TCIP TCIP; /**< \brief 1C, TG Capture for TG Input Pins */
|
||||
Ifx_CBS_TRC TRC[2]; /**< \brief 20, TG Routing for CPU */
|
||||
unsigned char reserved_28[20]; /**< \brief 28, \internal Reserved */
|
||||
Ifx_CBS_TRMC TRMC; /**< \brief 3C, TG Routing for MCDS Control */
|
||||
Ifx_CBS_TLCC TLCC[2]; /**< \brief 40, TG Line Counter Control */
|
||||
unsigned char reserved_48[8]; /**< \brief 48, \internal Reserved */
|
||||
Ifx_CBS_TLCV TLCV[2]; /**< \brief 50, TG Line Counter Value */
|
||||
unsigned char reserved_58[8]; /**< \brief 58, \internal Reserved */
|
||||
Ifx_CBS_TRSS TRSS; /**< \brief 60, TG Routing for Special Signals */
|
||||
Ifx_CBS_JTAGID JTAGID; /**< \brief 64, JTAG Device Identification Register */
|
||||
Ifx_CBS_COMDATA COMDATA; /**< \brief 68, Communication Mode Data Register */
|
||||
Ifx_CBS_IOSR IOSR; /**< \brief 6C, IOClient Status and Control Register */
|
||||
Ifx_CBS_TLS TLS; /**< \brief 70, TG Line State */
|
||||
Ifx_CBS_TCTL TCTL; /**< \brief 74, TG Capture for TG Lines */
|
||||
Ifx_CBS_OEC OEC; /**< \brief 78, OCDS Enable Control Register */
|
||||
Ifx_CBS_OCNTRL OCNTRL; /**< \brief 7C, OSCU Control Register */
|
||||
Ifx_CBS_OSTATE OSTATE; /**< \brief 80, OSCU Status Register */
|
||||
Ifx_CBS_INTMOD INTMOD; /**< \brief 84, Internal Mode Status and Control Register */
|
||||
Ifx_CBS_ICTSA ICTSA; /**< \brief 88, Internally Controlled Trace Source Register */
|
||||
Ifx_CBS_ICTTA ICTTA; /**< \brief 8C, Internally Controlled Trace Destination Register */
|
||||
Ifx_CBS_TLC TLC; /**< \brief 90, TG Line Control */
|
||||
Ifx_CBS_TL1ST TL1ST; /**< \brief 94, TG Line 1 Suspend Targets */
|
||||
Ifx_CBS_TLCHE TLCHE; /**< \brief 98, TG Line Capture and Hold Enable */
|
||||
Ifx_CBS_TLCHS TLCHS; /**< \brief 9C, TG Line Capture and Hold Clear */
|
||||
Ifx_CBS_TRIGS TRIGS; /**< \brief A0, Set Trigger to Host Register */
|
||||
Ifx_CBS_TRIGC TRIGC; /**< \brief A4, Clear Trigger to Host Register */
|
||||
Ifx_CBS_TLT TLT; /**< \brief A8, TG Line Timer */
|
||||
Ifx_CBS_TLTTH TLTTH; /**< \brief AC, TG Lines for Trigger to Host */
|
||||
Ifx_CBS_TCCB TCCB; /**< \brief B0, TG Capture for Cores - BRKOUT */
|
||||
Ifx_CBS_TCCH TCCH; /**< \brief B4, TG Capture for Cores - HALT */
|
||||
Ifx_CBS_TCTGB TCTGB; /**< \brief B8, TG Capture for OTGB0/1 */
|
||||
Ifx_CBS_TCM TCM; /**< \brief BC, TG Capture for MCDS */
|
||||
Ifx_CBS_TREC TREC[2]; /**< \brief C0, TG Routing Events of CPU */
|
||||
unsigned char reserved_C8[20]; /**< \brief C8, \internal Reserved */
|
||||
Ifx_CBS_TRMT TRMT; /**< \brief DC, TG Routing for MCDS Triggers */
|
||||
Ifx_CBS_TRTGB TRTGB[2]; /**< \brief E0, TG Routing for OTGB */
|
||||
unsigned char reserved_F0[16]; /**< \brief F0, \internal Reserved */
|
||||
Ifx_CBS_TRIG TRIG[22]; /**< \brief 100, Trigger to Host Register */
|
||||
unsigned char reserved_158[168]; /**< \brief 158, \internal Reserved */
|
||||
} Ifx_CBS;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXCBS_REGDEF_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,329 +0,0 @@
|
||||
/**
|
||||
* \file IfxCcu6_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Ccu6_Cfg Ccu6 address
|
||||
* \ingroup IfxLld_Ccu6
|
||||
*
|
||||
* \defgroup IfxLld_Ccu6_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Ccu6_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Ccu6_Cfg_Ccu60 2-CCU60
|
||||
* \ingroup IfxLld_Ccu6_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Ccu6_Cfg_Ccu61 2-CCU61
|
||||
* \ingroup IfxLld_Ccu6_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXCCU6_REG_H
|
||||
#define IFXCCU6_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxCcu6_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ccu6_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief CCU6 object */
|
||||
#define MODULE_CCU60 /*lint --e(923)*/ (*(Ifx_CCU6*)0xF0002A00u)
|
||||
|
||||
/** \brief CCU6 object */
|
||||
#define MODULE_CCU61 /*lint --e(923)*/ (*(Ifx_CCU6*)0xF0002B00u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ccu6_Cfg_Ccu60
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define CCU60_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_ACCEN0*)0xF0002AFCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define CCU60_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_CCU6_ACCEN1*)0xF0002AF8u)
|
||||
|
||||
/** \brief 30, Capture/Compare Register for Channel CC60 */
|
||||
#define CCU60_CC60R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC60R*)0xF0002A30u)
|
||||
|
||||
/** \brief 40, Capture/Compare Shadow Reg. for Channel CC60 */
|
||||
#define CCU60_CC60SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC60SR*)0xF0002A40u)
|
||||
|
||||
/** \brief 34, Capture/Compare Register for Channel CC61 */
|
||||
#define CCU60_CC61R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC61R*)0xF0002A34u)
|
||||
|
||||
/** \brief 44, Capture/Compare Shadow Reg. for Channel CC61 */
|
||||
#define CCU60_CC61SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC61SR*)0xF0002A44u)
|
||||
|
||||
/** \brief 38, Capture/Compare Register for Channel CC62 */
|
||||
#define CCU60_CC62R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC62R*)0xF0002A38u)
|
||||
|
||||
/** \brief 48, Capture/Compare Shadow Reg. for Channel CC62 */
|
||||
#define CCU60_CC62SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC62SR*)0xF0002A48u)
|
||||
|
||||
/** \brief 58, Compare Register for T13 */
|
||||
#define CCU60_CC63R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC63R*)0xF0002A58u)
|
||||
|
||||
/** \brief 5C, Compare Shadow Register for T13 */
|
||||
#define CCU60_CC63SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC63SR*)0xF0002A5Cu)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define CCU60_CLC /*lint --e(923)*/ (*(volatile Ifx_CCU6_CLC*)0xF0002A00u)
|
||||
|
||||
/** \brief 64, Compare State Modification Register */
|
||||
#define CCU60_CMPMODIF /*lint --e(923)*/ (*(volatile Ifx_CCU6_CMPMODIF*)0xF0002A64u)
|
||||
|
||||
/** \brief 60, Compare State Register */
|
||||
#define CCU60_CMPSTAT /*lint --e(923)*/ (*(volatile Ifx_CCU6_CMPSTAT*)0xF0002A60u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define CCU60_ID /*lint --e(923)*/ (*(volatile Ifx_CCU6_ID*)0xF0002A08u)
|
||||
|
||||
/** \brief B0, Interrupt Enable Register */
|
||||
#define CCU60_IEN /*lint --e(923)*/ (*(volatile Ifx_CCU6_IEN*)0xF0002AB0u)
|
||||
|
||||
/** \brief 98, Input Monitoring Register */
|
||||
#define CCU60_IMON /*lint --e(923)*/ (*(volatile Ifx_CCU6_IMON*)0xF0002A98u)
|
||||
|
||||
/** \brief AC, Interrupt Node Pointer Register */
|
||||
#define CCU60_INP /*lint --e(923)*/ (*(volatile Ifx_CCU6_INP*)0xF0002AACu)
|
||||
|
||||
/** \brief A0, Interrupt Status Register */
|
||||
#define CCU60_IS /*lint --e(923)*/ (*(volatile Ifx_CCU6_IS*)0xF0002AA0u)
|
||||
|
||||
/** \brief A8, Interrupt Status Reset Register */
|
||||
#define CCU60_ISR /*lint --e(923)*/ (*(volatile Ifx_CCU6_ISR*)0xF0002AA8u)
|
||||
|
||||
/** \brief A4, Interrupt Status Set Register */
|
||||
#define CCU60_ISS /*lint --e(923)*/ (*(volatile Ifx_CCU6_ISS*)0xF0002AA4u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define CCU60_KRST0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRST0*)0xF0002AF4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define CCU60_KRST1 /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRST1*)0xF0002AF0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define CCU60_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRSTCLR*)0xF0002AECu)
|
||||
|
||||
/** \brief 1C, Kernel State Control Sensitivity Register */
|
||||
#define CCU60_KSCSR /*lint --e(923)*/ (*(volatile Ifx_CCU6_KSCSR*)0xF0002A1Cu)
|
||||
|
||||
/** \brief 9C, Lost Indicator Register */
|
||||
#define CCU60_LI /*lint --e(923)*/ (*(volatile Ifx_CCU6_LI*)0xF0002A9Cu)
|
||||
|
||||
/** \brief 4, Module Configuration Register */
|
||||
#define CCU60_MCFG /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCFG*)0xF0002A04u)
|
||||
|
||||
/** \brief 94, Multi-Channel Mode Control Register */
|
||||
#define CCU60_MCMCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMCTR*)0xF0002A94u)
|
||||
|
||||
/** \brief 90, Multi-Channel Mode Output Register */
|
||||
#define CCU60_MCMOUT /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMOUT*)0xF0002A90u)
|
||||
|
||||
/** \brief 8C, Multi-Channel Mode Output Shadow Register */
|
||||
#define CCU60_MCMOUTS /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMOUTS*)0xF0002A8Cu)
|
||||
|
||||
/** \brief 80, Modulation Control Register */
|
||||
#define CCU60_MODCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_MODCTR*)0xF0002A80u)
|
||||
|
||||
/** \brief C, CCU60 Module Output Select Register */
|
||||
#define CCU60_MOSEL /*lint --e(923)*/ (*(volatile Ifx_CCU6_MOSEL*)0xF0002A0Cu)
|
||||
|
||||
/** \brief E8, OCDS Control and Status Register */
|
||||
#define CCU60_OCS /*lint --e(923)*/ (*(volatile Ifx_CCU6_OCS*)0xF0002AE8u)
|
||||
|
||||
/** \brief 10, Port Input Select Register 0 */
|
||||
#define CCU60_PISEL0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_PISEL0*)0xF0002A10u)
|
||||
|
||||
/** \brief 14, Port Input Select Register 2 */
|
||||
#define CCU60_PISEL2 /*lint --e(923)*/ (*(volatile Ifx_CCU6_PISEL2*)0xF0002A14u)
|
||||
|
||||
/** \brief 88, Passive State Level Register */
|
||||
#define CCU60_PSLR /*lint --e(923)*/ (*(volatile Ifx_CCU6_PSLR*)0xF0002A88u)
|
||||
|
||||
/** \brief 20, Timer T12 Counter Register */
|
||||
#define CCU60_T12 /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12*)0xF0002A20u)
|
||||
|
||||
/** \brief 28, Dead-Time Control Register for Timer12 */
|
||||
#define CCU60_T12DTC /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12DTC*)0xF0002A28u)
|
||||
|
||||
/** \brief 68, T12 Mode Select Register */
|
||||
#define CCU60_T12MSEL /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12MSEL*)0xF0002A68u)
|
||||
|
||||
/** \brief 24, Timer 12 Period Register */
|
||||
#define CCU60_T12PR /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12PR*)0xF0002A24u)
|
||||
|
||||
/** \brief 50, Timer T13 Counter Register */
|
||||
#define CCU60_T13 /*lint --e(923)*/ (*(volatile Ifx_CCU6_T13*)0xF0002A50u)
|
||||
|
||||
/** \brief 54, Timer 13 Period Register */
|
||||
#define CCU60_T13PR /*lint --e(923)*/ (*(volatile Ifx_CCU6_T13PR*)0xF0002A54u)
|
||||
|
||||
/** \brief 70, Timer Control Register 0 */
|
||||
#define CCU60_TCTR0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR0*)0xF0002A70u)
|
||||
|
||||
/** \brief 74, Timer Control Register 2 */
|
||||
#define CCU60_TCTR2 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR2*)0xF0002A74u)
|
||||
|
||||
/** \brief 78, Timer Control Register 4 */
|
||||
#define CCU60_TCTR4 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR4*)0xF0002A78u)
|
||||
|
||||
/** \brief 84, Trap Control Register */
|
||||
#define CCU60_TRPCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_TRPCTR*)0xF0002A84u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ccu6_Cfg_Ccu61
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define CCU61_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_ACCEN0*)0xF0002BFCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define CCU61_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_CCU6_ACCEN1*)0xF0002BF8u)
|
||||
|
||||
/** \brief 30, Capture/Compare Register for Channel CC60 */
|
||||
#define CCU61_CC60R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC60R*)0xF0002B30u)
|
||||
|
||||
/** \brief 40, Capture/Compare Shadow Reg. for Channel CC60 */
|
||||
#define CCU61_CC60SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC60SR*)0xF0002B40u)
|
||||
|
||||
/** \brief 34, Capture/Compare Register for Channel CC61 */
|
||||
#define CCU61_CC61R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC61R*)0xF0002B34u)
|
||||
|
||||
/** \brief 44, Capture/Compare Shadow Reg. for Channel CC61 */
|
||||
#define CCU61_CC61SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC61SR*)0xF0002B44u)
|
||||
|
||||
/** \brief 38, Capture/Compare Register for Channel CC62 */
|
||||
#define CCU61_CC62R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC62R*)0xF0002B38u)
|
||||
|
||||
/** \brief 48, Capture/Compare Shadow Reg. for Channel CC62 */
|
||||
#define CCU61_CC62SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC62SR*)0xF0002B48u)
|
||||
|
||||
/** \brief 58, Compare Register for T13 */
|
||||
#define CCU61_CC63R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC63R*)0xF0002B58u)
|
||||
|
||||
/** \brief 5C, Compare Shadow Register for T13 */
|
||||
#define CCU61_CC63SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC63SR*)0xF0002B5Cu)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define CCU61_CLC /*lint --e(923)*/ (*(volatile Ifx_CCU6_CLC*)0xF0002B00u)
|
||||
|
||||
/** \brief 64, Compare State Modification Register */
|
||||
#define CCU61_CMPMODIF /*lint --e(923)*/ (*(volatile Ifx_CCU6_CMPMODIF*)0xF0002B64u)
|
||||
|
||||
/** \brief 60, Compare State Register */
|
||||
#define CCU61_CMPSTAT /*lint --e(923)*/ (*(volatile Ifx_CCU6_CMPSTAT*)0xF0002B60u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define CCU61_ID /*lint --e(923)*/ (*(volatile Ifx_CCU6_ID*)0xF0002B08u)
|
||||
|
||||
/** \brief B0, Interrupt Enable Register */
|
||||
#define CCU61_IEN /*lint --e(923)*/ (*(volatile Ifx_CCU6_IEN*)0xF0002BB0u)
|
||||
|
||||
/** \brief 98, Input Monitoring Register */
|
||||
#define CCU61_IMON /*lint --e(923)*/ (*(volatile Ifx_CCU6_IMON*)0xF0002B98u)
|
||||
|
||||
/** \brief AC, Interrupt Node Pointer Register */
|
||||
#define CCU61_INP /*lint --e(923)*/ (*(volatile Ifx_CCU6_INP*)0xF0002BACu)
|
||||
|
||||
/** \brief A0, Interrupt Status Register */
|
||||
#define CCU61_IS /*lint --e(923)*/ (*(volatile Ifx_CCU6_IS*)0xF0002BA0u)
|
||||
|
||||
/** \brief A8, Interrupt Status Reset Register */
|
||||
#define CCU61_ISR /*lint --e(923)*/ (*(volatile Ifx_CCU6_ISR*)0xF0002BA8u)
|
||||
|
||||
/** \brief A4, Interrupt Status Set Register */
|
||||
#define CCU61_ISS /*lint --e(923)*/ (*(volatile Ifx_CCU6_ISS*)0xF0002BA4u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define CCU61_KRST0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRST0*)0xF0002BF4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define CCU61_KRST1 /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRST1*)0xF0002BF0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define CCU61_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRSTCLR*)0xF0002BECu)
|
||||
|
||||
/** \brief 1C, Kernel State Control Sensitivity Register */
|
||||
#define CCU61_KSCSR /*lint --e(923)*/ (*(volatile Ifx_CCU6_KSCSR*)0xF0002B1Cu)
|
||||
|
||||
/** \brief 9C, Lost Indicator Register */
|
||||
#define CCU61_LI /*lint --e(923)*/ (*(volatile Ifx_CCU6_LI*)0xF0002B9Cu)
|
||||
|
||||
/** \brief 4, Module Configuration Register */
|
||||
#define CCU61_MCFG /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCFG*)0xF0002B04u)
|
||||
|
||||
/** \brief 94, Multi-Channel Mode Control Register */
|
||||
#define CCU61_MCMCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMCTR*)0xF0002B94u)
|
||||
|
||||
/** \brief 90, Multi-Channel Mode Output Register */
|
||||
#define CCU61_MCMOUT /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMOUT*)0xF0002B90u)
|
||||
|
||||
/** \brief 8C, Multi-Channel Mode Output Shadow Register */
|
||||
#define CCU61_MCMOUTS /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMOUTS*)0xF0002B8Cu)
|
||||
|
||||
/** \brief 80, Modulation Control Register */
|
||||
#define CCU61_MODCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_MODCTR*)0xF0002B80u)
|
||||
|
||||
/** \brief E8, OCDS Control and Status Register */
|
||||
#define CCU61_OCS /*lint --e(923)*/ (*(volatile Ifx_CCU6_OCS*)0xF0002BE8u)
|
||||
|
||||
/** \brief 10, Port Input Select Register 0 */
|
||||
#define CCU61_PISEL0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_PISEL0*)0xF0002B10u)
|
||||
|
||||
/** \brief 14, Port Input Select Register 2 */
|
||||
#define CCU61_PISEL2 /*lint --e(923)*/ (*(volatile Ifx_CCU6_PISEL2*)0xF0002B14u)
|
||||
|
||||
/** \brief 88, Passive State Level Register */
|
||||
#define CCU61_PSLR /*lint --e(923)*/ (*(volatile Ifx_CCU6_PSLR*)0xF0002B88u)
|
||||
|
||||
/** \brief 20, Timer T12 Counter Register */
|
||||
#define CCU61_T12 /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12*)0xF0002B20u)
|
||||
|
||||
/** \brief 28, Dead-Time Control Register for Timer12 */
|
||||
#define CCU61_T12DTC /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12DTC*)0xF0002B28u)
|
||||
|
||||
/** \brief 68, T12 Mode Select Register */
|
||||
#define CCU61_T12MSEL /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12MSEL*)0xF0002B68u)
|
||||
|
||||
/** \brief 24, Timer 12 Period Register */
|
||||
#define CCU61_T12PR /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12PR*)0xF0002B24u)
|
||||
|
||||
/** \brief 50, Timer T13 Counter Register */
|
||||
#define CCU61_T13 /*lint --e(923)*/ (*(volatile Ifx_CCU6_T13*)0xF0002B50u)
|
||||
|
||||
/** \brief 54, Timer 13 Period Register */
|
||||
#define CCU61_T13PR /*lint --e(923)*/ (*(volatile Ifx_CCU6_T13PR*)0xF0002B54u)
|
||||
|
||||
/** \brief 70, Timer Control Register 0 */
|
||||
#define CCU61_TCTR0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR0*)0xF0002B70u)
|
||||
|
||||
/** \brief 74, Timer Control Register 2 */
|
||||
#define CCU61_TCTR2 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR2*)0xF0002B74u)
|
||||
|
||||
/** \brief 78, Timer Control Register 4 */
|
||||
#define CCU61_TCTR4 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR4*)0xF0002B78u)
|
||||
|
||||
/** \brief 84, Trap Control Register */
|
||||
#define CCU61_TRPCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_TRPCTR*)0xF0002B84u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXCCU6_REG_H */
|
||||
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@@ -1,435 +0,0 @@
|
||||
/**
|
||||
* \file IfxDsadc_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Dsadc_Cfg Dsadc address
|
||||
* \ingroup IfxLld_Dsadc
|
||||
*
|
||||
* \defgroup IfxLld_Dsadc_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Dsadc_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Dsadc_Cfg_Dsadc 2-DSADC
|
||||
* \ingroup IfxLld_Dsadc_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXDSADC_REG_H
|
||||
#define IFXDSADC_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxDsadc_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Dsadc_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief DSADC object */
|
||||
#define MODULE_DSADC /*lint --e(923)*/ (*(Ifx_DSADC*)0xF0024000u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Dsadc_Cfg_Dsadc
|
||||
* \{ */
|
||||
|
||||
/** \brief 3C, Access Enable Register 0 */
|
||||
#define DSADC_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_DSADC_ACCEN0*)0xF002403Cu)
|
||||
|
||||
/** \brief 90, Access Protection Register */
|
||||
#define DSADC_ACCPROT /*lint --e(923)*/ (*(volatile Ifx_DSADC_ACCPROT*)0xF0024090u)
|
||||
|
||||
/** \brief A0, Carrier Generator Configuration Register */
|
||||
#define DSADC_CGCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CGCFG*)0xF00240A0u)
|
||||
|
||||
/** \brief 128, Boundary Select Register */
|
||||
#define DSADC_CH0_BOUNDSEL /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_BOUNDSEL*)0xF0024128u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_BOUNDSEL.
|
||||
* To use register names with standard convension, please use DSADC_CH0_BOUNDSEL.
|
||||
*/
|
||||
#define DSADC_BOUNDSEL0 (DSADC_CH0_BOUNDSEL)
|
||||
|
||||
/** \brief 1A0, Carrier Generator Synchronization Register */
|
||||
#define DSADC_CH0_CGSYNC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_CGSYNC*)0xF00241A0u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_CGSYNC.
|
||||
* To use register names with standard convension, please use DSADC_CH0_CGSYNC.
|
||||
*/
|
||||
#define DSADC_CGSYNC0 (DSADC_CH0_CGSYNC)
|
||||
|
||||
/** \brief 108, Demodulator Input Configuration Register */
|
||||
#define DSADC_CH0_DICFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_DICFG*)0xF0024108u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_DICFG.
|
||||
* To use register names with standard convension, please use DSADC_CH0_DICFG.
|
||||
*/
|
||||
#define DSADC_DICFG0 (DSADC_CH0_DICFG)
|
||||
|
||||
/** \brief 118, Filter Configuration Register, Auxiliary Filter */
|
||||
#define DSADC_CH0_FCFGA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGA*)0xF0024118u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_FCFGA.
|
||||
* To use register names with standard convension, please use DSADC_CH0_FCFGA.
|
||||
*/
|
||||
#define DSADC_FCFGA0 (DSADC_CH0_FCFGA)
|
||||
|
||||
/** \brief 114, Filter Configuration Register, Main CIC Filter */
|
||||
#define DSADC_CH0_FCFGC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGC*)0xF0024114u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_FCFGC.
|
||||
* To use register names with standard convension, please use DSADC_CH0_FCFGC.
|
||||
*/
|
||||
#define DSADC_FCFGC0 (DSADC_CH0_FCFGC)
|
||||
|
||||
/** \brief 110, Filter Configuration Register, Main Filter Chain */
|
||||
#define DSADC_CH0_FCFGM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGM*)0xF0024110u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_FCFGM.
|
||||
* To use register names with standard convension, please use DSADC_CH0_FCFGM.
|
||||
*/
|
||||
#define DSADC_FCFGM0 (DSADC_CH0_FCFGM)
|
||||
|
||||
/** \brief 1D0, Initial Channel Config. Reg. 0 */
|
||||
#define DSADC_CH0_ICCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_ICCFG*)0xF00241D0u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_ICCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH0_ICCFG.
|
||||
*/
|
||||
#define DSADC_ICCFG0 (DSADC_CH0_ICCFG)
|
||||
|
||||
/** \brief 120, Integration Window Control Register */
|
||||
#define DSADC_CH0_IWCTR /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_IWCTR*)0xF0024120u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_IWCTR.
|
||||
* To use register names with standard convension, please use DSADC_CH0_IWCTR.
|
||||
*/
|
||||
#define DSADC_IWCTR0 (DSADC_CH0_IWCTR)
|
||||
|
||||
/** \brief 100, Modulator Configuration Register */
|
||||
#define DSADC_CH0_MODCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_MODCFG*)0xF0024100u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_MODCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH0_MODCFG.
|
||||
*/
|
||||
#define DSADC_MODCFG0 (DSADC_CH0_MODCFG)
|
||||
|
||||
/** \brief 138, Offset Register Main Filter */
|
||||
#define DSADC_CH0_OFFM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_OFFM*)0xF0024138u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_OFFM.
|
||||
* To use register names with standard convension, please use DSADC_CH0_OFFM.
|
||||
*/
|
||||
#define DSADC_OFFM0 (DSADC_CH0_OFFM)
|
||||
|
||||
/** \brief 1A8, Rectification Configuration Register */
|
||||
#define DSADC_CH0_RECTCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RECTCFG*)0xF00241A8u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_RECTCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH0_RECTCFG.
|
||||
*/
|
||||
#define DSADC_RECTCFG0 (DSADC_CH0_RECTCFG)
|
||||
|
||||
/** \brief 140, Result Register Auxiliary Filter */
|
||||
#define DSADC_CH0_RESA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESA*)0xF0024140u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_RESA.
|
||||
* To use register names with standard convension, please use DSADC_CH0_RESA.
|
||||
*/
|
||||
#define DSADC_RESA0 (DSADC_CH0_RESA)
|
||||
|
||||
/** \brief 130, Result Register Main Filter */
|
||||
#define DSADC_CH0_RESM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESM*)0xF0024130u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_RESM.
|
||||
* To use register names with standard convension, please use DSADC_CH0_RESM.
|
||||
*/
|
||||
#define DSADC_RESM0 (DSADC_CH0_RESM)
|
||||
|
||||
/** \brief 150, Time-Stamp Register */
|
||||
#define DSADC_CH0_TSTMP /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_TSTMP*)0xF0024150u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_TSTMP.
|
||||
* To use register names with standard convension, please use DSADC_CH0_TSTMP.
|
||||
*/
|
||||
#define DSADC_TSTMP0 (DSADC_CH0_TSTMP)
|
||||
|
||||
/** \brief 328, Boundary Select Register */
|
||||
#define DSADC_CH2_BOUNDSEL /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_BOUNDSEL*)0xF0024328u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_BOUNDSEL.
|
||||
* To use register names with standard convension, please use DSADC_CH2_BOUNDSEL.
|
||||
*/
|
||||
#define DSADC_BOUNDSEL2 (DSADC_CH2_BOUNDSEL)
|
||||
|
||||
/** \brief 3A0, Carrier Generator Synchronization Register */
|
||||
#define DSADC_CH2_CGSYNC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_CGSYNC*)0xF00243A0u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_CGSYNC.
|
||||
* To use register names with standard convension, please use DSADC_CH2_CGSYNC.
|
||||
*/
|
||||
#define DSADC_CGSYNC2 (DSADC_CH2_CGSYNC)
|
||||
|
||||
/** \brief 308, Demodulator Input Configuration Register */
|
||||
#define DSADC_CH2_DICFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_DICFG*)0xF0024308u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_DICFG.
|
||||
* To use register names with standard convension, please use DSADC_CH2_DICFG.
|
||||
*/
|
||||
#define DSADC_DICFG2 (DSADC_CH2_DICFG)
|
||||
|
||||
/** \brief 318, Filter Configuration Register, Auxiliary Filter */
|
||||
#define DSADC_CH2_FCFGA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGA*)0xF0024318u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_FCFGA.
|
||||
* To use register names with standard convension, please use DSADC_CH2_FCFGA.
|
||||
*/
|
||||
#define DSADC_FCFGA2 (DSADC_CH2_FCFGA)
|
||||
|
||||
/** \brief 314, Filter Configuration Register, Main CIC Filter */
|
||||
#define DSADC_CH2_FCFGC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGC*)0xF0024314u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_FCFGC.
|
||||
* To use register names with standard convension, please use DSADC_CH2_FCFGC.
|
||||
*/
|
||||
#define DSADC_FCFGC2 (DSADC_CH2_FCFGC)
|
||||
|
||||
/** \brief 310, Filter Configuration Register, Main Filter Chain */
|
||||
#define DSADC_CH2_FCFGM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGM*)0xF0024310u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_FCFGM.
|
||||
* To use register names with standard convension, please use DSADC_CH2_FCFGM.
|
||||
*/
|
||||
#define DSADC_FCFGM2 (DSADC_CH2_FCFGM)
|
||||
|
||||
/** \brief 3D0, Initial Channel Config. Reg. 0 */
|
||||
#define DSADC_CH2_ICCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_ICCFG*)0xF00243D0u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_ICCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH2_ICCFG.
|
||||
*/
|
||||
#define DSADC_ICCFG2 (DSADC_CH2_ICCFG)
|
||||
|
||||
/** \brief 320, Integration Window Control Register */
|
||||
#define DSADC_CH2_IWCTR /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_IWCTR*)0xF0024320u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_IWCTR.
|
||||
* To use register names with standard convension, please use DSADC_CH2_IWCTR.
|
||||
*/
|
||||
#define DSADC_IWCTR2 (DSADC_CH2_IWCTR)
|
||||
|
||||
/** \brief 300, Modulator Configuration Register */
|
||||
#define DSADC_CH2_MODCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_MODCFG*)0xF0024300u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_MODCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH2_MODCFG.
|
||||
*/
|
||||
#define DSADC_MODCFG2 (DSADC_CH2_MODCFG)
|
||||
|
||||
/** \brief 338, Offset Register Main Filter */
|
||||
#define DSADC_CH2_OFFM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_OFFM*)0xF0024338u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_OFFM.
|
||||
* To use register names with standard convension, please use DSADC_CH2_OFFM.
|
||||
*/
|
||||
#define DSADC_OFFM2 (DSADC_CH2_OFFM)
|
||||
|
||||
/** \brief 3A8, Rectification Configuration Register */
|
||||
#define DSADC_CH2_RECTCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RECTCFG*)0xF00243A8u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_RECTCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH2_RECTCFG.
|
||||
*/
|
||||
#define DSADC_RECTCFG2 (DSADC_CH2_RECTCFG)
|
||||
|
||||
/** \brief 340, Result Register Auxiliary Filter */
|
||||
#define DSADC_CH2_RESA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESA*)0xF0024340u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_RESA.
|
||||
* To use register names with standard convension, please use DSADC_CH2_RESA.
|
||||
*/
|
||||
#define DSADC_RESA2 (DSADC_CH2_RESA)
|
||||
|
||||
/** \brief 330, Result Register Main Filter */
|
||||
#define DSADC_CH2_RESM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESM*)0xF0024330u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_RESM.
|
||||
* To use register names with standard convension, please use DSADC_CH2_RESM.
|
||||
*/
|
||||
#define DSADC_RESM2 (DSADC_CH2_RESM)
|
||||
|
||||
/** \brief 350, Time-Stamp Register */
|
||||
#define DSADC_CH2_TSTMP /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_TSTMP*)0xF0024350u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_TSTMP.
|
||||
* To use register names with standard convension, please use DSADC_CH2_TSTMP.
|
||||
*/
|
||||
#define DSADC_TSTMP2 (DSADC_CH2_TSTMP)
|
||||
|
||||
/** \brief 428, Boundary Select Register */
|
||||
#define DSADC_CH3_BOUNDSEL /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_BOUNDSEL*)0xF0024428u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_BOUNDSEL.
|
||||
* To use register names with standard convension, please use DSADC_CH3_BOUNDSEL.
|
||||
*/
|
||||
#define DSADC_BOUNDSEL3 (DSADC_CH3_BOUNDSEL)
|
||||
|
||||
/** \brief 4A0, Carrier Generator Synchronization Register */
|
||||
#define DSADC_CH3_CGSYNC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_CGSYNC*)0xF00244A0u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_CGSYNC.
|
||||
* To use register names with standard convension, please use DSADC_CH3_CGSYNC.
|
||||
*/
|
||||
#define DSADC_CGSYNC3 (DSADC_CH3_CGSYNC)
|
||||
|
||||
/** \brief 408, Demodulator Input Configuration Register */
|
||||
#define DSADC_CH3_DICFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_DICFG*)0xF0024408u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_DICFG.
|
||||
* To use register names with standard convension, please use DSADC_CH3_DICFG.
|
||||
*/
|
||||
#define DSADC_DICFG3 (DSADC_CH3_DICFG)
|
||||
|
||||
/** \brief 418, Filter Configuration Register, Auxiliary Filter */
|
||||
#define DSADC_CH3_FCFGA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGA*)0xF0024418u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_FCFGA.
|
||||
* To use register names with standard convension, please use DSADC_CH3_FCFGA.
|
||||
*/
|
||||
#define DSADC_FCFGA3 (DSADC_CH3_FCFGA)
|
||||
|
||||
/** \brief 414, Filter Configuration Register, Main CIC Filter */
|
||||
#define DSADC_CH3_FCFGC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGC*)0xF0024414u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_FCFGC.
|
||||
* To use register names with standard convension, please use DSADC_CH3_FCFGC.
|
||||
*/
|
||||
#define DSADC_FCFGC3 (DSADC_CH3_FCFGC)
|
||||
|
||||
/** \brief 410, Filter Configuration Register, Main Filter Chain */
|
||||
#define DSADC_CH3_FCFGM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGM*)0xF0024410u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_FCFGM.
|
||||
* To use register names with standard convension, please use DSADC_CH3_FCFGM.
|
||||
*/
|
||||
#define DSADC_FCFGM3 (DSADC_CH3_FCFGM)
|
||||
|
||||
/** \brief 4D0, Initial Channel Config. Reg. 0 */
|
||||
#define DSADC_CH3_ICCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_ICCFG*)0xF00244D0u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_ICCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH3_ICCFG.
|
||||
*/
|
||||
#define DSADC_ICCFG3 (DSADC_CH3_ICCFG)
|
||||
|
||||
/** \brief 420, Integration Window Control Register */
|
||||
#define DSADC_CH3_IWCTR /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_IWCTR*)0xF0024420u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_IWCTR.
|
||||
* To use register names with standard convension, please use DSADC_CH3_IWCTR.
|
||||
*/
|
||||
#define DSADC_IWCTR3 (DSADC_CH3_IWCTR)
|
||||
|
||||
/** \brief 400, Modulator Configuration Register */
|
||||
#define DSADC_CH3_MODCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_MODCFG*)0xF0024400u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_MODCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH3_MODCFG.
|
||||
*/
|
||||
#define DSADC_MODCFG3 (DSADC_CH3_MODCFG)
|
||||
|
||||
/** \brief 438, Offset Register Main Filter */
|
||||
#define DSADC_CH3_OFFM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_OFFM*)0xF0024438u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_OFFM.
|
||||
* To use register names with standard convension, please use DSADC_CH3_OFFM.
|
||||
*/
|
||||
#define DSADC_OFFM3 (DSADC_CH3_OFFM)
|
||||
|
||||
/** \brief 4A8, Rectification Configuration Register */
|
||||
#define DSADC_CH3_RECTCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RECTCFG*)0xF00244A8u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_RECTCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH3_RECTCFG.
|
||||
*/
|
||||
#define DSADC_RECTCFG3 (DSADC_CH3_RECTCFG)
|
||||
|
||||
/** \brief 440, Result Register Auxiliary Filter */
|
||||
#define DSADC_CH3_RESA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESA*)0xF0024440u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_RESA.
|
||||
* To use register names with standard convension, please use DSADC_CH3_RESA.
|
||||
*/
|
||||
#define DSADC_RESA3 (DSADC_CH3_RESA)
|
||||
|
||||
/** \brief 430, Result Register Main Filter */
|
||||
#define DSADC_CH3_RESM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESM*)0xF0024430u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_RESM.
|
||||
* To use register names with standard convension, please use DSADC_CH3_RESM.
|
||||
*/
|
||||
#define DSADC_RESM3 (DSADC_CH3_RESM)
|
||||
|
||||
/** \brief 450, Time-Stamp Register */
|
||||
#define DSADC_CH3_TSTMP /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_TSTMP*)0xF0024450u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_TSTMP.
|
||||
* To use register names with standard convension, please use DSADC_CH3_TSTMP.
|
||||
*/
|
||||
#define DSADC_TSTMP3 (DSADC_CH3_TSTMP)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define DSADC_CLC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CLC*)0xF0024000u)
|
||||
|
||||
/** \brief E0, Event Flag Register */
|
||||
#define DSADC_EVFLAG /*lint --e(923)*/ (*(volatile Ifx_DSADC_EVFLAG*)0xF00240E0u)
|
||||
|
||||
/** \brief E4, Event Flag Clear Register */
|
||||
#define DSADC_EVFLAGCLR /*lint --e(923)*/ (*(volatile Ifx_DSADC_EVFLAGCLR*)0xF00240E4u)
|
||||
|
||||
/** \brief 80, Global Configuration Register */
|
||||
#define DSADC_GLOBCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_GLOBCFG*)0xF0024080u)
|
||||
|
||||
/** \brief 88, Global Run Control Register */
|
||||
#define DSADC_GLOBRC /*lint --e(923)*/ (*(volatile Ifx_DSADC_GLOBRC*)0xF0024088u)
|
||||
|
||||
/** \brief B0, Common Mode Hold Voltage Register 0 */
|
||||
#define DSADC_GLOBVCMH0 /*lint --e(923)*/ (*(volatile Ifx_DSADC_GLOBVCMH0*)0xF00240B0u)
|
||||
|
||||
/** \brief B8, Common Mode Hold Voltage Register 2 */
|
||||
#define DSADC_GLOBVCMH2 /*lint --e(923)*/ (*(volatile Ifx_DSADC_GLOBVCMH2*)0xF00240B8u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define DSADC_ID /*lint --e(923)*/ (*(volatile Ifx_DSADC_ID*)0xF0024008u)
|
||||
|
||||
/** \brief D0, Initial Global Config. Register */
|
||||
#define DSADC_IGCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_IGCFG*)0xF00240D0u)
|
||||
|
||||
/** \brief 34, Kernel Reset Register 0 */
|
||||
#define DSADC_KRST0 /*lint --e(923)*/ (*(volatile Ifx_DSADC_KRST0*)0xF0024034u)
|
||||
|
||||
/** \brief 30, Kernel Reset Register 1 */
|
||||
#define DSADC_KRST1 /*lint --e(923)*/ (*(volatile Ifx_DSADC_KRST1*)0xF0024030u)
|
||||
|
||||
/** \brief 2C, Kernel Reset Status Clear Register */
|
||||
#define DSADC_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_DSADC_KRSTCLR*)0xF002402Cu)
|
||||
|
||||
/** \brief 28, OCDS Control and Status Register */
|
||||
#define DSADC_OCS /*lint --e(923)*/ (*(volatile Ifx_DSADC_OCS*)0xF0024028u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXDSADC_REG_H */
|
||||
@@ -1,761 +0,0 @@
|
||||
/**
|
||||
* \file IfxDsadc_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Dsadc Dsadc
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Dsadc_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Dsadc
|
||||
*
|
||||
* \defgroup IfxLld_Dsadc_union Union
|
||||
* \ingroup IfxLld_Dsadc
|
||||
*
|
||||
* \defgroup IfxLld_Dsadc_struct Struct
|
||||
* \ingroup IfxLld_Dsadc
|
||||
*
|
||||
*/
|
||||
#ifndef IFXDSADC_REGDEF_H
|
||||
#define IFXDSADC_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Dsadc_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_DSADC_ACCEN0_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_DSADC_ACCEN0_Bits;
|
||||
|
||||
/** \brief Access Protection Register */
|
||||
typedef struct _Ifx_DSADC_ACCPROT_Bits
|
||||
{
|
||||
unsigned int RG00:1; /**< \brief [0:0] Register Group 0, Channels 0, 2, 3 (rw) */
|
||||
unsigned int RG01:1; /**< \brief [1:1] Register Group 1, Channels 0, 2, 3 (rw) */
|
||||
unsigned int RG02:1; /**< \brief [2:2] Register Group 2, Channels 0, 2, 3 (rw) */
|
||||
unsigned int RG03:1; /**< \brief [3:3] Register Group 3, Channels 0, 2, 3 (rw) */
|
||||
unsigned int RG04:1; /**< \brief [4:4] Register Group 4, Channels 0, 2, 3 (rw) */
|
||||
unsigned int reserved_5:9; /**< \brief \internal Reserved */
|
||||
unsigned int RG10:1; /**< \brief [14:14] Register Group 0/1, General Control (rw) */
|
||||
unsigned int RG11:1; /**< \brief [15:15] Register Group 0/1, General Control (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_ACCPROT_Bits;
|
||||
|
||||
/** \brief Carrier Generator Configuration Register */
|
||||
typedef struct _Ifx_DSADC_CGCFG_Bits
|
||||
{
|
||||
unsigned int CGMOD:2; /**< \brief [1:0] Carrier Generator Operating Mode (rw) */
|
||||
unsigned int BREV:1; /**< \brief [2:2] Bit-Reverse PWM Generation (rw) */
|
||||
unsigned int SIGPOL:1; /**< \brief [3:3] Signal Polarity (rw) */
|
||||
unsigned int DIVCG:4; /**< \brief [7:4] Divider Factor for the PWM Pattern Signal Generator (rw) */
|
||||
unsigned int reserved_8:7; /**< \brief \internal Reserved */
|
||||
unsigned int RUN:1; /**< \brief [15:15] Run Indicator (rh) */
|
||||
unsigned int BITCOUNT:5; /**< \brief [20:16] Bit Counter (rh) */
|
||||
unsigned int reserved_21:3; /**< \brief \internal Reserved */
|
||||
unsigned int STEPCOUNT:4; /**< \brief [27:24] Step Counter (rh) */
|
||||
unsigned int STEPS:1; /**< \brief [28:28] Step Counter Sign (rh) */
|
||||
unsigned int STEPD:1; /**< \brief [29:29] Step Counter Direction (rh) */
|
||||
unsigned int SGNCG:1; /**< \brief [30:30] Sign Signal from Carrier Generator (rh) */
|
||||
unsigned int reserved_31:1; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_CGCFG_Bits;
|
||||
|
||||
/** \brief Boundary Select Register */
|
||||
typedef struct _Ifx_DSADC_CH_BOUNDSEL_Bits
|
||||
{
|
||||
unsigned int BOUNDARYL:16; /**< \brief [15:0] Lower Boundary Value for Limit Checking (rw) */
|
||||
unsigned int BOUNDARYU:16; /**< \brief [31:16] Upper Boundary Value for Limit Checking (rw) */
|
||||
} Ifx_DSADC_CH_BOUNDSEL_Bits;
|
||||
|
||||
/** \brief Carrier Generator Synchronization Register */
|
||||
typedef struct _Ifx_DSADC_CH_CGSYNC_Bits
|
||||
{
|
||||
unsigned int SDCOUNT:8; /**< \brief [7:0] Sign Delay Counter (rh) */
|
||||
unsigned int SDCAP:8; /**< \brief [15:8] Sign Delay Capture Value (rh) */
|
||||
unsigned int SDPOS:8; /**< \brief [23:16] Sign Delay Value for Positive Halfwave (rw) */
|
||||
unsigned int SDNEG:8; /**< \brief [31:24] Sign Delay Value for Negative Halfwave (rw) */
|
||||
} Ifx_DSADC_CH_CGSYNC_Bits;
|
||||
|
||||
/** \brief Demodulator Input Configuration Register */
|
||||
typedef struct _Ifx_DSADC_CH_DICFG_Bits
|
||||
{
|
||||
unsigned int DSRC:4; /**< \brief [3:0] Input Data Source Select (rw) */
|
||||
unsigned int reserved_4:3; /**< \brief \internal Reserved */
|
||||
unsigned int DSWC:1; /**< \brief [7:7] Write Control for Data Selection (w) */
|
||||
unsigned int ITRMODE:2; /**< \brief [9:8] Integrator Trigger Mode (rw) */
|
||||
unsigned int TSTRMODE:2; /**< \brief [11:10] Timestamp Trigger Mode (rw) */
|
||||
unsigned int TRSEL:3; /**< \brief [14:12] Trigger Select (rw) */
|
||||
unsigned int TRWC:1; /**< \brief [15:15] Write Control for Trigger Parameters (w) */
|
||||
unsigned int CSRC:4; /**< \brief [19:16] Sample Clock Source Select (rw) */
|
||||
unsigned int STROBE:4; /**< \brief [23:20] Data Strobe Generation Mode (rw) */
|
||||
unsigned int reserved_24:7; /**< \brief \internal Reserved */
|
||||
unsigned int SCWC:1; /**< \brief [31:31] Write Control for Strobe/Clock Selection (w) */
|
||||
} Ifx_DSADC_CH_DICFG_Bits;
|
||||
|
||||
/** \brief Filter Configuration Register, Auxiliary Filter */
|
||||
typedef struct _Ifx_DSADC_CH_FCFGA_Bits
|
||||
{
|
||||
unsigned int CFADF:8; /**< \brief [7:0] CIC Filter (Auxiliary) Decimation Factor (rw) */
|
||||
unsigned int CFAC:2; /**< \brief [9:8] CIC Filter (Auxiliary) Configuration (rw) */
|
||||
unsigned int SRGA:2; /**< \brief [11:10] Service Request Generation Auxiliary Filter (rw) */
|
||||
unsigned int ESEL:2; /**< \brief [13:12] Event Select (rw) */
|
||||
unsigned int EGT:1; /**< \brief [14:14] Event Gating (rw) */
|
||||
unsigned int reserved_15:1; /**< \brief \internal Reserved */
|
||||
unsigned int AFSC:2; /**< \brief [17:16] Auxiliary Filter Shift Control (rw) */
|
||||
unsigned int reserved_18:6; /**< \brief \internal Reserved */
|
||||
unsigned int CFADCNT:8; /**< \brief [31:24] CIC Filter (Auxiliary) Decimation Counter (rh) */
|
||||
} Ifx_DSADC_CH_FCFGA_Bits;
|
||||
|
||||
/** \brief Filter Configuration Register, Main CIC Filter */
|
||||
typedef struct _Ifx_DSADC_CH_FCFGC_Bits
|
||||
{
|
||||
unsigned int CFMDF:8; /**< \brief [7:0] CIC Filter (Main Chain) Decimation Factor (rw) */
|
||||
unsigned int CFMC:2; /**< \brief [9:8] CIC Filter (Main Chain) Configuration (rw) */
|
||||
unsigned int CFEN:1; /**< \brief [10:10] CIC Filter Enable (rw) */
|
||||
unsigned int reserved_11:1; /**< \brief \internal Reserved */
|
||||
unsigned int MFSC:2; /**< \brief [13:12] Main Filter Shift Control (rw) */
|
||||
unsigned int SRGM:2; /**< \brief [15:14] Service Request Generation Main Chain (rw) */
|
||||
unsigned int CFMSV:8; /**< \brief [23:16] CIC Filter (Main Chain) Start Value (rw) */
|
||||
unsigned int CFMDCNT:8; /**< \brief [31:24] CIC Filter (Main Chain) Decimation Counter (rh) */
|
||||
} Ifx_DSADC_CH_FCFGC_Bits;
|
||||
|
||||
/** \brief Filter Configuration Register, Main Filter Chain */
|
||||
typedef struct _Ifx_DSADC_CH_FCFGM_Bits
|
||||
{
|
||||
unsigned int FIR0EN:1; /**< \brief [0:0] FIR Filter 0 Enable (rw) */
|
||||
unsigned int FIR1EN:1; /**< \brief [1:1] FIR Filter 1 Enable (rw) */
|
||||
unsigned int OCEN:1; /**< \brief [2:2] Offset Compensation Filter Enable (rw) */
|
||||
unsigned int DSH:2; /**< \brief [4:3] Data Shift Control (rw) */
|
||||
unsigned int FSH:1; /**< \brief [5:5] FIR Shift Control (rw) */
|
||||
unsigned int reserved_6:26; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_CH_FCFGM_Bits;
|
||||
|
||||
/** \brief Initial Channel Config. Reg. 0 */
|
||||
typedef struct _Ifx_DSADC_CH_ICCFG_Bits
|
||||
{
|
||||
unsigned int DI0:1; /**< \brief [0:0] Dithering Function Enable (rw) */
|
||||
unsigned int DI1:1; /**< \brief [1:1] Dithering Function Enable (rw) */
|
||||
unsigned int reserved_2:2; /**< \brief \internal Reserved */
|
||||
unsigned int IREN:1; /**< \brief [4:4] Integrator Reset Enable (rw) */
|
||||
unsigned int reserved_5:3; /**< \brief \internal Reserved */
|
||||
unsigned int TWINSP:6; /**< \brief [13:8] Setup Parameters for this Twin Modulator (rw) */
|
||||
unsigned int reserved_14:17; /**< \brief \internal Reserved */
|
||||
unsigned int WREN:1; /**< \brief [31:31] Write Enable (rw) */
|
||||
} Ifx_DSADC_CH_ICCFG_Bits;
|
||||
|
||||
/** \brief Integration Window Control Register */
|
||||
typedef struct _Ifx_DSADC_CH_IWCTR_Bits
|
||||
{
|
||||
unsigned int NVALCNT:6; /**< \brief [5:0] Number of Values Counted (rh) */
|
||||
unsigned int reserved_6:1; /**< \brief \internal Reserved */
|
||||
unsigned int INTEN:1; /**< \brief [7:7] Integration Enable (rh) */
|
||||
unsigned int REPCNT:4; /**< \brief [11:8] Integration Cycle Counter (rh) */
|
||||
unsigned int REPVAL:4; /**< \brief [15:12] Number of Integration Cycles (rw) */
|
||||
unsigned int NVALDIS:6; /**< \brief [21:16] Number of Values Discarded (rw) */
|
||||
unsigned int reserved_22:1; /**< \brief \internal Reserved */
|
||||
unsigned int IWS:1; /**< \brief [23:23] Integration Window Size (rw) */
|
||||
unsigned int NVALINT:6; /**< \brief [29:24] Number of Values Integrated (rw) */
|
||||
unsigned int reserved_30:2; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_CH_IWCTR_Bits;
|
||||
|
||||
/** \brief Modulator Configuration Register */
|
||||
typedef struct _Ifx_DSADC_CH_MODCFG_Bits
|
||||
{
|
||||
unsigned int INCFGP:2; /**< \brief [1:0] Configuration of Positive Input Line (rw) */
|
||||
unsigned int INCFGN:2; /**< \brief [3:2] Configuration of Negative Input Line (rw) */
|
||||
unsigned int GAINSEL:4; /**< \brief [7:4] Gain Select of Analog Input Path (rw) */
|
||||
unsigned int INSEL:2; /**< \brief [9:8] Input Pin Selection (rw) */
|
||||
unsigned int INMUX:2; /**< \brief [11:10] Input Multiplexer Setting (rh) */
|
||||
unsigned int INMODE:2; /**< \brief [13:12] Input Multiplexer Control Mode (rw) */
|
||||
unsigned int INMAC:1; /**< \brief [14:14] Input Multiplexer Action Control (rw) */
|
||||
unsigned int INCWC:1; /**< \brief [15:15] Write Control for Input Parameters (w) */
|
||||
unsigned int DIVM:4; /**< \brief [19:16] Divider Factor for Modulator Clock (rw) */
|
||||
unsigned int reserved_20:3; /**< \brief \internal Reserved */
|
||||
unsigned int DWC:1; /**< \brief [23:23] Write Control for Divider Factor (w) */
|
||||
unsigned int CMVS:2; /**< \brief [25:24] Common Mode Voltage Selection (rw) */
|
||||
unsigned int MCFG:2; /**< \brief [27:26] Modulator Configuration (rw) */
|
||||
unsigned int GCEN:1; /**< \brief [28:28] Gain Calibration Enable (rw) */
|
||||
unsigned int APC:1; /**< \brief [29:29] Automatic Power Control (rw) */
|
||||
unsigned int reserved_30:1; /**< \brief \internal Reserved */
|
||||
unsigned int MWC:1; /**< \brief [31:31] Write Control for Mode Selection (w) */
|
||||
} Ifx_DSADC_CH_MODCFG_Bits;
|
||||
|
||||
/** \brief Offset Register Main Filter */
|
||||
typedef struct _Ifx_DSADC_CH_OFFM_Bits
|
||||
{
|
||||
unsigned int OFFSET:16; /**< \brief [15:0] Offset Value (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_CH_OFFM_Bits;
|
||||
|
||||
/** \brief Rectification Configuration Register */
|
||||
typedef struct _Ifx_DSADC_CH_RECTCFG_Bits
|
||||
{
|
||||
unsigned int RFEN:1; /**< \brief [0:0] Rectification Enable (rw) */
|
||||
unsigned int reserved_1:3; /**< \brief \internal Reserved */
|
||||
unsigned int SSRC:2; /**< \brief [5:4] Sign Source (rw) */
|
||||
unsigned int reserved_6:9; /**< \brief \internal Reserved */
|
||||
unsigned int SDCVAL:1; /**< \brief [15:15] Sign Delay Capture Valid Flag (rh) */
|
||||
unsigned int reserved_16:14; /**< \brief \internal Reserved */
|
||||
unsigned int SGNCS:1; /**< \brief [30:30] Selected Carrier Sign Signal (rh) */
|
||||
unsigned int SGND:1; /**< \brief [31:31] Sign Signal Delayed (rh) */
|
||||
} Ifx_DSADC_CH_RECTCFG_Bits;
|
||||
|
||||
/** \brief Result Register Auxiliary Filter */
|
||||
typedef struct _Ifx_DSADC_CH_RESA_Bits
|
||||
{
|
||||
unsigned int RESULT:16; /**< \brief [15:0] Result of most recent conversion (rh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_CH_RESA_Bits;
|
||||
|
||||
/** \brief Result Register Main Filter */
|
||||
typedef struct _Ifx_DSADC_CH_RESM_Bits
|
||||
{
|
||||
unsigned int RESULT:16; /**< \brief [15:0] Result of most recent conversion (rh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_CH_RESM_Bits;
|
||||
|
||||
/** \brief Time-Stamp Register */
|
||||
typedef struct _Ifx_DSADC_CH_TSTMP_Bits
|
||||
{
|
||||
unsigned int RESULT:16; /**< \brief [15:0] Result of most recent conversion (rh) */
|
||||
unsigned int CFMDCNT:8; /**< \brief [23:16] CIC Filter (Main Chain) Decimation Counter (rh) */
|
||||
unsigned int NVALCNT:6; /**< \brief [29:24] Number of Values Counted (rh) */
|
||||
unsigned int TSVAL:1; /**< \brief [30:30] Timestamp Valid (rh) */
|
||||
unsigned int TSSR:1; /**< \brief [31:31] Timestamp Service Request (rw) */
|
||||
} Ifx_DSADC_CH_TSTMP_Bits;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef struct _Ifx_DSADC_CLC_Bits
|
||||
{
|
||||
unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (r) */
|
||||
unsigned int reserved_2:1; /**< \brief \internal Reserved */
|
||||
unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_CLC_Bits;
|
||||
|
||||
/** \brief Event Flag Register */
|
||||
typedef struct _Ifx_DSADC_EVFLAG_Bits
|
||||
{
|
||||
unsigned int RESEV0:1; /**< \brief [0:0] Result Event (rwh) */
|
||||
unsigned int reserved_1:1; /**< \brief \internal Reserved */
|
||||
unsigned int RESEV2:1; /**< \brief [2:2] Result Event (rwh) */
|
||||
unsigned int RESEV3:1; /**< \brief [3:3] Result Event (rwh) */
|
||||
unsigned int reserved_4:12; /**< \brief \internal Reserved */
|
||||
unsigned int ALEV0:1; /**< \brief [16:16] Alarm Event (rwh) */
|
||||
unsigned int reserved_17:1; /**< \brief \internal Reserved */
|
||||
unsigned int ALEV2:1; /**< \brief [18:18] Alarm Event (rwh) */
|
||||
unsigned int ALEV3:1; /**< \brief [19:19] Alarm Event (rwh) */
|
||||
unsigned int reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_EVFLAG_Bits;
|
||||
|
||||
/** \brief Event Flag Clear Register */
|
||||
typedef struct _Ifx_DSADC_EVFLAGCLR_Bits
|
||||
{
|
||||
unsigned int RESEC0:1; /**< \brief [0:0] Result Event Clear (w) */
|
||||
unsigned int reserved_1:1; /**< \brief \internal Reserved */
|
||||
unsigned int RESEC2:1; /**< \brief [2:2] Result Event Clear (w) */
|
||||
unsigned int RESEC3:1; /**< \brief [3:3] Result Event Clear (w) */
|
||||
unsigned int reserved_4:12; /**< \brief \internal Reserved */
|
||||
unsigned int ALEC0:1; /**< \brief [16:16] Alarm Event Clear (w) */
|
||||
unsigned int reserved_17:1; /**< \brief \internal Reserved */
|
||||
unsigned int ALEC2:1; /**< \brief [18:18] Alarm Event Clear (w) */
|
||||
unsigned int ALEC3:1; /**< \brief [19:19] Alarm Event Clear (w) */
|
||||
unsigned int reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_EVFLAGCLR_Bits;
|
||||
|
||||
/** \brief Global Configuration Register */
|
||||
typedef struct _Ifx_DSADC_GLOBCFG_Bits
|
||||
{
|
||||
unsigned int MCSEL:3; /**< \brief [2:0] Modulator Clock Select (rw) */
|
||||
unsigned int reserved_3:8; /**< \brief \internal Reserved */
|
||||
unsigned int IRM0:1; /**< \brief [11:11] Internal Resistance Measurement Control (rw) */
|
||||
unsigned int reserved_12:4; /**< \brief \internal Reserved */
|
||||
unsigned int IBSEL:4; /**< \brief [19:16] Bias Current Select (rw) */
|
||||
unsigned int LOSUP:1; /**< \brief [20:20] Low Power Supply Voltage Select (rw) */
|
||||
unsigned int reserved_21:1; /**< \brief \internal Reserved */
|
||||
unsigned int ICT:1; /**< \brief [22:22] Internal Channel Test (rw) */
|
||||
unsigned int PSWC:1; /**< \brief [23:23] Write Control for Power Supply Parameters (w) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_GLOBCFG_Bits;
|
||||
|
||||
/** \brief Global Run Control Register */
|
||||
typedef struct _Ifx_DSADC_GLOBRC_Bits
|
||||
{
|
||||
unsigned int CH0RUN:1; /**< \brief [0:0] Channel 0 Run Control (rw) */
|
||||
unsigned int reserved_1:1; /**< \brief \internal Reserved */
|
||||
unsigned int CH2RUN:1; /**< \brief [2:2] Channel 2 Run Control (rw) */
|
||||
unsigned int CH3RUN:1; /**< \brief [3:3] Channel 3 Run Control (rw) */
|
||||
unsigned int reserved_4:12; /**< \brief \internal Reserved */
|
||||
unsigned int M0RUN:1; /**< \brief [16:16] Modulator 0 Run Control (rw) */
|
||||
unsigned int reserved_17:1; /**< \brief \internal Reserved */
|
||||
unsigned int M2RUN:1; /**< \brief [18:18] Modulator 2 Run Control (rw) */
|
||||
unsigned int M3RUN:1; /**< \brief [19:19] Modulator 3 Run Control (rw) */
|
||||
unsigned int reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_GLOBRC_Bits;
|
||||
|
||||
/** \brief Common Mode Hold Voltage Register 0 */
|
||||
typedef struct _Ifx_DSADC_GLOBVCMH0_Bits
|
||||
{
|
||||
unsigned int IN0PVC0:1; /**< \brief [0:0] Voltage Control of Positive Inputs 0-1 of CH0 (rw) */
|
||||
unsigned int IN0PVC1:1; /**< \brief [1:1] Voltage Control of Positive Inputs 0-1 of CH0 (rw) */
|
||||
unsigned int reserved_2:2; /**< \brief \internal Reserved */
|
||||
unsigned int IN0NVC0:1; /**< \brief [4:4] Voltage Control of Negative Inputs 0-1 of CH0 (rw) */
|
||||
unsigned int IN0NVC1:1; /**< \brief [5:5] Voltage Control of Negative Inputs 0-1 of CH0 (rw) */
|
||||
unsigned int reserved_6:10; /**< \brief \internal Reserved */
|
||||
unsigned int IN2PVC0:1; /**< \brief [16:16] Voltage Control of Positive Input 0 of CH2 (rw) */
|
||||
unsigned int reserved_17:3; /**< \brief \internal Reserved */
|
||||
unsigned int IN2NVC0:1; /**< \brief [20:20] Voltage Control of Negative Input 0 of CH2 (rw) */
|
||||
unsigned int reserved_21:3; /**< \brief \internal Reserved */
|
||||
unsigned int IN3PVC0:1; /**< \brief [24:24] Voltage Control of Positive Inputs 0-3 of CH3 (rw) */
|
||||
unsigned int IN3PVC1:1; /**< \brief [25:25] Voltage Control of Positive Inputs 0-3 of CH3 (rw) */
|
||||
unsigned int IN3PVC2:1; /**< \brief [26:26] Voltage Control of Positive Inputs 0-3 of CH3 (rw) */
|
||||
unsigned int IN3PVC3:1; /**< \brief [27:27] Voltage Control of Positive Inputs 0-3 of CH3 (rw) */
|
||||
unsigned int IN3NVC0:1; /**< \brief [28:28] Voltage Control of Negative Inputs 0-3 of CH3 (rw) */
|
||||
unsigned int IN3NVC1:1; /**< \brief [29:29] Voltage Control of Negative Inputs 0-3 of CH3 (rw) */
|
||||
unsigned int IN3NVC2:1; /**< \brief [30:30] Voltage Control of Negative Inputs 0-3 of CH3 (rw) */
|
||||
unsigned int IN3NVC3:1; /**< \brief [31:31] Voltage Control of Negative Inputs 0-3 of CH3 (rw) */
|
||||
} Ifx_DSADC_GLOBVCMH0_Bits;
|
||||
|
||||
/** \brief Common Mode Hold Voltage Register 2 */
|
||||
typedef struct _Ifx_DSADC_GLOBVCMH2_Bits
|
||||
{
|
||||
unsigned int reserved_0:29; /**< \brief \internal Reserved */
|
||||
unsigned int VHON:1; /**< \brief [29:29] Common Mode Hold Voltage On (rw) */
|
||||
unsigned int VCMHS:2; /**< \brief [31:30] Common Mode Hold Voltage Selection (rw) */
|
||||
} Ifx_DSADC_GLOBVCMH2_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_DSADC_ID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_DSADC_ID_Bits;
|
||||
|
||||
/** \brief Initial Global Config. Register */
|
||||
typedef struct _Ifx_DSADC_IGCFG_Bits
|
||||
{
|
||||
unsigned int DITRIM:3; /**< \brief [2:0] Trimming Value for the Dithering Function (rw) */
|
||||
unsigned int reserved_3:13; /**< \brief \internal Reserved */
|
||||
unsigned int GLOBSP:10; /**< \brief [25:16] Global Setup Parameters for the MultiADC (rw) */
|
||||
unsigned int reserved_26:5; /**< \brief \internal Reserved */
|
||||
unsigned int WREN:1; /**< \brief [31:31] Write Enable (rw) */
|
||||
} Ifx_DSADC_IGCFG_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef struct _Ifx_DSADC_KRST0_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_KRST0_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef struct _Ifx_DSADC_KRST1_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_KRST1_Bits;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef struct _Ifx_DSADC_KRSTCLR_Bits
|
||||
{
|
||||
unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_KRSTCLR_Bits;
|
||||
|
||||
/** \brief OCDS Control and Status Register */
|
||||
typedef struct _Ifx_DSADC_OCS_Bits
|
||||
{
|
||||
unsigned int reserved_0:24; /**< \brief \internal Reserved */
|
||||
unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
|
||||
unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
|
||||
unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
|
||||
unsigned int reserved_30:2; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_OCS_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Dsadc_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_ACCEN0;
|
||||
|
||||
/** \brief Access Protection Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_ACCPROT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_ACCPROT;
|
||||
|
||||
/** \brief Carrier Generator Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CGCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CGCFG;
|
||||
|
||||
/** \brief Boundary Select Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_BOUNDSEL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_BOUNDSEL;
|
||||
|
||||
/** \brief Carrier Generator Synchronization Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_CGSYNC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_CGSYNC;
|
||||
|
||||
/** \brief Demodulator Input Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_DICFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_DICFG;
|
||||
|
||||
/** \brief Filter Configuration Register, Auxiliary Filter */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_FCFGA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_FCFGA;
|
||||
|
||||
/** \brief Filter Configuration Register, Main CIC Filter */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_FCFGC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_FCFGC;
|
||||
|
||||
/** \brief Filter Configuration Register, Main Filter Chain */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_FCFGM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_FCFGM;
|
||||
|
||||
/** \brief Initial Channel Config. Reg. 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_ICCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_ICCFG;
|
||||
|
||||
/** \brief Integration Window Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_IWCTR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_IWCTR;
|
||||
|
||||
/** \brief Modulator Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_MODCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_MODCFG;
|
||||
|
||||
/** \brief Offset Register Main Filter */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_OFFM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_OFFM;
|
||||
|
||||
/** \brief Rectification Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_RECTCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_RECTCFG;
|
||||
|
||||
/** \brief Result Register Auxiliary Filter */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_RESA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_RESA;
|
||||
|
||||
/** \brief Result Register Main Filter */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_RESM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_RESM;
|
||||
|
||||
/** \brief Time-Stamp Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_TSTMP_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_TSTMP;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CLC;
|
||||
|
||||
/** \brief Event Flag Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_EVFLAG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_EVFLAG;
|
||||
|
||||
/** \brief Event Flag Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_EVFLAGCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_EVFLAGCLR;
|
||||
|
||||
/** \brief Global Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_GLOBCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_GLOBCFG;
|
||||
|
||||
/** \brief Global Run Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_GLOBRC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_GLOBRC;
|
||||
|
||||
/** \brief Common Mode Hold Voltage Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_GLOBVCMH0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_GLOBVCMH0;
|
||||
|
||||
/** \brief Common Mode Hold Voltage Register 2 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_GLOBVCMH2_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_GLOBVCMH2;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_ID;
|
||||
|
||||
/** \brief Initial Global Config. Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_IGCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_IGCFG;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_KRST0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_KRST0;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_KRST1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_KRST1;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_KRSTCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_KRSTCLR;
|
||||
|
||||
/** \brief OCDS Control and Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_OCS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_OCS;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Dsadc_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L1
|
||||
* \{ */
|
||||
|
||||
/** \brief Channel objects */
|
||||
typedef volatile struct _Ifx_DSADC_CH
|
||||
{
|
||||
Ifx_DSADC_CH_MODCFG MODCFG; /**< \brief 0, Modulator Configuration Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_DSADC_CH_DICFG DICFG; /**< \brief 8, Demodulator Input Configuration Register */
|
||||
unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
|
||||
Ifx_DSADC_CH_FCFGM FCFGM; /**< \brief 10, Filter Configuration Register, Main Filter Chain */
|
||||
Ifx_DSADC_CH_FCFGC FCFGC; /**< \brief 14, Filter Configuration Register, Main CIC Filter */
|
||||
Ifx_DSADC_CH_FCFGA FCFGA; /**< \brief 18, Filter Configuration Register, Auxiliary Filter */
|
||||
unsigned char reserved_1C[4]; /**< \brief 1C, \internal Reserved */
|
||||
Ifx_DSADC_CH_IWCTR IWCTR; /**< \brief 20, Integration Window Control Register */
|
||||
unsigned char reserved_24[4]; /**< \brief 24, \internal Reserved */
|
||||
Ifx_DSADC_CH_BOUNDSEL BOUNDSEL; /**< \brief 28, Boundary Select Register */
|
||||
unsigned char reserved_2C[4]; /**< \brief 2C, \internal Reserved */
|
||||
Ifx_DSADC_CH_RESM RESM; /**< \brief 30, Result Register Main Filter */
|
||||
unsigned char reserved_34[4]; /**< \brief 34, \internal Reserved */
|
||||
Ifx_DSADC_CH_OFFM OFFM; /**< \brief 38, Offset Register Main Filter */
|
||||
unsigned char reserved_3C[4]; /**< \brief 3C, \internal Reserved */
|
||||
Ifx_DSADC_CH_RESA RESA; /**< \brief 40, Result Register Auxiliary Filter */
|
||||
unsigned char reserved_44[12]; /**< \brief 44, \internal Reserved */
|
||||
Ifx_DSADC_CH_TSTMP TSTMP; /**< \brief 50, Time-Stamp Register */
|
||||
unsigned char reserved_54[76]; /**< \brief 54, \internal Reserved */
|
||||
Ifx_DSADC_CH_CGSYNC CGSYNC; /**< \brief A0, Carrier Generator Synchronization Register */
|
||||
unsigned char reserved_A4[4]; /**< \brief A4, \internal Reserved */
|
||||
Ifx_DSADC_CH_RECTCFG RECTCFG; /**< \brief A8, Rectification Configuration Register */
|
||||
unsigned char reserved_AC[36]; /**< \brief AC, \internal Reserved */
|
||||
Ifx_DSADC_CH_ICCFG ICCFG; /**< \brief D0, Initial Channel Config. Reg. 0 */
|
||||
unsigned char reserved_D4[44]; /**< \brief D4, \internal Reserved */
|
||||
} Ifx_DSADC_CH;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Dsadc_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief DSADC object */
|
||||
typedef volatile struct _Ifx_DSADC
|
||||
{
|
||||
Ifx_DSADC_CLC CLC; /**< \brief 0, Clock Control Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_DSADC_ID ID; /**< \brief 8, Module Identification Register */
|
||||
unsigned char reserved_C[28]; /**< \brief C, \internal Reserved */
|
||||
Ifx_DSADC_OCS OCS; /**< \brief 28, OCDS Control and Status Register */
|
||||
Ifx_DSADC_KRSTCLR KRSTCLR; /**< \brief 2C, Kernel Reset Status Clear Register */
|
||||
Ifx_DSADC_KRST1 KRST1; /**< \brief 30, Kernel Reset Register 1 */
|
||||
Ifx_DSADC_KRST0 KRST0; /**< \brief 34, Kernel Reset Register 0 */
|
||||
unsigned char reserved_38[4]; /**< \brief 38, \internal Reserved */
|
||||
Ifx_DSADC_ACCEN0 ACCEN0; /**< \brief 3C, Access Enable Register 0 */
|
||||
unsigned char reserved_40[64]; /**< \brief 40, \internal Reserved */
|
||||
Ifx_DSADC_GLOBCFG GLOBCFG; /**< \brief 80, Global Configuration Register */
|
||||
unsigned char reserved_84[4]; /**< \brief 84, \internal Reserved */
|
||||
Ifx_DSADC_GLOBRC GLOBRC; /**< \brief 88, Global Run Control Register */
|
||||
unsigned char reserved_8C[4]; /**< \brief 8C, \internal Reserved */
|
||||
Ifx_DSADC_ACCPROT ACCPROT; /**< \brief 90, Access Protection Register */
|
||||
unsigned char reserved_94[12]; /**< \brief 94, \internal Reserved */
|
||||
Ifx_DSADC_CGCFG CGCFG; /**< \brief A0, Carrier Generator Configuration Register */
|
||||
unsigned char reserved_A4[12]; /**< \brief A4, \internal Reserved */
|
||||
Ifx_DSADC_GLOBVCMH0 GLOBVCMH0; /**< \brief B0, Common Mode Hold Voltage Register 0 */
|
||||
unsigned char reserved_B4[4]; /**< \brief B4, \internal Reserved */
|
||||
Ifx_DSADC_GLOBVCMH2 GLOBVCMH2; /**< \brief B8, Common Mode Hold Voltage Register 2 */
|
||||
unsigned char reserved_BC[20]; /**< \brief BC, \internal Reserved */
|
||||
Ifx_DSADC_IGCFG IGCFG; /**< \brief D0, Initial Global Config. Register */
|
||||
unsigned char reserved_D4[12]; /**< \brief D4, \internal Reserved */
|
||||
Ifx_DSADC_EVFLAG EVFLAG; /**< \brief E0, Event Flag Register */
|
||||
Ifx_DSADC_EVFLAGCLR EVFLAGCLR; /**< \brief E4, Event Flag Clear Register */
|
||||
unsigned char reserved_E8[24]; /**< \brief E8, \internal Reserved */
|
||||
Ifx_DSADC_CH CH[4]; /**< \brief 100, Channel objects */
|
||||
unsigned char reserved_500[2816]; /**< \brief 500, \internal Reserved */
|
||||
} Ifx_DSADC;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXDSADC_REGDEF_H */
|
||||
@@ -1,621 +0,0 @@
|
||||
/**
|
||||
* \file IfxEbcu_bf.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC2XXED_TS_V1.0.R2
|
||||
* Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu_BitfieldsMask Bitfields mask and offset
|
||||
* \ingroup IfxLld_Ebcu
|
||||
*
|
||||
*/
|
||||
#ifndef IFXEBCU_BF_H
|
||||
#define IFXEBCU_BF_H 1
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ebcu_BitfieldsMask
|
||||
* \{ */
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN0 */
|
||||
#define IFX_EBCU_ACCEN0_EN0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN0 */
|
||||
#define IFX_EBCU_ACCEN0_EN0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN0 */
|
||||
#define IFX_EBCU_ACCEN0_EN0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN10 */
|
||||
#define IFX_EBCU_ACCEN0_EN10_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN10 */
|
||||
#define IFX_EBCU_ACCEN0_EN10_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN10 */
|
||||
#define IFX_EBCU_ACCEN0_EN10_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN11 */
|
||||
#define IFX_EBCU_ACCEN0_EN11_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN11 */
|
||||
#define IFX_EBCU_ACCEN0_EN11_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN11 */
|
||||
#define IFX_EBCU_ACCEN0_EN11_OFF (11u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN12 */
|
||||
#define IFX_EBCU_ACCEN0_EN12_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN12 */
|
||||
#define IFX_EBCU_ACCEN0_EN12_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN12 */
|
||||
#define IFX_EBCU_ACCEN0_EN12_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN13 */
|
||||
#define IFX_EBCU_ACCEN0_EN13_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN13 */
|
||||
#define IFX_EBCU_ACCEN0_EN13_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN13 */
|
||||
#define IFX_EBCU_ACCEN0_EN13_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN14 */
|
||||
#define IFX_EBCU_ACCEN0_EN14_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN14 */
|
||||
#define IFX_EBCU_ACCEN0_EN14_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN14 */
|
||||
#define IFX_EBCU_ACCEN0_EN14_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN15 */
|
||||
#define IFX_EBCU_ACCEN0_EN15_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN15 */
|
||||
#define IFX_EBCU_ACCEN0_EN15_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN15 */
|
||||
#define IFX_EBCU_ACCEN0_EN15_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN16 */
|
||||
#define IFX_EBCU_ACCEN0_EN16_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN16 */
|
||||
#define IFX_EBCU_ACCEN0_EN16_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN16 */
|
||||
#define IFX_EBCU_ACCEN0_EN16_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN17 */
|
||||
#define IFX_EBCU_ACCEN0_EN17_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN17 */
|
||||
#define IFX_EBCU_ACCEN0_EN17_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN17 */
|
||||
#define IFX_EBCU_ACCEN0_EN17_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN18 */
|
||||
#define IFX_EBCU_ACCEN0_EN18_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN18 */
|
||||
#define IFX_EBCU_ACCEN0_EN18_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN18 */
|
||||
#define IFX_EBCU_ACCEN0_EN18_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN19 */
|
||||
#define IFX_EBCU_ACCEN0_EN19_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN19 */
|
||||
#define IFX_EBCU_ACCEN0_EN19_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN19 */
|
||||
#define IFX_EBCU_ACCEN0_EN19_OFF (19u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN1 */
|
||||
#define IFX_EBCU_ACCEN0_EN1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN1 */
|
||||
#define IFX_EBCU_ACCEN0_EN1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN1 */
|
||||
#define IFX_EBCU_ACCEN0_EN1_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN20 */
|
||||
#define IFX_EBCU_ACCEN0_EN20_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN20 */
|
||||
#define IFX_EBCU_ACCEN0_EN20_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN20 */
|
||||
#define IFX_EBCU_ACCEN0_EN20_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN21 */
|
||||
#define IFX_EBCU_ACCEN0_EN21_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN21 */
|
||||
#define IFX_EBCU_ACCEN0_EN21_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN21 */
|
||||
#define IFX_EBCU_ACCEN0_EN21_OFF (21u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN22 */
|
||||
#define IFX_EBCU_ACCEN0_EN22_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN22 */
|
||||
#define IFX_EBCU_ACCEN0_EN22_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN22 */
|
||||
#define IFX_EBCU_ACCEN0_EN22_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN23 */
|
||||
#define IFX_EBCU_ACCEN0_EN23_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN23 */
|
||||
#define IFX_EBCU_ACCEN0_EN23_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN23 */
|
||||
#define IFX_EBCU_ACCEN0_EN23_OFF (23u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN24 */
|
||||
#define IFX_EBCU_ACCEN0_EN24_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN24 */
|
||||
#define IFX_EBCU_ACCEN0_EN24_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN24 */
|
||||
#define IFX_EBCU_ACCEN0_EN24_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN25 */
|
||||
#define IFX_EBCU_ACCEN0_EN25_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN25 */
|
||||
#define IFX_EBCU_ACCEN0_EN25_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN25 */
|
||||
#define IFX_EBCU_ACCEN0_EN25_OFF (25u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN26 */
|
||||
#define IFX_EBCU_ACCEN0_EN26_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN26 */
|
||||
#define IFX_EBCU_ACCEN0_EN26_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN26 */
|
||||
#define IFX_EBCU_ACCEN0_EN26_OFF (26u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN27 */
|
||||
#define IFX_EBCU_ACCEN0_EN27_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN27 */
|
||||
#define IFX_EBCU_ACCEN0_EN27_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN27 */
|
||||
#define IFX_EBCU_ACCEN0_EN27_OFF (27u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN28 */
|
||||
#define IFX_EBCU_ACCEN0_EN28_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN28 */
|
||||
#define IFX_EBCU_ACCEN0_EN28_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN28 */
|
||||
#define IFX_EBCU_ACCEN0_EN28_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN29 */
|
||||
#define IFX_EBCU_ACCEN0_EN29_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN29 */
|
||||
#define IFX_EBCU_ACCEN0_EN29_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN29 */
|
||||
#define IFX_EBCU_ACCEN0_EN29_OFF (29u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN2 */
|
||||
#define IFX_EBCU_ACCEN0_EN2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN2 */
|
||||
#define IFX_EBCU_ACCEN0_EN2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN2 */
|
||||
#define IFX_EBCU_ACCEN0_EN2_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN30 */
|
||||
#define IFX_EBCU_ACCEN0_EN30_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN30 */
|
||||
#define IFX_EBCU_ACCEN0_EN30_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN30 */
|
||||
#define IFX_EBCU_ACCEN0_EN30_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN31 */
|
||||
#define IFX_EBCU_ACCEN0_EN31_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN31 */
|
||||
#define IFX_EBCU_ACCEN0_EN31_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN31 */
|
||||
#define IFX_EBCU_ACCEN0_EN31_OFF (31u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN3 */
|
||||
#define IFX_EBCU_ACCEN0_EN3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN3 */
|
||||
#define IFX_EBCU_ACCEN0_EN3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN3 */
|
||||
#define IFX_EBCU_ACCEN0_EN3_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN4 */
|
||||
#define IFX_EBCU_ACCEN0_EN4_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN4 */
|
||||
#define IFX_EBCU_ACCEN0_EN4_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN4 */
|
||||
#define IFX_EBCU_ACCEN0_EN4_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN5 */
|
||||
#define IFX_EBCU_ACCEN0_EN5_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN5 */
|
||||
#define IFX_EBCU_ACCEN0_EN5_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN5 */
|
||||
#define IFX_EBCU_ACCEN0_EN5_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN6 */
|
||||
#define IFX_EBCU_ACCEN0_EN6_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN6 */
|
||||
#define IFX_EBCU_ACCEN0_EN6_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN6 */
|
||||
#define IFX_EBCU_ACCEN0_EN6_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN7 */
|
||||
#define IFX_EBCU_ACCEN0_EN7_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN7 */
|
||||
#define IFX_EBCU_ACCEN0_EN7_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN7 */
|
||||
#define IFX_EBCU_ACCEN0_EN7_OFF (7u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN8 */
|
||||
#define IFX_EBCU_ACCEN0_EN8_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN8 */
|
||||
#define IFX_EBCU_ACCEN0_EN8_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN8 */
|
||||
#define IFX_EBCU_ACCEN0_EN8_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN9 */
|
||||
#define IFX_EBCU_ACCEN0_EN9_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN9 */
|
||||
#define IFX_EBCU_ACCEN0_EN9_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN9 */
|
||||
#define IFX_EBCU_ACCEN0_EN9_OFF (9u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_CON_Bits.DBG */
|
||||
#define IFX_EBCU_CON_DBG_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_CON_Bits.DBG */
|
||||
#define IFX_EBCU_CON_DBG_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_CON_Bits.DBG */
|
||||
#define IFX_EBCU_CON_DBG_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_CON_Bits.SPC */
|
||||
#define IFX_EBCU_CON_SPC_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_CON_Bits.SPC */
|
||||
#define IFX_EBCU_CON_SPC_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_CON_Bits.SPC */
|
||||
#define IFX_EBCU_CON_SPC_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_CON_Bits.TOUT */
|
||||
#define IFX_EBCU_CON_TOUT_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_CON_Bits.TOUT */
|
||||
#define IFX_EBCU_CON_TOUT_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_CON_Bits.TOUT */
|
||||
#define IFX_EBCU_CON_TOUT_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_EADD_Bits.FPIADR */
|
||||
#define IFX_EBCU_EADD_FPIADR_LEN (32u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_EADD_Bits.FPIADR */
|
||||
#define IFX_EBCU_EADD_FPIADR_MSK (0xffffffffu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_EADD_Bits.FPIADR */
|
||||
#define IFX_EBCU_EADD_FPIADR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.ABT */
|
||||
#define IFX_EBCU_ECON_ABT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.ABT */
|
||||
#define IFX_EBCU_ECON_ABT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.ABT */
|
||||
#define IFX_EBCU_ECON_ABT_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.ACK */
|
||||
#define IFX_EBCU_ECON_ACK_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.ACK */
|
||||
#define IFX_EBCU_ECON_ACK_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.ACK */
|
||||
#define IFX_EBCU_ECON_ACK_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.ERRCNT */
|
||||
#define IFX_EBCU_ECON_ERRCNT_LEN (14u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.ERRCNT */
|
||||
#define IFX_EBCU_ECON_ERRCNT_MSK (0x3fffu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.ERRCNT */
|
||||
#define IFX_EBCU_ECON_ERRCNT_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.OPC */
|
||||
#define IFX_EBCU_ECON_OPC_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.OPC */
|
||||
#define IFX_EBCU_ECON_OPC_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.OPC */
|
||||
#define IFX_EBCU_ECON_OPC_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.RDN */
|
||||
#define IFX_EBCU_ECON_RDN_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.RDN */
|
||||
#define IFX_EBCU_ECON_RDN_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.RDN */
|
||||
#define IFX_EBCU_ECON_RDN_OFF (21u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.RDY */
|
||||
#define IFX_EBCU_ECON_RDY_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.RDY */
|
||||
#define IFX_EBCU_ECON_RDY_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.RDY */
|
||||
#define IFX_EBCU_ECON_RDY_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.SVM */
|
||||
#define IFX_EBCU_ECON_SVM_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.SVM */
|
||||
#define IFX_EBCU_ECON_SVM_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.SVM */
|
||||
#define IFX_EBCU_ECON_SVM_OFF (19u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.TAG */
|
||||
#define IFX_EBCU_ECON_TAG_LEN (6u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.TAG */
|
||||
#define IFX_EBCU_ECON_TAG_MSK (0x3fu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.TAG */
|
||||
#define IFX_EBCU_ECON_TAG_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.TOUT */
|
||||
#define IFX_EBCU_ECON_TOUT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.TOUT */
|
||||
#define IFX_EBCU_ECON_TOUT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.TOUT */
|
||||
#define IFX_EBCU_ECON_TOUT_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.WRN */
|
||||
#define IFX_EBCU_ECON_WRN_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.WRN */
|
||||
#define IFX_EBCU_ECON_WRN_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.WRN */
|
||||
#define IFX_EBCU_ECON_WRN_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_EDAT_Bits.FPIDAT */
|
||||
#define IFX_EBCU_EDAT_FPIDAT_LEN (32u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_EDAT_Bits.FPIDAT */
|
||||
#define IFX_EBCU_EDAT_FPIDAT_MSK (0xffffffffu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_EDAT_Bits.FPIDAT */
|
||||
#define IFX_EBCU_EDAT_FPIDAT_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ID_Bits.MOD_REV */
|
||||
#define IFX_EBCU_ID_MOD_REV_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ID_Bits.MOD_REV */
|
||||
#define IFX_EBCU_ID_MOD_REV_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ID_Bits.MOD_REV */
|
||||
#define IFX_EBCU_ID_MOD_REV_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ID_Bits.MODNUMBER */
|
||||
#define IFX_EBCU_ID_MODNUMBER_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ID_Bits.MODNUMBER */
|
||||
#define IFX_EBCU_ID_MODNUMBER_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ID_Bits.MODNUMBER */
|
||||
#define IFX_EBCU_ID_MODNUMBER_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER10 */
|
||||
#define IFX_EBCU_PRIOH_MASTER10_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER10 */
|
||||
#define IFX_EBCU_PRIOH_MASTER10_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER10 */
|
||||
#define IFX_EBCU_PRIOH_MASTER10_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER11 */
|
||||
#define IFX_EBCU_PRIOH_MASTER11_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER11 */
|
||||
#define IFX_EBCU_PRIOH_MASTER11_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER11 */
|
||||
#define IFX_EBCU_PRIOH_MASTER11_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER12 */
|
||||
#define IFX_EBCU_PRIOH_MASTER12_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER12 */
|
||||
#define IFX_EBCU_PRIOH_MASTER12_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER12 */
|
||||
#define IFX_EBCU_PRIOH_MASTER12_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER13 */
|
||||
#define IFX_EBCU_PRIOH_MASTER13_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER13 */
|
||||
#define IFX_EBCU_PRIOH_MASTER13_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER13 */
|
||||
#define IFX_EBCU_PRIOH_MASTER13_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER14 */
|
||||
#define IFX_EBCU_PRIOH_MASTER14_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER14 */
|
||||
#define IFX_EBCU_PRIOH_MASTER14_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER14 */
|
||||
#define IFX_EBCU_PRIOH_MASTER14_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER15 */
|
||||
#define IFX_EBCU_PRIOH_MASTER15_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER15 */
|
||||
#define IFX_EBCU_PRIOH_MASTER15_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER15 */
|
||||
#define IFX_EBCU_PRIOH_MASTER15_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER8 */
|
||||
#define IFX_EBCU_PRIOH_MASTER8_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER8 */
|
||||
#define IFX_EBCU_PRIOH_MASTER8_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER8 */
|
||||
#define IFX_EBCU_PRIOH_MASTER8_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER9 */
|
||||
#define IFX_EBCU_PRIOH_MASTER9_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER9 */
|
||||
#define IFX_EBCU_PRIOH_MASTER9_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER9 */
|
||||
#define IFX_EBCU_PRIOH_MASTER9_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER0 */
|
||||
#define IFX_EBCU_PRIOL_MASTER0_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER0 */
|
||||
#define IFX_EBCU_PRIOL_MASTER0_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER0 */
|
||||
#define IFX_EBCU_PRIOL_MASTER0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER1 */
|
||||
#define IFX_EBCU_PRIOL_MASTER1_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER1 */
|
||||
#define IFX_EBCU_PRIOL_MASTER1_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER1 */
|
||||
#define IFX_EBCU_PRIOL_MASTER1_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER2 */
|
||||
#define IFX_EBCU_PRIOL_MASTER2_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER2 */
|
||||
#define IFX_EBCU_PRIOL_MASTER2_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER2 */
|
||||
#define IFX_EBCU_PRIOL_MASTER2_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER3 */
|
||||
#define IFX_EBCU_PRIOL_MASTER3_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER3 */
|
||||
#define IFX_EBCU_PRIOL_MASTER3_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER3 */
|
||||
#define IFX_EBCU_PRIOL_MASTER3_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER4 */
|
||||
#define IFX_EBCU_PRIOL_MASTER4_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER4 */
|
||||
#define IFX_EBCU_PRIOL_MASTER4_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER4 */
|
||||
#define IFX_EBCU_PRIOL_MASTER4_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER5 */
|
||||
#define IFX_EBCU_PRIOL_MASTER5_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER5 */
|
||||
#define IFX_EBCU_PRIOL_MASTER5_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER5 */
|
||||
#define IFX_EBCU_PRIOL_MASTER5_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER6 */
|
||||
#define IFX_EBCU_PRIOL_MASTER6_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER6 */
|
||||
#define IFX_EBCU_PRIOL_MASTER6_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER6 */
|
||||
#define IFX_EBCU_PRIOL_MASTER6_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER7 */
|
||||
#define IFX_EBCU_PRIOL_MASTER7_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER7 */
|
||||
#define IFX_EBCU_PRIOL_MASTER7_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER7 */
|
||||
#define IFX_EBCU_PRIOL_MASTER7_OFF (28u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXEBCU_BF_H */
|
||||
@@ -1,123 +0,0 @@
|
||||
/**
|
||||
* \file IfxEbcu_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC2XXED_TS_V1.0.R2
|
||||
* Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu_Cfg Ebcu address
|
||||
* \ingroup IfxLld_Ebcu
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Ebcu_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu_Cfg_Ebcu0 2-EBCU0
|
||||
* \ingroup IfxLld_Ebcu_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXEBCU_REG_H
|
||||
#define IFXEBCU_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxEbcu_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ebcu_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief EBCU object */
|
||||
#define MODULE_EBCU0 /*lint --e(923)*/ (*(Ifx_EBCU*)0xF90E0100u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ebcu_Cfg_Ebcu0
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define EBCU0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_EBCU_ACCEN0*)0xF90E01FCu)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_ACCEN0.
|
||||
* To use register names with standard convension, please use EBCU0_ACCEN0.
|
||||
*/
|
||||
#define EBCU_ACCEN0 (EBCU0_ACCEN0)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define EBCU0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_EBCU_ACCEN1*)0xF90E01F8u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_ACCEN1.
|
||||
* To use register names with standard convension, please use EBCU0_ACCEN1.
|
||||
*/
|
||||
#define EBCU_ACCEN1 (EBCU0_ACCEN1)
|
||||
|
||||
/** \brief 10, EBCU Control Register */
|
||||
#define EBCU0_CON /*lint --e(923)*/ (*(volatile Ifx_EBCU_CON*)0xF90E0110u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_CON.
|
||||
* To use register names with standard convension, please use EBCU0_CON.
|
||||
*/
|
||||
#define EBCU_CON (EBCU0_CON)
|
||||
|
||||
/** \brief 24, Error Address Capture Register */
|
||||
#define EBCU0_EADD /*lint --e(923)*/ (*(volatile Ifx_EBCU_EADD*)0xF90E0124u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_EADD.
|
||||
* To use register names with standard convension, please use EBCU0_EADD.
|
||||
*/
|
||||
#define EBCU_EADD (EBCU0_EADD)
|
||||
|
||||
/** \brief 20, Error Control Capture Register */
|
||||
#define EBCU0_ECON /*lint --e(923)*/ (*(volatile Ifx_EBCU_ECON*)0xF90E0120u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_ECON.
|
||||
* To use register names with standard convension, please use EBCU0_ECON.
|
||||
*/
|
||||
#define EBCU_ECON (EBCU0_ECON)
|
||||
|
||||
/** \brief 28, Error Data Capture Register */
|
||||
#define EBCU0_EDAT /*lint --e(923)*/ (*(volatile Ifx_EBCU_EDAT*)0xF90E0128u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_EDAT.
|
||||
* To use register names with standard convension, please use EBCU0_EDAT.
|
||||
*/
|
||||
#define EBCU_EDAT (EBCU0_EDAT)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define EBCU0_ID /*lint --e(923)*/ (*(volatile Ifx_EBCU_ID*)0xF90E0108u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_ID.
|
||||
* To use register names with standard convension, please use EBCU0_ID.
|
||||
*/
|
||||
#define EBCU_ID (EBCU0_ID)
|
||||
|
||||
/** \brief 14, Arbiter Priority Register */
|
||||
#define EBCU0_PRIOH /*lint --e(923)*/ (*(volatile Ifx_EBCU_PRIOH*)0xF90E0114u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_PRIOH.
|
||||
* To use register names with standard convension, please use EBCU0_PRIOH.
|
||||
*/
|
||||
#define EBCU_PRIOH (EBCU0_PRIOH)
|
||||
|
||||
/** \brief 18, Arbiter Priority Register */
|
||||
#define EBCU0_PRIOL /*lint --e(923)*/ (*(volatile Ifx_EBCU_PRIOL*)0xF90E0118u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_PRIOL.
|
||||
* To use register names with standard convension, please use EBCU0_PRIOL.
|
||||
*/
|
||||
#define EBCU_PRIOL (EBCU0_PRIOL)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXEBCU_REG_H */
|
||||
@@ -1,264 +0,0 @@
|
||||
/**
|
||||
* \file IfxEbcu_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC2XXED_TS_V1.0.R2
|
||||
* Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu Ebcu
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Ebcu
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu_union Union
|
||||
* \ingroup IfxLld_Ebcu
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu_struct Struct
|
||||
* \ingroup IfxLld_Ebcu
|
||||
*
|
||||
*/
|
||||
#ifndef IFXEBCU_REGDEF_H
|
||||
#define IFXEBCU_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ebcu_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_EBCU_ACCEN0_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID x (rw) */
|
||||
} Ifx_EBCU_ACCEN0_Bits;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef struct _Ifx_EBCU_ACCEN1_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_EBCU_ACCEN1_Bits;
|
||||
|
||||
/** \brief EBCU Control Register */
|
||||
typedef struct _Ifx_EBCU_CON_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit TOUT:16; /**< \brief [15:0] Bus Time-Out Value (rw) */
|
||||
Ifx_Strict_32Bit DBG:1; /**< \brief [16:16] Debug Trace Enable (rw) */
|
||||
Ifx_Strict_32Bit reserved_17:7; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit SPC:8; /**< \brief [31:24] Starvation Period Control (rw) */
|
||||
} Ifx_EBCU_CON_Bits;
|
||||
|
||||
/** \brief Error Address Capture Register */
|
||||
typedef struct _Ifx_EBCU_EADD_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit FPIADR:32; /**< \brief [31:0] Captured FPI Bus Address (rwh) */
|
||||
} Ifx_EBCU_EADD_Bits;
|
||||
|
||||
/** \brief Error Control Capture Register */
|
||||
typedef struct _Ifx_EBCU_ECON_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit ERRCNT:14; /**< \brief [13:0] FPI Bus Error Counter (rwh) */
|
||||
Ifx_Strict_32Bit TOUT:1; /**< \brief [14:14] State of FPI Bus Time-Out Signal (rwh) */
|
||||
Ifx_Strict_32Bit RDY:1; /**< \brief [15:15] State of FPI Bus Ready Signal (rwh) */
|
||||
Ifx_Strict_32Bit ABT:1; /**< \brief [16:16] State of FPI Bus Abort Signal (rwh) */
|
||||
Ifx_Strict_32Bit ACK:2; /**< \brief [18:17] State of FPI Bus Acknowledge Signals (rwh) */
|
||||
Ifx_Strict_32Bit SVM:1; /**< \brief [19:19] State of FPI Bus Supervisor Mode Signal (rwh) */
|
||||
Ifx_Strict_32Bit WRN:1; /**< \brief [20:20] State of FPI Bus Write Signal (rwh) */
|
||||
Ifx_Strict_32Bit RDN:1; /**< \brief [21:21] State of FPI Bus Read Signal (rwh) */
|
||||
Ifx_Strict_32Bit TAG:6; /**< \brief [27:22] FPI Bus Master Tag Number Signals (rwh) */
|
||||
Ifx_Strict_32Bit OPC:4; /**< \brief [31:28] FPI Bus Operation Code Signals (rwh) */
|
||||
} Ifx_EBCU_ECON_Bits;
|
||||
|
||||
/** \brief Error Data Capture Register */
|
||||
typedef struct _Ifx_EBCU_EDAT_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit FPIDAT:32; /**< \brief [31:0] Captured FPI Bus Address (rwh) */
|
||||
} Ifx_EBCU_EDAT_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_EBCU_ID_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit MOD_REV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
Ifx_Strict_32Bit MODNUMBER:8; /**< \brief [15:8] Module Number Value (r) */
|
||||
Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_EBCU_ID_Bits;
|
||||
|
||||
/** \brief Arbiter Priority Register */
|
||||
typedef struct _Ifx_EBCU_PRIOH_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit MASTER8:4; /**< \brief [3:0] Master 8 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER9:4; /**< \brief [7:4] Master 9 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER10:4; /**< \brief [11:8] Master 10 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER11:4; /**< \brief [15:12] Master 11 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER12:4; /**< \brief [19:16] Master 12 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER13:4; /**< \brief [23:20] Master 13 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER14:4; /**< \brief [27:24] Master 14 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER15:4; /**< \brief [31:28] Master 15 Priority (rw) */
|
||||
} Ifx_EBCU_PRIOH_Bits;
|
||||
|
||||
/** \brief Arbiter Priority Register */
|
||||
typedef struct _Ifx_EBCU_PRIOL_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit MASTER0:4; /**< \brief [3:0] Master 0 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER1:4; /**< \brief [7:4] Master 1 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER2:4; /**< \brief [11:8] Master 2 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER3:4; /**< \brief [15:12] Master 3 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER4:4; /**< \brief [19:16] Master 4 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER5:4; /**< \brief [23:20] Master 5 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER6:4; /**< \brief [27:24] Master 6 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER7:4; /**< \brief [31:28] Master 7 Priority (rw) */
|
||||
} Ifx_EBCU_PRIOL_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ebcu_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_ACCEN0;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_ACCEN1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_ACCEN1;
|
||||
|
||||
/** \brief EBCU Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_CON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_CON;
|
||||
|
||||
/** \brief Error Address Capture Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_EADD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_EADD;
|
||||
|
||||
/** \brief Error Control Capture Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_ECON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_ECON;
|
||||
|
||||
/** \brief Error Data Capture Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_EDAT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_EDAT;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_ID;
|
||||
|
||||
/** \brief Arbiter Priority Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_PRIOH_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_PRIOH;
|
||||
|
||||
/** \brief Arbiter Priority Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_PRIOL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_PRIOL;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ebcu_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief EBCU object */
|
||||
typedef volatile struct _Ifx_EBCU
|
||||
{
|
||||
unsigned char reserved_0[8]; /**< \brief 0, \internal Reserved */
|
||||
Ifx_EBCU_ID ID; /**< \brief 8, Module Identification Register */
|
||||
unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
|
||||
Ifx_EBCU_CON CON; /**< \brief 10, EBCU Control Register */
|
||||
Ifx_EBCU_PRIOH PRIOH; /**< \brief 14, Arbiter Priority Register */
|
||||
Ifx_EBCU_PRIOL PRIOL; /**< \brief 18, Arbiter Priority Register */
|
||||
unsigned char reserved_1C[4]; /**< \brief 1C, \internal Reserved */
|
||||
Ifx_EBCU_ECON ECON; /**< \brief 20, Error Control Capture Register */
|
||||
Ifx_EBCU_EADD EADD; /**< \brief 24, Error Address Capture Register */
|
||||
Ifx_EBCU_EDAT EDAT; /**< \brief 28, Error Data Capture Register */
|
||||
unsigned char reserved_2C[204]; /**< \brief 2C, \internal Reserved */
|
||||
Ifx_EBCU_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
|
||||
Ifx_EBCU_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
|
||||
} Ifx_EBCU;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXEBCU_REGDEF_H */
|
||||
@@ -1,954 +0,0 @@
|
||||
/**
|
||||
* \file IfxEmem_bf.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC2XXED_TS_V1.0.R2
|
||||
* Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Emem_BitfieldsMask Bitfields mask and offset
|
||||
* \ingroup IfxLld_Emem
|
||||
*
|
||||
*/
|
||||
#ifndef IFXEMEM_BF_H
|
||||
#define IFXEMEM_BF_H 1
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Emem_BitfieldsMask
|
||||
* \{ */
|
||||
|
||||
/** \brief Length for Ifx_EMEM_CLC_Bits.DISR */
|
||||
#define IFX_EMEM_CLC_DISR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_CLC_Bits.DISR */
|
||||
#define IFX_EMEM_CLC_DISR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_CLC_Bits.DISR */
|
||||
#define IFX_EMEM_CLC_DISR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_CLC_Bits.DISS */
|
||||
#define IFX_EMEM_CLC_DISS_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_CLC_Bits.DISS */
|
||||
#define IFX_EMEM_CLC_DISS_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_CLC_Bits.DISS */
|
||||
#define IFX_EMEM_CLC_DISS_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_ID_Bits.MOD_REV */
|
||||
#define IFX_EMEM_ID_MOD_REV_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_ID_Bits.MOD_REV */
|
||||
#define IFX_EMEM_ID_MOD_REV_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_ID_Bits.MOD_REV */
|
||||
#define IFX_EMEM_ID_MOD_REV_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_ID_Bits.MOD_TYPE */
|
||||
#define IFX_EMEM_ID_MOD_TYPE_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_ID_Bits.MOD_TYPE */
|
||||
#define IFX_EMEM_ID_MOD_TYPE_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_ID_Bits.MOD_TYPE */
|
||||
#define IFX_EMEM_ID_MOD_TYPE_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_ID_Bits.MODNUMBER */
|
||||
#define IFX_EMEM_ID_MODNUMBER_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_ID_Bits.MODNUMBER */
|
||||
#define IFX_EMEM_ID_MODNUMBER_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_ID_Bits.MODNUMBER */
|
||||
#define IFX_EMEM_ID_MODNUMBER_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGEN */
|
||||
#define IFX_EMEM_SBRCTR_ACGEN_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGEN */
|
||||
#define IFX_EMEM_SBRCTR_ACGEN_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGEN */
|
||||
#define IFX_EMEM_SBRCTR_ACGEN_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST0_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST10 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST10_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST10 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST10_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST10 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST10_OFF (26u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST11 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST11_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST11 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST11_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST11 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST11_OFF (27u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST12 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST12_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST12 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST12_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST12 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST12_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST13 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST13_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST13 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST13_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST13 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST13_OFF (29u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST14 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST14_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST14 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST14_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST14 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST14_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST15 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST15_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST15 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST15_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST15 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST15_OFF (31u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST1 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST1 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST1 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST1_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST2 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST2 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST2 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST2_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST3 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST3 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST3 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST3_OFF (19u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST4 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST4_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST4 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST4_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST4 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST4_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST5 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST5_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST5 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST5_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST5 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST5_OFF (21u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST6 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST6_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST6 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST6_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST6 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST6_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST7 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST7_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST7 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST7_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST7 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST7_OFF (23u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST8 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST8_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST8 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST8_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST8 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST8_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST9 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST9_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST9 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST9_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST9 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST9_OFF (25u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGSXCM0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXCM0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGSXCM0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXCM0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGSXCM0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXCM0_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGSXTM0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXTM0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGSXTM0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXTM0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGSXTM0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXTM0_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGSXTM1 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXTM1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGSXTM1 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXTM1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGSXTM1 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXTM1_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.STBLOCK */
|
||||
#define IFX_EMEM_SBRCTR_STBLOCK_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.STBLOCK */
|
||||
#define IFX_EMEM_SBRCTR_STBLOCK_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.STBLOCK */
|
||||
#define IFX_EMEM_SBRCTR_STBLOCK_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.STBSLK */
|
||||
#define IFX_EMEM_SBRCTR_STBSLK_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.STBSLK */
|
||||
#define IFX_EMEM_SBRCTR_STBSLK_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.STBSLK */
|
||||
#define IFX_EMEM_SBRCTR_STBSLK_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.STBULK */
|
||||
#define IFX_EMEM_SBRCTR_STBULK_LEN (3u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.STBULK */
|
||||
#define IFX_EMEM_SBRCTR_STBULK_MSK (0x7u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.STBULK */
|
||||
#define IFX_EMEM_SBRCTR_STBULK_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T0 */
|
||||
#define IFX_EMEM_TILECC_T0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T0 */
|
||||
#define IFX_EMEM_TILECC_T0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T0 */
|
||||
#define IFX_EMEM_TILECC_T0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T10 */
|
||||
#define IFX_EMEM_TILECC_T10_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T10 */
|
||||
#define IFX_EMEM_TILECC_T10_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T10 */
|
||||
#define IFX_EMEM_TILECC_T10_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T11 */
|
||||
#define IFX_EMEM_TILECC_T11_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T11 */
|
||||
#define IFX_EMEM_TILECC_T11_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T11 */
|
||||
#define IFX_EMEM_TILECC_T11_OFF (11u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T12 */
|
||||
#define IFX_EMEM_TILECC_T12_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T12 */
|
||||
#define IFX_EMEM_TILECC_T12_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T12 */
|
||||
#define IFX_EMEM_TILECC_T12_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T13 */
|
||||
#define IFX_EMEM_TILECC_T13_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T13 */
|
||||
#define IFX_EMEM_TILECC_T13_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T13 */
|
||||
#define IFX_EMEM_TILECC_T13_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T14 */
|
||||
#define IFX_EMEM_TILECC_T14_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T14 */
|
||||
#define IFX_EMEM_TILECC_T14_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T14 */
|
||||
#define IFX_EMEM_TILECC_T14_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T15 */
|
||||
#define IFX_EMEM_TILECC_T15_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T15 */
|
||||
#define IFX_EMEM_TILECC_T15_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T15 */
|
||||
#define IFX_EMEM_TILECC_T15_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T1 */
|
||||
#define IFX_EMEM_TILECC_T1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T1 */
|
||||
#define IFX_EMEM_TILECC_T1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T1 */
|
||||
#define IFX_EMEM_TILECC_T1_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T2 */
|
||||
#define IFX_EMEM_TILECC_T2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T2 */
|
||||
#define IFX_EMEM_TILECC_T2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T2 */
|
||||
#define IFX_EMEM_TILECC_T2_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T3 */
|
||||
#define IFX_EMEM_TILECC_T3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T3 */
|
||||
#define IFX_EMEM_TILECC_T3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T3 */
|
||||
#define IFX_EMEM_TILECC_T3_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T4 */
|
||||
#define IFX_EMEM_TILECC_T4_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T4 */
|
||||
#define IFX_EMEM_TILECC_T4_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T4 */
|
||||
#define IFX_EMEM_TILECC_T4_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T5 */
|
||||
#define IFX_EMEM_TILECC_T5_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T5 */
|
||||
#define IFX_EMEM_TILECC_T5_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T5 */
|
||||
#define IFX_EMEM_TILECC_T5_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T6 */
|
||||
#define IFX_EMEM_TILECC_T6_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T6 */
|
||||
#define IFX_EMEM_TILECC_T6_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T6 */
|
||||
#define IFX_EMEM_TILECC_T6_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T7 */
|
||||
#define IFX_EMEM_TILECC_T7_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T7 */
|
||||
#define IFX_EMEM_TILECC_T7_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T7 */
|
||||
#define IFX_EMEM_TILECC_T7_OFF (7u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T8 */
|
||||
#define IFX_EMEM_TILECC_T8_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T8 */
|
||||
#define IFX_EMEM_TILECC_T8_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T8 */
|
||||
#define IFX_EMEM_TILECC_T8_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T9 */
|
||||
#define IFX_EMEM_TILECC_T9_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T9 */
|
||||
#define IFX_EMEM_TILECC_T9_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T9 */
|
||||
#define IFX_EMEM_TILECC_T9_OFF (9u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECC_XTM0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECC_XTM0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECC_XTM0_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECC_XTM1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECC_XTM1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECC_XTM1_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T0 */
|
||||
#define IFX_EMEM_TILECONFIG_T0_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T0 */
|
||||
#define IFX_EMEM_TILECONFIG_T0_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T0 */
|
||||
#define IFX_EMEM_TILECONFIG_T0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T10 */
|
||||
#define IFX_EMEM_TILECONFIG_T10_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T10 */
|
||||
#define IFX_EMEM_TILECONFIG_T10_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T10 */
|
||||
#define IFX_EMEM_TILECONFIG_T10_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T11 */
|
||||
#define IFX_EMEM_TILECONFIG_T11_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T11 */
|
||||
#define IFX_EMEM_TILECONFIG_T11_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T11 */
|
||||
#define IFX_EMEM_TILECONFIG_T11_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T12 */
|
||||
#define IFX_EMEM_TILECONFIG_T12_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T12 */
|
||||
#define IFX_EMEM_TILECONFIG_T12_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T12 */
|
||||
#define IFX_EMEM_TILECONFIG_T12_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T13 */
|
||||
#define IFX_EMEM_TILECONFIG_T13_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T13 */
|
||||
#define IFX_EMEM_TILECONFIG_T13_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T13 */
|
||||
#define IFX_EMEM_TILECONFIG_T13_OFF (26u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T14 */
|
||||
#define IFX_EMEM_TILECONFIG_T14_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T14 */
|
||||
#define IFX_EMEM_TILECONFIG_T14_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T14 */
|
||||
#define IFX_EMEM_TILECONFIG_T14_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T15 */
|
||||
#define IFX_EMEM_TILECONFIG_T15_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T15 */
|
||||
#define IFX_EMEM_TILECONFIG_T15_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T15 */
|
||||
#define IFX_EMEM_TILECONFIG_T15_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T1 */
|
||||
#define IFX_EMEM_TILECONFIG_T1_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T1 */
|
||||
#define IFX_EMEM_TILECONFIG_T1_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T1 */
|
||||
#define IFX_EMEM_TILECONFIG_T1_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T2 */
|
||||
#define IFX_EMEM_TILECONFIG_T2_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T2 */
|
||||
#define IFX_EMEM_TILECONFIG_T2_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T2 */
|
||||
#define IFX_EMEM_TILECONFIG_T2_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T3 */
|
||||
#define IFX_EMEM_TILECONFIG_T3_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T3 */
|
||||
#define IFX_EMEM_TILECONFIG_T3_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T3 */
|
||||
#define IFX_EMEM_TILECONFIG_T3_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T4 */
|
||||
#define IFX_EMEM_TILECONFIG_T4_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T4 */
|
||||
#define IFX_EMEM_TILECONFIG_T4_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T4 */
|
||||
#define IFX_EMEM_TILECONFIG_T4_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T5 */
|
||||
#define IFX_EMEM_TILECONFIG_T5_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T5 */
|
||||
#define IFX_EMEM_TILECONFIG_T5_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T5 */
|
||||
#define IFX_EMEM_TILECONFIG_T5_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T6 */
|
||||
#define IFX_EMEM_TILECONFIG_T6_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T6 */
|
||||
#define IFX_EMEM_TILECONFIG_T6_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T6 */
|
||||
#define IFX_EMEM_TILECONFIG_T6_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T7 */
|
||||
#define IFX_EMEM_TILECONFIG_T7_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T7 */
|
||||
#define IFX_EMEM_TILECONFIG_T7_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T7 */
|
||||
#define IFX_EMEM_TILECONFIG_T7_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T8 */
|
||||
#define IFX_EMEM_TILECONFIG_T8_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T8 */
|
||||
#define IFX_EMEM_TILECONFIG_T8_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T8 */
|
||||
#define IFX_EMEM_TILECONFIG_T8_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T9 */
|
||||
#define IFX_EMEM_TILECONFIG_T9_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T9 */
|
||||
#define IFX_EMEM_TILECONFIG_T9_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T9 */
|
||||
#define IFX_EMEM_TILECONFIG_T9_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIGXM_Bits.XCM0 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XCM0_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIGXM_Bits.XCM0 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XCM0_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIGXM_Bits.XCM0 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XCM0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIGXM_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XTM0_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIGXM_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XTM0_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIGXM_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XTM0_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIGXM_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XTM1_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIGXM_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XTM1_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIGXM_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XTM1_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T0 */
|
||||
#define IFX_EMEM_TILECT_T0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T0 */
|
||||
#define IFX_EMEM_TILECT_T0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T0 */
|
||||
#define IFX_EMEM_TILECT_T0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T10 */
|
||||
#define IFX_EMEM_TILECT_T10_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T10 */
|
||||
#define IFX_EMEM_TILECT_T10_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T10 */
|
||||
#define IFX_EMEM_TILECT_T10_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T11 */
|
||||
#define IFX_EMEM_TILECT_T11_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T11 */
|
||||
#define IFX_EMEM_TILECT_T11_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T11 */
|
||||
#define IFX_EMEM_TILECT_T11_OFF (11u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T12 */
|
||||
#define IFX_EMEM_TILECT_T12_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T12 */
|
||||
#define IFX_EMEM_TILECT_T12_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T12 */
|
||||
#define IFX_EMEM_TILECT_T12_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T13 */
|
||||
#define IFX_EMEM_TILECT_T13_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T13 */
|
||||
#define IFX_EMEM_TILECT_T13_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T13 */
|
||||
#define IFX_EMEM_TILECT_T13_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T14 */
|
||||
#define IFX_EMEM_TILECT_T14_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T14 */
|
||||
#define IFX_EMEM_TILECT_T14_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T14 */
|
||||
#define IFX_EMEM_TILECT_T14_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T15 */
|
||||
#define IFX_EMEM_TILECT_T15_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T15 */
|
||||
#define IFX_EMEM_TILECT_T15_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T15 */
|
||||
#define IFX_EMEM_TILECT_T15_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T1 */
|
||||
#define IFX_EMEM_TILECT_T1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T1 */
|
||||
#define IFX_EMEM_TILECT_T1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T1 */
|
||||
#define IFX_EMEM_TILECT_T1_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T2 */
|
||||
#define IFX_EMEM_TILECT_T2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T2 */
|
||||
#define IFX_EMEM_TILECT_T2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T2 */
|
||||
#define IFX_EMEM_TILECT_T2_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T3 */
|
||||
#define IFX_EMEM_TILECT_T3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T3 */
|
||||
#define IFX_EMEM_TILECT_T3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T3 */
|
||||
#define IFX_EMEM_TILECT_T3_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T4 */
|
||||
#define IFX_EMEM_TILECT_T4_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T4 */
|
||||
#define IFX_EMEM_TILECT_T4_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T4 */
|
||||
#define IFX_EMEM_TILECT_T4_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T5 */
|
||||
#define IFX_EMEM_TILECT_T5_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T5 */
|
||||
#define IFX_EMEM_TILECT_T5_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T5 */
|
||||
#define IFX_EMEM_TILECT_T5_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T6 */
|
||||
#define IFX_EMEM_TILECT_T6_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T6 */
|
||||
#define IFX_EMEM_TILECT_T6_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T6 */
|
||||
#define IFX_EMEM_TILECT_T6_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T7 */
|
||||
#define IFX_EMEM_TILECT_T7_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T7 */
|
||||
#define IFX_EMEM_TILECT_T7_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T7 */
|
||||
#define IFX_EMEM_TILECT_T7_OFF (7u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T8 */
|
||||
#define IFX_EMEM_TILECT_T8_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T8 */
|
||||
#define IFX_EMEM_TILECT_T8_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T8 */
|
||||
#define IFX_EMEM_TILECT_T8_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T9 */
|
||||
#define IFX_EMEM_TILECT_T9_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T9 */
|
||||
#define IFX_EMEM_TILECT_T9_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T9 */
|
||||
#define IFX_EMEM_TILECT_T9_OFF (9u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECT_XTM0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECT_XTM0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECT_XTM0_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECT_XTM1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECT_XTM1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECT_XTM1_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE0 */
|
||||
#define IFX_EMEM_TILESTATE_TILE0_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE0 */
|
||||
#define IFX_EMEM_TILESTATE_TILE0_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE0 */
|
||||
#define IFX_EMEM_TILESTATE_TILE0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE10 */
|
||||
#define IFX_EMEM_TILESTATE_TILE10_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE10 */
|
||||
#define IFX_EMEM_TILESTATE_TILE10_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE10 */
|
||||
#define IFX_EMEM_TILESTATE_TILE10_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE11 */
|
||||
#define IFX_EMEM_TILESTATE_TILE11_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE11 */
|
||||
#define IFX_EMEM_TILESTATE_TILE11_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE11 */
|
||||
#define IFX_EMEM_TILESTATE_TILE11_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE12 */
|
||||
#define IFX_EMEM_TILESTATE_TILE12_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE12 */
|
||||
#define IFX_EMEM_TILESTATE_TILE12_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE12 */
|
||||
#define IFX_EMEM_TILESTATE_TILE12_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE13 */
|
||||
#define IFX_EMEM_TILESTATE_TILE13_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE13 */
|
||||
#define IFX_EMEM_TILESTATE_TILE13_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE13 */
|
||||
#define IFX_EMEM_TILESTATE_TILE13_OFF (26u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE14 */
|
||||
#define IFX_EMEM_TILESTATE_TILE14_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE14 */
|
||||
#define IFX_EMEM_TILESTATE_TILE14_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE14 */
|
||||
#define IFX_EMEM_TILESTATE_TILE14_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE15 */
|
||||
#define IFX_EMEM_TILESTATE_TILE15_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE15 */
|
||||
#define IFX_EMEM_TILESTATE_TILE15_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE15 */
|
||||
#define IFX_EMEM_TILESTATE_TILE15_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE1 */
|
||||
#define IFX_EMEM_TILESTATE_TILE1_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE1 */
|
||||
#define IFX_EMEM_TILESTATE_TILE1_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE1 */
|
||||
#define IFX_EMEM_TILESTATE_TILE1_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE2 */
|
||||
#define IFX_EMEM_TILESTATE_TILE2_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE2 */
|
||||
#define IFX_EMEM_TILESTATE_TILE2_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE2 */
|
||||
#define IFX_EMEM_TILESTATE_TILE2_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE3 */
|
||||
#define IFX_EMEM_TILESTATE_TILE3_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE3 */
|
||||
#define IFX_EMEM_TILESTATE_TILE3_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE3 */
|
||||
#define IFX_EMEM_TILESTATE_TILE3_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE4 */
|
||||
#define IFX_EMEM_TILESTATE_TILE4_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE4 */
|
||||
#define IFX_EMEM_TILESTATE_TILE4_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE4 */
|
||||
#define IFX_EMEM_TILESTATE_TILE4_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE5 */
|
||||
#define IFX_EMEM_TILESTATE_TILE5_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE5 */
|
||||
#define IFX_EMEM_TILESTATE_TILE5_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE5 */
|
||||
#define IFX_EMEM_TILESTATE_TILE5_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE6 */
|
||||
#define IFX_EMEM_TILESTATE_TILE6_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE6 */
|
||||
#define IFX_EMEM_TILESTATE_TILE6_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE6 */
|
||||
#define IFX_EMEM_TILESTATE_TILE6_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE7 */
|
||||
#define IFX_EMEM_TILESTATE_TILE7_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE7 */
|
||||
#define IFX_EMEM_TILESTATE_TILE7_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE7 */
|
||||
#define IFX_EMEM_TILESTATE_TILE7_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE8 */
|
||||
#define IFX_EMEM_TILESTATE_TILE8_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE8 */
|
||||
#define IFX_EMEM_TILESTATE_TILE8_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE8 */
|
||||
#define IFX_EMEM_TILESTATE_TILE8_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE9 */
|
||||
#define IFX_EMEM_TILESTATE_TILE9_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE9 */
|
||||
#define IFX_EMEM_TILESTATE_TILE9_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE9 */
|
||||
#define IFX_EMEM_TILESTATE_TILE9_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATEXM_Bits.XCM0 */
|
||||
#define IFX_EMEM_TILESTATEXM_XCM0_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATEXM_Bits.XCM0 */
|
||||
#define IFX_EMEM_TILESTATEXM_XCM0_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATEXM_Bits.XCM0 */
|
||||
#define IFX_EMEM_TILESTATEXM_XCM0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATEXM_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILESTATEXM_XTM0_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATEXM_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILESTATEXM_XTM0_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATEXM_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILESTATEXM_XTM0_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATEXM_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILESTATEXM_XTM1_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATEXM_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILESTATEXM_XTM1_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATEXM_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILESTATEXM_XTM1_OFF (18u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXEMEM_BF_H */
|
||||
@@ -1,78 +0,0 @@
|
||||
/**
|
||||
* \file IfxEmem_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC2XXED_TS_V1.0.R2
|
||||
* Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Emem_Cfg Emem address
|
||||
* \ingroup IfxLld_Emem
|
||||
*
|
||||
* \defgroup IfxLld_Emem_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Emem_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Emem_Cfg_Emem 2-EMEM
|
||||
* \ingroup IfxLld_Emem_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXEMEM_REG_H
|
||||
#define IFXEMEM_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxEmem_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Emem_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief EMEM object */
|
||||
#define MODULE_EMEM /*lint --e(923)*/ (*(Ifx_EMEM*)0xF90E6000u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Emem_Cfg_Emem
|
||||
* \{ */
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define EMEM_CLC /*lint --e(923)*/ (*(volatile Ifx_EMEM_CLC*)0xF90E6000u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define EMEM_ID /*lint --e(923)*/ (*(volatile Ifx_EMEM_ID*)0xF90E6008u)
|
||||
|
||||
/** \brief 34, Standby RAM Control Register */
|
||||
#define EMEM_SBRCTR /*lint --e(923)*/ (*(volatile Ifx_EMEM_SBRCTR*)0xF90E6034u)
|
||||
|
||||
/** \brief 24, Calibration Tile Control Register */
|
||||
#define EMEM_TILECC /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILECC*)0xF90E6024u)
|
||||
|
||||
/** \brief 20, Tile Configuration Register */
|
||||
#define EMEM_TILECONFIG /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILECONFIG*)0xF90E6020u)
|
||||
|
||||
/** \brief 40, Extended Tile Configuration Register */
|
||||
#define EMEM_TILECONFIGXM /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILECONFIGXM*)0xF90E6040u)
|
||||
|
||||
/** \brief 28, Trace Tile Control Register */
|
||||
#define EMEM_TILECT /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILECT*)0xF90E6028u)
|
||||
|
||||
/** \brief 2C, Tile Status Register */
|
||||
#define EMEM_TILESTATE /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILESTATE*)0xF90E602Cu)
|
||||
|
||||
/** \brief 4C, Extended Tile Status Register */
|
||||
#define EMEM_TILESTATEXM /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILESTATEXM*)0xF90E604Cu)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXEMEM_REG_H */
|
||||
@@ -1,309 +0,0 @@
|
||||
/**
|
||||
* \file IfxEmem_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC2XXED_TS_V1.0.R2
|
||||
* Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Emem Emem
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Emem_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Emem
|
||||
*
|
||||
* \defgroup IfxLld_Emem_union Union
|
||||
* \ingroup IfxLld_Emem
|
||||
*
|
||||
* \defgroup IfxLld_Emem_struct Struct
|
||||
* \ingroup IfxLld_Emem
|
||||
*
|
||||
*/
|
||||
#ifndef IFXEMEM_REGDEF_H
|
||||
#define IFXEMEM_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Emem_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef struct _Ifx_EMEM_CLC_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
Ifx_Strict_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
|
||||
Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_EMEM_CLC_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_EMEM_ID_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit MOD_REV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
Ifx_Strict_32Bit MOD_TYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
Ifx_Strict_32Bit MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_EMEM_ID_Bits;
|
||||
|
||||
/** \brief Standby RAM Control Register */
|
||||
typedef struct _Ifx_EMEM_SBRCTR_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit STBLOCK:1; /**< \brief [0:0] Standby Lock Flag (rh) */
|
||||
Ifx_Strict_32Bit STBULK:3; /**< \brief [3:1] Unlock Standby Lock Flag (w) */
|
||||
Ifx_Strict_32Bit STBSLK:4; /**< \brief [7:4] Set Standby Lock Flag (w) */
|
||||
Ifx_Strict_32Bit ACGSXCM0:1; /**< \brief [8:8] Automatic Clock Gating Status of XCM0 (rh) */
|
||||
Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit ACGEN:1; /**< \brief [12:12] Automatic Clock Gating Enabling (rw) */
|
||||
Ifx_Strict_32Bit ACGSXTM0:1; /**< \brief [13:13] Automatic Clock Gating Status of XTM0 (rh) */
|
||||
Ifx_Strict_32Bit ACGSXTM1:1; /**< \brief [14:14] Automatic Clock Gating Status of XTM1 (rh) */
|
||||
Ifx_Strict_32Bit reserved_15:1; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit ACGST0:1; /**< \brief [16:16] Automatic Clock Gating Status of Tile 0 (rh) */
|
||||
Ifx_Strict_32Bit ACGST1:1; /**< \brief [17:17] Automatic Clock Gating Status of Tile 1 (rh) */
|
||||
Ifx_Strict_32Bit ACGST2:1; /**< \brief [18:18] Automatic Clock Gating Status of Tile 2 (rh) */
|
||||
Ifx_Strict_32Bit ACGST3:1; /**< \brief [19:19] Automatic Clock Gating Status of Tile 3 (rh) */
|
||||
Ifx_Strict_32Bit ACGST4:1; /**< \brief [20:20] Automatic Clock Gating Status of Tile 4 (rh) */
|
||||
Ifx_Strict_32Bit ACGST5:1; /**< \brief [21:21] Automatic Clock Gating Status of Tile 5 (rh) */
|
||||
Ifx_Strict_32Bit ACGST6:1; /**< \brief [22:22] Automatic Clock Gating Status of Tile 6 (rh) */
|
||||
Ifx_Strict_32Bit ACGST7:1; /**< \brief [23:23] Automatic Clock Gating Status of Tile 7 (rh) */
|
||||
Ifx_Strict_32Bit ACGST8:1; /**< \brief [24:24] Automatic Clock Gating Status of Tile 8 (rh) */
|
||||
Ifx_Strict_32Bit ACGST9:1; /**< \brief [25:25] Automatic Clock Gating Status of Tile 9 (rh) */
|
||||
Ifx_Strict_32Bit ACGST10:1; /**< \brief [26:26] Automatic Clock Gating Status of Tile 10 (rh) */
|
||||
Ifx_Strict_32Bit ACGST11:1; /**< \brief [27:27] Automatic Clock Gating Status of Tile 11 (rh) */
|
||||
Ifx_Strict_32Bit ACGST12:1; /**< \brief [28:28] Automatic Clock Gating Status of Tile 12 (rh) */
|
||||
Ifx_Strict_32Bit ACGST13:1; /**< \brief [29:29] Automatic Clock Gating Status of Tile 13 (rh) */
|
||||
Ifx_Strict_32Bit ACGST14:1; /**< \brief [30:30] Automatic Clock Gating Status of Tile 14 (rh) */
|
||||
Ifx_Strict_32Bit ACGST15:1; /**< \brief [31:31] Automatic Clock Gating Status of Tile 15 (rh) */
|
||||
} Ifx_EMEM_SBRCTR_Bits;
|
||||
|
||||
/** \brief Calibration Tile Control Register */
|
||||
typedef struct _Ifx_EMEM_TILECC_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit T0:1; /**< \brief [0:0] Calibration Tile 0 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T1:1; /**< \brief [1:1] Calibration Tile 1 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T2:1; /**< \brief [2:2] Calibration Tile 2 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T3:1; /**< \brief [3:3] Calibration Tile 3 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T4:1; /**< \brief [4:4] Calibration Tile 4 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T5:1; /**< \brief [5:5] Calibration Tile 5 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T6:1; /**< \brief [6:6] Calibration Tile 6 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T7:1; /**< \brief [7:7] Calibration Tile 7 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T8:1; /**< \brief [8:8] Calibration Tile 8 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T9:1; /**< \brief [9:9] Calibration Tile 9 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T10:1; /**< \brief [10:10] Calibration Tile 10 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T11:1; /**< \brief [11:11] Calibration Tile 11 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T12:1; /**< \brief [12:12] Calibration Tile 12 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T13:1; /**< \brief [13:13] Calibration Tile 13 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T14:1; /**< \brief [14:14] Calibration Tile 14 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T15:1; /**< \brief [15:15] Calibration Tile 15 Control Bit (w) */
|
||||
Ifx_Strict_32Bit XTM0:1; /**< \brief [16:16] Calibration XTM0 Tile Control Bit (w) */
|
||||
Ifx_Strict_32Bit XTM1:1; /**< \brief [17:17] Calibration XTM1 Tile Control Bit (w) */
|
||||
Ifx_Strict_32Bit reserved_18:14; /**< \brief \internal Reserved */
|
||||
} Ifx_EMEM_TILECC_Bits;
|
||||
|
||||
/** \brief Tile Configuration Register */
|
||||
typedef struct _Ifx_EMEM_TILECONFIG_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit T0:2; /**< \brief [1:0] Tile 0 Allocation (w) */
|
||||
Ifx_Strict_32Bit T1:2; /**< \brief [3:2] Tile 1 Allocation (w) */
|
||||
Ifx_Strict_32Bit T2:2; /**< \brief [5:4] Tile 2 Allocation (w) */
|
||||
Ifx_Strict_32Bit T3:2; /**< \brief [7:6] Tile 3 Allocation (w) */
|
||||
Ifx_Strict_32Bit T4:2; /**< \brief [9:8] Tile 4 Allocation (w) */
|
||||
Ifx_Strict_32Bit T5:2; /**< \brief [11:10] Tile 5 Allocation (w) */
|
||||
Ifx_Strict_32Bit T6:2; /**< \brief [13:12] Tile 6 Allocation (w) */
|
||||
Ifx_Strict_32Bit T7:2; /**< \brief [15:14] Tile 7 Allocation (w) */
|
||||
Ifx_Strict_32Bit T8:2; /**< \brief [17:16] Tile 8 Allocation (w) */
|
||||
Ifx_Strict_32Bit T9:2; /**< \brief [19:18] Tile 9 Allocation (w) */
|
||||
Ifx_Strict_32Bit T10:2; /**< \brief [21:20] Tile 10 Allocation (w) */
|
||||
Ifx_Strict_32Bit T11:2; /**< \brief [23:22] Tile 11 Allocation (w) */
|
||||
Ifx_Strict_32Bit T12:2; /**< \brief [25:24] Tile 12 Allocation (w) */
|
||||
Ifx_Strict_32Bit T13:2; /**< \brief [27:26] Tile 13 Allocation (w) */
|
||||
Ifx_Strict_32Bit T14:2; /**< \brief [29:28] Tile 14 Allocation (w) */
|
||||
Ifx_Strict_32Bit T15:2; /**< \brief [31:30] Tile 15 Allocation (w) */
|
||||
} Ifx_EMEM_TILECONFIG_Bits;
|
||||
|
||||
/** \brief Extended Tile Configuration Register */
|
||||
typedef struct _Ifx_EMEM_TILECONFIGXM_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit XCM0:2; /**< \brief [1:0] XCM0 Tile Allocation (w) */
|
||||
Ifx_Strict_32Bit reserved_2:14; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit XTM0:2; /**< \brief [17:16] XTM0 Tile Allocation (w) */
|
||||
Ifx_Strict_32Bit XTM1:2; /**< \brief [19:18] XTM1 Tile Allocation (w) */
|
||||
Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_EMEM_TILECONFIGXM_Bits;
|
||||
|
||||
/** \brief Trace Tile Control Register */
|
||||
typedef struct _Ifx_EMEM_TILECT_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit T0:1; /**< \brief [0:0] Trace Tile 0 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T1:1; /**< \brief [1:1] Trace Tile 1 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T2:1; /**< \brief [2:2] Trace Tile 2 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T3:1; /**< \brief [3:3] Trace Tile 3 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T4:1; /**< \brief [4:4] Trace Tile 4 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T5:1; /**< \brief [5:5] Trace Tile 5 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T6:1; /**< \brief [6:6] Trace Tile 6 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T7:1; /**< \brief [7:7] Trace Tile 7 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T8:1; /**< \brief [8:8] Trace Tile 8 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T9:1; /**< \brief [9:9] Trace Tile 9 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T10:1; /**< \brief [10:10] Trace Tile 10 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T11:1; /**< \brief [11:11] Trace Tile 11 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T12:1; /**< \brief [12:12] Trace Tile 12 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T13:1; /**< \brief [13:13] Trace Tile 13 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T14:1; /**< \brief [14:14] Trace Tile 14 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T15:1; /**< \brief [15:15] Trace Tile 15 Control Bit (w) */
|
||||
Ifx_Strict_32Bit XTM0:1; /**< \brief [16:16] Trace XTM0 Tile Control Bit (w) */
|
||||
Ifx_Strict_32Bit XTM1:1; /**< \brief [17:17] Trace XTM1 Tile Control Bit (w) */
|
||||
Ifx_Strict_32Bit reserved_18:14; /**< \brief \internal Reserved */
|
||||
} Ifx_EMEM_TILECT_Bits;
|
||||
|
||||
/** \brief Tile Status Register */
|
||||
typedef struct _Ifx_EMEM_TILESTATE_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit TILE0:2; /**< \brief [1:0] Usage of Tile 0 (rh) */
|
||||
Ifx_Strict_32Bit TILE1:2; /**< \brief [3:2] Usage of Tile 1 (rh) */
|
||||
Ifx_Strict_32Bit TILE2:2; /**< \brief [5:4] Usage of Tile 2 (rh) */
|
||||
Ifx_Strict_32Bit TILE3:2; /**< \brief [7:6] Usage of Tile 3 (rh) */
|
||||
Ifx_Strict_32Bit TILE4:2; /**< \brief [9:8] Usage of Tile 4 (rh) */
|
||||
Ifx_Strict_32Bit TILE5:2; /**< \brief [11:10] Usage of Tile 5 (rh) */
|
||||
Ifx_Strict_32Bit TILE6:2; /**< \brief [13:12] Usage of Tile 6 (rh) */
|
||||
Ifx_Strict_32Bit TILE7:2; /**< \brief [15:14] Usage of Tile 7 (rh) */
|
||||
Ifx_Strict_32Bit TILE8:2; /**< \brief [17:16] Usage of Tile 8 (rh) */
|
||||
Ifx_Strict_32Bit TILE9:2; /**< \brief [19:18] Usage of Tile 9 (rh) */
|
||||
Ifx_Strict_32Bit TILE10:2; /**< \brief [21:20] Usage of Tile 10 (rh) */
|
||||
Ifx_Strict_32Bit TILE11:2; /**< \brief [23:22] Usage of Tile 11 (rh) */
|
||||
Ifx_Strict_32Bit TILE12:2; /**< \brief [25:24] Usage of Tile 12 (rh) */
|
||||
Ifx_Strict_32Bit TILE13:2; /**< \brief [27:26] Usage of Tile 13 (rh) */
|
||||
Ifx_Strict_32Bit TILE14:2; /**< \brief [29:28] Usage of Tile 14 (rh) */
|
||||
Ifx_Strict_32Bit TILE15:2; /**< \brief [31:30] Usage of Tile 15 (rh) */
|
||||
} Ifx_EMEM_TILESTATE_Bits;
|
||||
|
||||
/** \brief Extended Tile Status Register */
|
||||
typedef struct _Ifx_EMEM_TILESTATEXM_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit XCM0:2; /**< \brief [1:0] Usage of XCM0 Tile (rh) */
|
||||
Ifx_Strict_32Bit reserved_2:14; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit XTM0:2; /**< \brief [17:16] Usage of XTM0 Tile (rh) */
|
||||
Ifx_Strict_32Bit XTM1:2; /**< \brief [19:18] Usage of XTM1 Tile (rh) */
|
||||
Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_EMEM_TILESTATEXM_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Emem_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_CLC;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_ID;
|
||||
|
||||
/** \brief Standby RAM Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_SBRCTR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_SBRCTR;
|
||||
|
||||
/** \brief Calibration Tile Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_TILECC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_TILECC;
|
||||
|
||||
/** \brief Tile Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_TILECONFIG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_TILECONFIG;
|
||||
|
||||
/** \brief Extended Tile Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_TILECONFIGXM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_TILECONFIGXM;
|
||||
|
||||
/** \brief Trace Tile Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_TILECT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_TILECT;
|
||||
|
||||
/** \brief Tile Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_TILESTATE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_TILESTATE;
|
||||
|
||||
/** \brief Extended Tile Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_TILESTATEXM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_TILESTATEXM;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Emem_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief EMEM object */
|
||||
typedef volatile struct _Ifx_EMEM
|
||||
{
|
||||
Ifx_EMEM_CLC CLC; /**< \brief 0, Clock Control Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_EMEM_ID ID; /**< \brief 8, Module Identification Register */
|
||||
unsigned char reserved_C[20]; /**< \brief C, \internal Reserved */
|
||||
Ifx_EMEM_TILECONFIG TILECONFIG; /**< \brief 20, Tile Configuration Register */
|
||||
Ifx_EMEM_TILECC TILECC; /**< \brief 24, Calibration Tile Control Register */
|
||||
Ifx_EMEM_TILECT TILECT; /**< \brief 28, Trace Tile Control Register */
|
||||
Ifx_EMEM_TILESTATE TILESTATE; /**< \brief 2C, Tile Status Register */
|
||||
unsigned char reserved_30[4]; /**< \brief 30, \internal Reserved */
|
||||
Ifx_EMEM_SBRCTR SBRCTR; /**< \brief 34, Standby RAM Control Register */
|
||||
unsigned char reserved_38[8]; /**< \brief 38, \internal Reserved */
|
||||
Ifx_EMEM_TILECONFIGXM TILECONFIGXM; /**< \brief 40, Extended Tile Configuration Register */
|
||||
unsigned char reserved_44[8]; /**< \brief 44, \internal Reserved */
|
||||
Ifx_EMEM_TILESTATEXM TILESTATEXM; /**< \brief 4C, Extended Tile Status Register */
|
||||
unsigned char reserved_50[176]; /**< \brief 50, \internal Reserved */
|
||||
} Ifx_EMEM;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXEMEM_REGDEF_H */
|
||||
File diff suppressed because it is too large
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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Load Diff
@@ -1,702 +0,0 @@
|
||||
/**
|
||||
* \file IfxFce_bf.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Fce_BitfieldsMask Bitfields mask and offset
|
||||
* \ingroup IfxLld_Fce
|
||||
*
|
||||
*/
|
||||
#ifndef IFXFCE_BF_H
|
||||
#define IFXFCE_BF_H 1
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Fce_BitfieldsMask
|
||||
* \{ */
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN0 */
|
||||
#define IFX_FCE_ACCEN0_EN0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN0 */
|
||||
#define IFX_FCE_ACCEN0_EN0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN0 */
|
||||
#define IFX_FCE_ACCEN0_EN0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN10 */
|
||||
#define IFX_FCE_ACCEN0_EN10_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN10 */
|
||||
#define IFX_FCE_ACCEN0_EN10_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN10 */
|
||||
#define IFX_FCE_ACCEN0_EN10_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN11 */
|
||||
#define IFX_FCE_ACCEN0_EN11_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN11 */
|
||||
#define IFX_FCE_ACCEN0_EN11_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN11 */
|
||||
#define IFX_FCE_ACCEN0_EN11_OFF (11u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN12 */
|
||||
#define IFX_FCE_ACCEN0_EN12_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN12 */
|
||||
#define IFX_FCE_ACCEN0_EN12_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN12 */
|
||||
#define IFX_FCE_ACCEN0_EN12_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN13 */
|
||||
#define IFX_FCE_ACCEN0_EN13_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN13 */
|
||||
#define IFX_FCE_ACCEN0_EN13_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN13 */
|
||||
#define IFX_FCE_ACCEN0_EN13_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN14 */
|
||||
#define IFX_FCE_ACCEN0_EN14_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN14 */
|
||||
#define IFX_FCE_ACCEN0_EN14_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN14 */
|
||||
#define IFX_FCE_ACCEN0_EN14_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN15 */
|
||||
#define IFX_FCE_ACCEN0_EN15_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN15 */
|
||||
#define IFX_FCE_ACCEN0_EN15_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN15 */
|
||||
#define IFX_FCE_ACCEN0_EN15_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN16 */
|
||||
#define IFX_FCE_ACCEN0_EN16_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN16 */
|
||||
#define IFX_FCE_ACCEN0_EN16_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN16 */
|
||||
#define IFX_FCE_ACCEN0_EN16_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN17 */
|
||||
#define IFX_FCE_ACCEN0_EN17_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN17 */
|
||||
#define IFX_FCE_ACCEN0_EN17_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN17 */
|
||||
#define IFX_FCE_ACCEN0_EN17_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN18 */
|
||||
#define IFX_FCE_ACCEN0_EN18_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN18 */
|
||||
#define IFX_FCE_ACCEN0_EN18_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN18 */
|
||||
#define IFX_FCE_ACCEN0_EN18_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN19 */
|
||||
#define IFX_FCE_ACCEN0_EN19_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN19 */
|
||||
#define IFX_FCE_ACCEN0_EN19_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN19 */
|
||||
#define IFX_FCE_ACCEN0_EN19_OFF (19u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN1 */
|
||||
#define IFX_FCE_ACCEN0_EN1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN1 */
|
||||
#define IFX_FCE_ACCEN0_EN1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN1 */
|
||||
#define IFX_FCE_ACCEN0_EN1_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN20 */
|
||||
#define IFX_FCE_ACCEN0_EN20_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN20 */
|
||||
#define IFX_FCE_ACCEN0_EN20_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN20 */
|
||||
#define IFX_FCE_ACCEN0_EN20_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN21 */
|
||||
#define IFX_FCE_ACCEN0_EN21_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN21 */
|
||||
#define IFX_FCE_ACCEN0_EN21_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN21 */
|
||||
#define IFX_FCE_ACCEN0_EN21_OFF (21u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN22 */
|
||||
#define IFX_FCE_ACCEN0_EN22_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN22 */
|
||||
#define IFX_FCE_ACCEN0_EN22_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN22 */
|
||||
#define IFX_FCE_ACCEN0_EN22_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN23 */
|
||||
#define IFX_FCE_ACCEN0_EN23_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN23 */
|
||||
#define IFX_FCE_ACCEN0_EN23_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN23 */
|
||||
#define IFX_FCE_ACCEN0_EN23_OFF (23u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN24 */
|
||||
#define IFX_FCE_ACCEN0_EN24_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN24 */
|
||||
#define IFX_FCE_ACCEN0_EN24_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN24 */
|
||||
#define IFX_FCE_ACCEN0_EN24_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN25 */
|
||||
#define IFX_FCE_ACCEN0_EN25_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN25 */
|
||||
#define IFX_FCE_ACCEN0_EN25_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN25 */
|
||||
#define IFX_FCE_ACCEN0_EN25_OFF (25u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN26 */
|
||||
#define IFX_FCE_ACCEN0_EN26_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN26 */
|
||||
#define IFX_FCE_ACCEN0_EN26_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN26 */
|
||||
#define IFX_FCE_ACCEN0_EN26_OFF (26u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN27 */
|
||||
#define IFX_FCE_ACCEN0_EN27_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN27 */
|
||||
#define IFX_FCE_ACCEN0_EN27_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN27 */
|
||||
#define IFX_FCE_ACCEN0_EN27_OFF (27u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN28 */
|
||||
#define IFX_FCE_ACCEN0_EN28_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN28 */
|
||||
#define IFX_FCE_ACCEN0_EN28_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN28 */
|
||||
#define IFX_FCE_ACCEN0_EN28_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN29 */
|
||||
#define IFX_FCE_ACCEN0_EN29_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN29 */
|
||||
#define IFX_FCE_ACCEN0_EN29_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN29 */
|
||||
#define IFX_FCE_ACCEN0_EN29_OFF (29u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN2 */
|
||||
#define IFX_FCE_ACCEN0_EN2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN2 */
|
||||
#define IFX_FCE_ACCEN0_EN2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN2 */
|
||||
#define IFX_FCE_ACCEN0_EN2_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN30 */
|
||||
#define IFX_FCE_ACCEN0_EN30_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN30 */
|
||||
#define IFX_FCE_ACCEN0_EN30_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN30 */
|
||||
#define IFX_FCE_ACCEN0_EN30_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN31 */
|
||||
#define IFX_FCE_ACCEN0_EN31_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN31 */
|
||||
#define IFX_FCE_ACCEN0_EN31_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN31 */
|
||||
#define IFX_FCE_ACCEN0_EN31_OFF (31u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN3 */
|
||||
#define IFX_FCE_ACCEN0_EN3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN3 */
|
||||
#define IFX_FCE_ACCEN0_EN3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN3 */
|
||||
#define IFX_FCE_ACCEN0_EN3_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN4 */
|
||||
#define IFX_FCE_ACCEN0_EN4_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN4 */
|
||||
#define IFX_FCE_ACCEN0_EN4_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN4 */
|
||||
#define IFX_FCE_ACCEN0_EN4_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN5 */
|
||||
#define IFX_FCE_ACCEN0_EN5_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN5 */
|
||||
#define IFX_FCE_ACCEN0_EN5_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN5 */
|
||||
#define IFX_FCE_ACCEN0_EN5_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN6 */
|
||||
#define IFX_FCE_ACCEN0_EN6_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN6 */
|
||||
#define IFX_FCE_ACCEN0_EN6_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN6 */
|
||||
#define IFX_FCE_ACCEN0_EN6_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN7 */
|
||||
#define IFX_FCE_ACCEN0_EN7_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN7 */
|
||||
#define IFX_FCE_ACCEN0_EN7_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN7 */
|
||||
#define IFX_FCE_ACCEN0_EN7_OFF (7u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN8 */
|
||||
#define IFX_FCE_ACCEN0_EN8_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN8 */
|
||||
#define IFX_FCE_ACCEN0_EN8_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN8 */
|
||||
#define IFX_FCE_ACCEN0_EN8_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ACCEN0_Bits.EN9 */
|
||||
#define IFX_FCE_ACCEN0_EN9_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ACCEN0_Bits.EN9 */
|
||||
#define IFX_FCE_ACCEN0_EN9_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ACCEN0_Bits.EN9 */
|
||||
#define IFX_FCE_ACCEN0_EN9_OFF (9u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_CFG_Bits.ALR */
|
||||
#define IFX_FCE_CFG_ALR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_CFG_Bits.ALR */
|
||||
#define IFX_FCE_CFG_ALR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_CFG_Bits.ALR */
|
||||
#define IFX_FCE_CFG_ALR_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_CFG_Bits.BEI */
|
||||
#define IFX_FCE_CFG_BEI_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_CFG_Bits.BEI */
|
||||
#define IFX_FCE_CFG_BEI_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_CFG_Bits.BEI */
|
||||
#define IFX_FCE_CFG_BEI_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_CFG_Bits.CCE */
|
||||
#define IFX_FCE_CFG_CCE_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_CFG_Bits.CCE */
|
||||
#define IFX_FCE_CFG_CCE_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_CFG_Bits.CCE */
|
||||
#define IFX_FCE_CFG_CCE_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_CFG_Bits.CEI */
|
||||
#define IFX_FCE_CFG_CEI_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_CFG_Bits.CEI */
|
||||
#define IFX_FCE_CFG_CEI_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_CFG_Bits.CEI */
|
||||
#define IFX_FCE_CFG_CEI_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_CFG_Bits.CMI */
|
||||
#define IFX_FCE_CFG_CMI_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_CFG_Bits.CMI */
|
||||
#define IFX_FCE_CFG_CMI_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_CFG_Bits.CMI */
|
||||
#define IFX_FCE_CFG_CMI_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_CFG_Bits.LEI */
|
||||
#define IFX_FCE_CFG_LEI_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_CFG_Bits.LEI */
|
||||
#define IFX_FCE_CFG_LEI_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_CFG_Bits.LEI */
|
||||
#define IFX_FCE_CFG_LEI_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_CFG_Bits.REFIN */
|
||||
#define IFX_FCE_CFG_REFIN_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_CFG_Bits.REFIN */
|
||||
#define IFX_FCE_CFG_REFIN_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_CFG_Bits.REFIN */
|
||||
#define IFX_FCE_CFG_REFIN_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_CFG_Bits.REFOUT */
|
||||
#define IFX_FCE_CFG_REFOUT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_CFG_Bits.REFOUT */
|
||||
#define IFX_FCE_CFG_REFOUT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_CFG_Bits.REFOUT */
|
||||
#define IFX_FCE_CFG_REFOUT_OFF (9u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_CFG_Bits.XSEL */
|
||||
#define IFX_FCE_CFG_XSEL_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_CFG_Bits.XSEL */
|
||||
#define IFX_FCE_CFG_XSEL_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_CFG_Bits.XSEL */
|
||||
#define IFX_FCE_CFG_XSEL_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_CLC_Bits.DISR */
|
||||
#define IFX_FCE_CLC_DISR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_CLC_Bits.DISR */
|
||||
#define IFX_FCE_CLC_DISR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_CLC_Bits.DISR */
|
||||
#define IFX_FCE_CLC_DISR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_CLC_Bits.DISS */
|
||||
#define IFX_FCE_CLC_DISS_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_CLC_Bits.DISS */
|
||||
#define IFX_FCE_CLC_DISS_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_CLC_Bits.DISS */
|
||||
#define IFX_FCE_CLC_DISS_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_CTR_Bits.FCM */
|
||||
#define IFX_FCE_CTR_FCM_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_CTR_Bits.FCM */
|
||||
#define IFX_FCE_CTR_FCM_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_CTR_Bits.FCM */
|
||||
#define IFX_FCE_CTR_FCM_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_CTR_Bits.FRM_CFG */
|
||||
#define IFX_FCE_CTR_FRM_CFG_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_CTR_Bits.FRM_CFG */
|
||||
#define IFX_FCE_CTR_FRM_CFG_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_CTR_Bits.FRM_CFG */
|
||||
#define IFX_FCE_CTR_FRM_CFG_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_CTR_Bits.FRM_CHECK */
|
||||
#define IFX_FCE_CTR_FRM_CHECK_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_CTR_Bits.FRM_CHECK */
|
||||
#define IFX_FCE_CTR_FRM_CHECK_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_CTR_Bits.FRM_CHECK */
|
||||
#define IFX_FCE_CTR_FRM_CHECK_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ID_Bits.MODNUMBER */
|
||||
#define IFX_FCE_ID_MODNUMBER_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ID_Bits.MODNUMBER */
|
||||
#define IFX_FCE_ID_MODNUMBER_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ID_Bits.MODNUMBER */
|
||||
#define IFX_FCE_ID_MODNUMBER_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ID_Bits.MODREV */
|
||||
#define IFX_FCE_ID_MODREV_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ID_Bits.MODREV */
|
||||
#define IFX_FCE_ID_MODREV_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ID_Bits.MODREV */
|
||||
#define IFX_FCE_ID_MODREV_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_ID_Bits.MODTYPE */
|
||||
#define IFX_FCE_ID_MODTYPE_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_ID_Bits.MODTYPE */
|
||||
#define IFX_FCE_ID_MODTYPE_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_ID_Bits.MODTYPE */
|
||||
#define IFX_FCE_ID_MODTYPE_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN0_CHECK_Bits.CHECK */
|
||||
#define IFX_FCE_IN0_CHECK_CHECK_LEN (32u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN0_CHECK_Bits.CHECK */
|
||||
#define IFX_FCE_IN0_CHECK_CHECK_MSK (0xffffffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN0_CHECK_Bits.CHECK */
|
||||
#define IFX_FCE_IN0_CHECK_CHECK_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN0_CRC_Bits.CRC */
|
||||
#define IFX_FCE_IN0_CRC_CRC_LEN (32u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN0_CRC_Bits.CRC */
|
||||
#define IFX_FCE_IN0_CRC_CRC_MSK (0xffffffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN0_CRC_Bits.CRC */
|
||||
#define IFX_FCE_IN0_CRC_CRC_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN0_IR_Bits.IR */
|
||||
#define IFX_FCE_IN0_IR_IR_LEN (32u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN0_IR_Bits.IR */
|
||||
#define IFX_FCE_IN0_IR_IR_MSK (0xffffffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN0_IR_Bits.IR */
|
||||
#define IFX_FCE_IN0_IR_IR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN0_RES_Bits.RES */
|
||||
#define IFX_FCE_IN0_RES_RES_LEN (32u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN0_RES_Bits.RES */
|
||||
#define IFX_FCE_IN0_RES_RES_MSK (0xffffffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN0_RES_Bits.RES */
|
||||
#define IFX_FCE_IN0_RES_RES_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN1_CHECK_Bits.CHECK */
|
||||
#define IFX_FCE_IN1_CHECK_CHECK_LEN (32u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN1_CHECK_Bits.CHECK */
|
||||
#define IFX_FCE_IN1_CHECK_CHECK_MSK (0xffffffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN1_CHECK_Bits.CHECK */
|
||||
#define IFX_FCE_IN1_CHECK_CHECK_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN1_CRC_Bits.CRC */
|
||||
#define IFX_FCE_IN1_CRC_CRC_LEN (32u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN1_CRC_Bits.CRC */
|
||||
#define IFX_FCE_IN1_CRC_CRC_MSK (0xffffffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN1_CRC_Bits.CRC */
|
||||
#define IFX_FCE_IN1_CRC_CRC_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN1_IR_Bits.IR */
|
||||
#define IFX_FCE_IN1_IR_IR_LEN (32u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN1_IR_Bits.IR */
|
||||
#define IFX_FCE_IN1_IR_IR_MSK (0xffffffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN1_IR_Bits.IR */
|
||||
#define IFX_FCE_IN1_IR_IR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN1_RES_Bits.RES */
|
||||
#define IFX_FCE_IN1_RES_RES_LEN (32u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN1_RES_Bits.RES */
|
||||
#define IFX_FCE_IN1_RES_RES_MSK (0xffffffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN1_RES_Bits.RES */
|
||||
#define IFX_FCE_IN1_RES_RES_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN2_CHECK_Bits.CHECK */
|
||||
#define IFX_FCE_IN2_CHECK_CHECK_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN2_CHECK_Bits.CHECK */
|
||||
#define IFX_FCE_IN2_CHECK_CHECK_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN2_CHECK_Bits.CHECK */
|
||||
#define IFX_FCE_IN2_CHECK_CHECK_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN2_CRC_Bits.CRC */
|
||||
#define IFX_FCE_IN2_CRC_CRC_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN2_CRC_Bits.CRC */
|
||||
#define IFX_FCE_IN2_CRC_CRC_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN2_CRC_Bits.CRC */
|
||||
#define IFX_FCE_IN2_CRC_CRC_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN2_IR_Bits.IR */
|
||||
#define IFX_FCE_IN2_IR_IR_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN2_IR_Bits.IR */
|
||||
#define IFX_FCE_IN2_IR_IR_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN2_IR_Bits.IR */
|
||||
#define IFX_FCE_IN2_IR_IR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN2_RES_Bits.RES */
|
||||
#define IFX_FCE_IN2_RES_RES_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN2_RES_Bits.RES */
|
||||
#define IFX_FCE_IN2_RES_RES_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN2_RES_Bits.RES */
|
||||
#define IFX_FCE_IN2_RES_RES_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN3_CHECK_Bits.CHECK */
|
||||
#define IFX_FCE_IN3_CHECK_CHECK_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN3_CHECK_Bits.CHECK */
|
||||
#define IFX_FCE_IN3_CHECK_CHECK_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN3_CHECK_Bits.CHECK */
|
||||
#define IFX_FCE_IN3_CHECK_CHECK_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN3_CRC_Bits.CRC */
|
||||
#define IFX_FCE_IN3_CRC_CRC_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN3_CRC_Bits.CRC */
|
||||
#define IFX_FCE_IN3_CRC_CRC_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN3_CRC_Bits.CRC */
|
||||
#define IFX_FCE_IN3_CRC_CRC_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN3_IR_Bits.IR */
|
||||
#define IFX_FCE_IN3_IR_IR_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN3_IR_Bits.IR */
|
||||
#define IFX_FCE_IN3_IR_IR_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN3_IR_Bits.IR */
|
||||
#define IFX_FCE_IN3_IR_IR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_IN3_RES_Bits.RES */
|
||||
#define IFX_FCE_IN3_RES_RES_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_IN3_RES_Bits.RES */
|
||||
#define IFX_FCE_IN3_RES_RES_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_IN3_RES_Bits.RES */
|
||||
#define IFX_FCE_IN3_RES_RES_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_KRST0_Bits.RST */
|
||||
#define IFX_FCE_KRST0_RST_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_KRST0_Bits.RST */
|
||||
#define IFX_FCE_KRST0_RST_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_KRST0_Bits.RST */
|
||||
#define IFX_FCE_KRST0_RST_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_KRST0_Bits.RSTSTAT */
|
||||
#define IFX_FCE_KRST0_RSTSTAT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_KRST0_Bits.RSTSTAT */
|
||||
#define IFX_FCE_KRST0_RSTSTAT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_KRST0_Bits.RSTSTAT */
|
||||
#define IFX_FCE_KRST0_RSTSTAT_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_KRST1_Bits.RST */
|
||||
#define IFX_FCE_KRST1_RST_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_KRST1_Bits.RST */
|
||||
#define IFX_FCE_KRST1_RST_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_KRST1_Bits.RST */
|
||||
#define IFX_FCE_KRST1_RST_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_KRSTCLR_Bits.CLR */
|
||||
#define IFX_FCE_KRSTCLR_CLR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_KRSTCLR_Bits.CLR */
|
||||
#define IFX_FCE_KRSTCLR_CLR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_KRSTCLR_Bits.CLR */
|
||||
#define IFX_FCE_KRSTCLR_CLR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_LENGTH_Bits.LENGTH */
|
||||
#define IFX_FCE_LENGTH_LENGTH_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_LENGTH_Bits.LENGTH */
|
||||
#define IFX_FCE_LENGTH_LENGTH_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_LENGTH_Bits.LENGTH */
|
||||
#define IFX_FCE_LENGTH_LENGTH_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_STS_Bits.BEF */
|
||||
#define IFX_FCE_STS_BEF_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_STS_Bits.BEF */
|
||||
#define IFX_FCE_STS_BEF_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_STS_Bits.BEF */
|
||||
#define IFX_FCE_STS_BEF_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_STS_Bits.CEF */
|
||||
#define IFX_FCE_STS_CEF_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_STS_Bits.CEF */
|
||||
#define IFX_FCE_STS_CEF_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_STS_Bits.CEF */
|
||||
#define IFX_FCE_STS_CEF_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_STS_Bits.CMF */
|
||||
#define IFX_FCE_STS_CMF_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_STS_Bits.CMF */
|
||||
#define IFX_FCE_STS_CMF_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_STS_Bits.CMF */
|
||||
#define IFX_FCE_STS_CMF_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FCE_STS_Bits.LEF */
|
||||
#define IFX_FCE_STS_LEF_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FCE_STS_Bits.LEF */
|
||||
#define IFX_FCE_STS_LEF_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FCE_STS_Bits.LEF */
|
||||
#define IFX_FCE_STS_LEF_OFF (2u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXFCE_BF_H */
|
||||
@@ -1,363 +0,0 @@
|
||||
/**
|
||||
* \file IfxFce_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Fce_Cfg Fce address
|
||||
* \ingroup IfxLld_Fce
|
||||
*
|
||||
* \defgroup IfxLld_Fce_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Fce_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Fce_Cfg_Fce0 2-FCE0
|
||||
* \ingroup IfxLld_Fce_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXFCE_REG_H
|
||||
#define IFXFCE_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxFce_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Fce_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief FCE object */
|
||||
#define MODULE_FCE0 /*lint --e(923)*/ (*(Ifx_FCE*)0xF0003F00u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Fce_Cfg_Fce0
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define FCE0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_FCE_ACCEN0*)0xF0003FFCu)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_ACCEN0.
|
||||
* To use register names with standard convension, please use FCE0_ACCEN0.
|
||||
*/
|
||||
#define FCE_ACCEN0 (FCE0_ACCEN0)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define FCE0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_FCE_ACCEN1*)0xF0003FF8u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_ACCEN1.
|
||||
* To use register names with standard convension, please use FCE0_ACCEN1.
|
||||
*/
|
||||
#define FCE_ACCEN1 (FCE0_ACCEN1)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define FCE0_CLC /*lint --e(923)*/ (*(volatile Ifx_FCE_CLC*)0xF0003F00u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_CLC.
|
||||
* To use register names with standard convension, please use FCE0_CLC.
|
||||
*/
|
||||
#define FCE_CLC (FCE0_CLC)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define FCE0_ID /*lint --e(923)*/ (*(volatile Ifx_FCE_ID*)0xF0003F08u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_ID.
|
||||
* To use register names with standard convension, please use FCE0_ID.
|
||||
*/
|
||||
#define FCE_ID (FCE0_ID)
|
||||
|
||||
/** \brief 28, CRC Configuration Register */
|
||||
#define FCE0_IN0_CFG /*lint --e(923)*/ (*(volatile Ifx_FCE_CFG*)0xF0003F28u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN0_CFG.
|
||||
* To use register names with standard convension, please use FCE0_IN0_CFG.
|
||||
*/
|
||||
#define FCE_CFG0 (FCE0_IN0_CFG)
|
||||
|
||||
/** \brief 34, CRC Check Register */
|
||||
#define FCE0_IN0_CHECK /*lint --e(923)*/ (*(volatile Ifx_FCE_IN0_CHECK*)0xF0003F34u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN0_CHECK.
|
||||
* To use register names with standard convension, please use FCE0_IN0_CHECK.
|
||||
*/
|
||||
#define FCE_CHECK0 (FCE0_IN0_CHECK)
|
||||
|
||||
/** \brief 38, CRC Register */
|
||||
#define FCE0_IN0_CRC /*lint --e(923)*/ (*(volatile Ifx_FCE_IN0_CRC*)0xF0003F38u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN0_CRC.
|
||||
* To use register names with standard convension, please use FCE0_IN0_CRC.
|
||||
*/
|
||||
#define FCE_CRC0 (FCE0_IN0_CRC)
|
||||
|
||||
/** \brief 3C, CRC Test Register */
|
||||
#define FCE0_IN0_CTR /*lint --e(923)*/ (*(volatile Ifx_FCE_CTR*)0xF0003F3Cu)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN0_CTR.
|
||||
* To use register names with standard convension, please use FCE0_IN0_CTR.
|
||||
*/
|
||||
#define FCE_CTR0 (FCE0_IN0_CTR)
|
||||
|
||||
/** \brief 20, Input Register */
|
||||
#define FCE0_IN0_IR /*lint --e(923)*/ (*(volatile Ifx_FCE_IN0_IR*)0xF0003F20u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN0_IR.
|
||||
* To use register names with standard convension, please use FCE0_IN0_IR.
|
||||
*/
|
||||
#define FCE_IR0 (FCE0_IN0_IR)
|
||||
|
||||
/** \brief 30, CRC Length Register */
|
||||
#define FCE0_IN0_LENGTH /*lint --e(923)*/ (*(volatile Ifx_FCE_LENGTH*)0xF0003F30u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN0_LENGTH.
|
||||
* To use register names with standard convension, please use FCE0_IN0_LENGTH.
|
||||
*/
|
||||
#define FCE_LENGTH0 (FCE0_IN0_LENGTH)
|
||||
|
||||
/** \brief 24, CRC Result Register */
|
||||
#define FCE0_IN0_RES /*lint --e(923)*/ (*(volatile Ifx_FCE_IN0_RES*)0xF0003F24u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN0_RES.
|
||||
* To use register names with standard convension, please use FCE0_IN0_RES.
|
||||
*/
|
||||
#define FCE_RES0 (FCE0_IN0_RES)
|
||||
|
||||
/** \brief 2C, CRC Status Register */
|
||||
#define FCE0_IN0_STS /*lint --e(923)*/ (*(volatile Ifx_FCE_STS*)0xF0003F2Cu)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN0_STS.
|
||||
* To use register names with standard convension, please use FCE0_IN0_STS.
|
||||
*/
|
||||
#define FCE_STS0 (FCE0_IN0_STS)
|
||||
|
||||
/** \brief 48, CRC Configuration Register */
|
||||
#define FCE0_IN1_CFG /*lint --e(923)*/ (*(volatile Ifx_FCE_CFG*)0xF0003F48u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN1_CFG.
|
||||
* To use register names with standard convension, please use FCE0_IN1_CFG.
|
||||
*/
|
||||
#define FCE_CFG1 (FCE0_IN1_CFG)
|
||||
|
||||
/** \brief 54, CRC Check Register */
|
||||
#define FCE0_IN1_CHECK /*lint --e(923)*/ (*(volatile Ifx_FCE_IN1_CHECK*)0xF0003F54u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN1_CHECK.
|
||||
* To use register names with standard convension, please use FCE0_IN1_CHECK.
|
||||
*/
|
||||
#define FCE_CHECK1 (FCE0_IN1_CHECK)
|
||||
|
||||
/** \brief 58, CRC Register */
|
||||
#define FCE0_IN1_CRC /*lint --e(923)*/ (*(volatile Ifx_FCE_IN1_CRC*)0xF0003F58u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN1_CRC.
|
||||
* To use register names with standard convension, please use FCE0_IN1_CRC.
|
||||
*/
|
||||
#define FCE_CRC1 (FCE0_IN1_CRC)
|
||||
|
||||
/** \brief 5C, CRC Test Register */
|
||||
#define FCE0_IN1_CTR /*lint --e(923)*/ (*(volatile Ifx_FCE_CTR*)0xF0003F5Cu)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN1_CTR.
|
||||
* To use register names with standard convension, please use FCE0_IN1_CTR.
|
||||
*/
|
||||
#define FCE_CTR1 (FCE0_IN1_CTR)
|
||||
|
||||
/** \brief 40, Input Register */
|
||||
#define FCE0_IN1_IR /*lint --e(923)*/ (*(volatile Ifx_FCE_IN1_IR*)0xF0003F40u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN1_IR.
|
||||
* To use register names with standard convension, please use FCE0_IN1_IR.
|
||||
*/
|
||||
#define FCE_IR1 (FCE0_IN1_IR)
|
||||
|
||||
/** \brief 50, CRC Length Register */
|
||||
#define FCE0_IN1_LENGTH /*lint --e(923)*/ (*(volatile Ifx_FCE_LENGTH*)0xF0003F50u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN1_LENGTH.
|
||||
* To use register names with standard convension, please use FCE0_IN1_LENGTH.
|
||||
*/
|
||||
#define FCE_LENGTH1 (FCE0_IN1_LENGTH)
|
||||
|
||||
/** \brief 44, CRC Result Register */
|
||||
#define FCE0_IN1_RES /*lint --e(923)*/ (*(volatile Ifx_FCE_IN1_RES*)0xF0003F44u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN1_RES.
|
||||
* To use register names with standard convension, please use FCE0_IN1_RES.
|
||||
*/
|
||||
#define FCE_RES1 (FCE0_IN1_RES)
|
||||
|
||||
/** \brief 4C, CRC Status Register */
|
||||
#define FCE0_IN1_STS /*lint --e(923)*/ (*(volatile Ifx_FCE_STS*)0xF0003F4Cu)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN1_STS.
|
||||
* To use register names with standard convension, please use FCE0_IN1_STS.
|
||||
*/
|
||||
#define FCE_STS1 (FCE0_IN1_STS)
|
||||
|
||||
/** \brief 68, CRC Configuration Register */
|
||||
#define FCE0_IN2_CFG /*lint --e(923)*/ (*(volatile Ifx_FCE_CFG*)0xF0003F68u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN2_CFG.
|
||||
* To use register names with standard convension, please use FCE0_IN2_CFG.
|
||||
*/
|
||||
#define FCE_CFG2 (FCE0_IN2_CFG)
|
||||
|
||||
/** \brief 74, CRC Check Register */
|
||||
#define FCE0_IN2_CHECK /*lint --e(923)*/ (*(volatile Ifx_FCE_IN2_CHECK*)0xF0003F74u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN2_CHECK.
|
||||
* To use register names with standard convension, please use FCE0_IN2_CHECK.
|
||||
*/
|
||||
#define FCE_CHECK2 (FCE0_IN2_CHECK)
|
||||
|
||||
/** \brief 78, CRC Register */
|
||||
#define FCE0_IN2_CRC /*lint --e(923)*/ (*(volatile Ifx_FCE_IN2_CRC*)0xF0003F78u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN2_CRC.
|
||||
* To use register names with standard convension, please use FCE0_IN2_CRC.
|
||||
*/
|
||||
#define FCE_CRC2 (FCE0_IN2_CRC)
|
||||
|
||||
/** \brief 7C, CRC Test Register */
|
||||
#define FCE0_IN2_CTR /*lint --e(923)*/ (*(volatile Ifx_FCE_CTR*)0xF0003F7Cu)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN2_CTR.
|
||||
* To use register names with standard convension, please use FCE0_IN2_CTR.
|
||||
*/
|
||||
#define FCE_CTR2 (FCE0_IN2_CTR)
|
||||
|
||||
/** \brief 60, Input Register */
|
||||
#define FCE0_IN2_IR /*lint --e(923)*/ (*(volatile Ifx_FCE_IN2_IR*)0xF0003F60u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN2_IR.
|
||||
* To use register names with standard convension, please use FCE0_IN2_IR.
|
||||
*/
|
||||
#define FCE_IR2 (FCE0_IN2_IR)
|
||||
|
||||
/** \brief 70, CRC Length Register */
|
||||
#define FCE0_IN2_LENGTH /*lint --e(923)*/ (*(volatile Ifx_FCE_LENGTH*)0xF0003F70u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN2_LENGTH.
|
||||
* To use register names with standard convension, please use FCE0_IN2_LENGTH.
|
||||
*/
|
||||
#define FCE_LENGTH2 (FCE0_IN2_LENGTH)
|
||||
|
||||
/** \brief 64, CRC Result Register */
|
||||
#define FCE0_IN2_RES /*lint --e(923)*/ (*(volatile Ifx_FCE_IN2_RES*)0xF0003F64u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN2_RES.
|
||||
* To use register names with standard convension, please use FCE0_IN2_RES.
|
||||
*/
|
||||
#define FCE_RES2 (FCE0_IN2_RES)
|
||||
|
||||
/** \brief 6C, CRC Status Register */
|
||||
#define FCE0_IN2_STS /*lint --e(923)*/ (*(volatile Ifx_FCE_STS*)0xF0003F6Cu)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN2_STS.
|
||||
* To use register names with standard convension, please use FCE0_IN2_STS.
|
||||
*/
|
||||
#define FCE_STS2 (FCE0_IN2_STS)
|
||||
|
||||
/** \brief 88, CRC Configuration Register */
|
||||
#define FCE0_IN3_CFG /*lint --e(923)*/ (*(volatile Ifx_FCE_CFG*)0xF0003F88u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN3_CFG.
|
||||
* To use register names with standard convension, please use FCE0_IN3_CFG.
|
||||
*/
|
||||
#define FCE_CFG3 (FCE0_IN3_CFG)
|
||||
|
||||
/** \brief 94, CRC Check Register */
|
||||
#define FCE0_IN3_CHECK /*lint --e(923)*/ (*(volatile Ifx_FCE_IN3_CHECK*)0xF0003F94u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN3_CHECK.
|
||||
* To use register names with standard convension, please use FCE0_IN3_CHECK.
|
||||
*/
|
||||
#define FCE_CHECK3 (FCE0_IN3_CHECK)
|
||||
|
||||
/** \brief 98, CRC Register */
|
||||
#define FCE0_IN3_CRC /*lint --e(923)*/ (*(volatile Ifx_FCE_IN3_CRC*)0xF0003F98u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN3_CRC.
|
||||
* To use register names with standard convension, please use FCE0_IN3_CRC.
|
||||
*/
|
||||
#define FCE_CRC3 (FCE0_IN3_CRC)
|
||||
|
||||
/** \brief 9C, CRC Test Register */
|
||||
#define FCE0_IN3_CTR /*lint --e(923)*/ (*(volatile Ifx_FCE_CTR*)0xF0003F9Cu)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN3_CTR.
|
||||
* To use register names with standard convension, please use FCE0_IN3_CTR.
|
||||
*/
|
||||
#define FCE_CTR3 (FCE0_IN3_CTR)
|
||||
|
||||
/** \brief 80, Input Register */
|
||||
#define FCE0_IN3_IR /*lint --e(923)*/ (*(volatile Ifx_FCE_IN3_IR*)0xF0003F80u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN3_IR.
|
||||
* To use register names with standard convension, please use FCE0_IN3_IR.
|
||||
*/
|
||||
#define FCE_IR3 (FCE0_IN3_IR)
|
||||
|
||||
/** \brief 90, CRC Length Register */
|
||||
#define FCE0_IN3_LENGTH /*lint --e(923)*/ (*(volatile Ifx_FCE_LENGTH*)0xF0003F90u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN3_LENGTH.
|
||||
* To use register names with standard convension, please use FCE0_IN3_LENGTH.
|
||||
*/
|
||||
#define FCE_LENGTH3 (FCE0_IN3_LENGTH)
|
||||
|
||||
/** \brief 84, CRC Result Register */
|
||||
#define FCE0_IN3_RES /*lint --e(923)*/ (*(volatile Ifx_FCE_IN3_RES*)0xF0003F84u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN3_RES.
|
||||
* To use register names with standard convension, please use FCE0_IN3_RES.
|
||||
*/
|
||||
#define FCE_RES3 (FCE0_IN3_RES)
|
||||
|
||||
/** \brief 8C, CRC Status Register */
|
||||
#define FCE0_IN3_STS /*lint --e(923)*/ (*(volatile Ifx_FCE_STS*)0xF0003F8Cu)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_IN3_STS.
|
||||
* To use register names with standard convension, please use FCE0_IN3_STS.
|
||||
*/
|
||||
#define FCE_STS3 (FCE0_IN3_STS)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define FCE0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_FCE_KRST0*)0xF0003FF4u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_KRST0.
|
||||
* To use register names with standard convension, please use FCE0_KRST0.
|
||||
*/
|
||||
#define FCE_KRST0 (FCE0_KRST0)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define FCE0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_FCE_KRST1*)0xF0003FF0u)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_KRST1.
|
||||
* To use register names with standard convension, please use FCE0_KRST1.
|
||||
*/
|
||||
#define FCE_KRST1 (FCE0_KRST1)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define FCE0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_FCE_KRSTCLR*)0xF0003FECu)
|
||||
|
||||
/** Alias (User Manual Name) for FCE0_KRSTCLR.
|
||||
* To use register names with standard convension, please use FCE0_KRSTCLR.
|
||||
*/
|
||||
#define FCE_KRSTCLR (FCE0_KRSTCLR)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXFCE_REG_H */
|
||||
@@ -1,585 +0,0 @@
|
||||
/**
|
||||
* \file IfxFce_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Fce Fce
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Fce_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Fce
|
||||
*
|
||||
* \defgroup IfxLld_Fce_union Union
|
||||
* \ingroup IfxLld_Fce
|
||||
*
|
||||
* \defgroup IfxLld_Fce_struct Struct
|
||||
* \ingroup IfxLld_Fce
|
||||
*
|
||||
*/
|
||||
#ifndef IFXFCE_REGDEF_H
|
||||
#define IFXFCE_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Fce_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_FCE_ACCEN0_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_FCE_ACCEN0_Bits;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef struct _Ifx_FCE_ACCEN1_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_ACCEN1_Bits;
|
||||
|
||||
/** \brief CRC Configuration Register */
|
||||
typedef struct _Ifx_FCE_CFG_Bits
|
||||
{
|
||||
unsigned int CMI:1; /**< \brief [0:0] CRC Mismatch Interrupt (rw) */
|
||||
unsigned int CEI:1; /**< \brief [1:1] Configuration Error Interrupt (rw) */
|
||||
unsigned int LEI:1; /**< \brief [2:2] Length Error Interrupt (rw) */
|
||||
unsigned int BEI:1; /**< \brief [3:3] Bus Error Interrupt (rw) */
|
||||
unsigned int CCE:1; /**< \brief [4:4] CRC Check Comparison (rw) */
|
||||
unsigned int ALR:1; /**< \brief [5:5] Automatic Length Reload (rw) */
|
||||
unsigned int reserved_6:2; /**< \brief \internal Reserved */
|
||||
unsigned int REFIN:1; /**< \brief [8:8] IR Byte Wise Reflection (rw) */
|
||||
unsigned int REFOUT:1; /**< \brief [9:9] CRC 32-Bit Wise Reflection (rw) */
|
||||
unsigned int XSEL:1; /**< \brief [10:10] Selects the value to be xored with the final CRC (rw) */
|
||||
unsigned int reserved_11:21; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_CFG_Bits;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef struct _Ifx_FCE_CLC_Bits
|
||||
{
|
||||
unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_CLC_Bits;
|
||||
|
||||
/** \brief CRC Test Register */
|
||||
typedef struct _Ifx_FCE_CTR_Bits
|
||||
{
|
||||
unsigned int FCM:1; /**< \brief [0:0] Force CRC Mismatch (rw) */
|
||||
unsigned int FRM_CFG:1; /**< \brief [1:1] Force CFG Register Mismatch (rw) */
|
||||
unsigned int FRM_CHECK:1; /**< \brief [2:2] Force Check Register Mismatch (rw) */
|
||||
unsigned int reserved_3:29; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_CTR_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_FCE_ID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_FCE_ID_Bits;
|
||||
|
||||
/** \brief CRC Check Register */
|
||||
typedef struct _Ifx_FCE_IN0_CHECK_Bits
|
||||
{
|
||||
unsigned int CHECK:32; /**< \brief [31:0] CHECK Register (rw) */
|
||||
} Ifx_FCE_IN0_CHECK_Bits;
|
||||
|
||||
/** \brief CRC Register */
|
||||
typedef struct _Ifx_FCE_IN0_CRC_Bits
|
||||
{
|
||||
unsigned int CRC:32; /**< \brief [31:0] CRC Register (rwh) */
|
||||
} Ifx_FCE_IN0_CRC_Bits;
|
||||
|
||||
/** \brief Input Register */
|
||||
typedef struct _Ifx_FCE_IN0_IR_Bits
|
||||
{
|
||||
unsigned int IR:32; /**< \brief [31:0] Input Register (rw) */
|
||||
} Ifx_FCE_IN0_IR_Bits;
|
||||
|
||||
/** \brief CRC Result Register */
|
||||
typedef struct _Ifx_FCE_IN0_RES_Bits
|
||||
{
|
||||
unsigned int RES:32; /**< \brief [31:0] Result Register (rh) */
|
||||
} Ifx_FCE_IN0_RES_Bits;
|
||||
|
||||
/** \brief CRC Check Register */
|
||||
typedef struct _Ifx_FCE_IN1_CHECK_Bits
|
||||
{
|
||||
unsigned int CHECK:32; /**< \brief [31:0] CHECK Register (rw) */
|
||||
} Ifx_FCE_IN1_CHECK_Bits;
|
||||
|
||||
/** \brief CRC Register */
|
||||
typedef struct _Ifx_FCE_IN1_CRC_Bits
|
||||
{
|
||||
unsigned int CRC:32; /**< \brief [31:0] CRC Register (rwh) */
|
||||
} Ifx_FCE_IN1_CRC_Bits;
|
||||
|
||||
/** \brief Input Register */
|
||||
typedef struct _Ifx_FCE_IN1_IR_Bits
|
||||
{
|
||||
unsigned int IR:32; /**< \brief [31:0] Input Register (rw) */
|
||||
} Ifx_FCE_IN1_IR_Bits;
|
||||
|
||||
/** \brief CRC Result Register */
|
||||
typedef struct _Ifx_FCE_IN1_RES_Bits
|
||||
{
|
||||
unsigned int RES:32; /**< \brief [31:0] Result Register (rh) */
|
||||
} Ifx_FCE_IN1_RES_Bits;
|
||||
|
||||
/** \brief CRC Check Register */
|
||||
typedef struct _Ifx_FCE_IN2_CHECK_Bits
|
||||
{
|
||||
unsigned int CHECK:16; /**< \brief [15:0] CHECK Register (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_IN2_CHECK_Bits;
|
||||
|
||||
/** \brief CRC Register */
|
||||
typedef struct _Ifx_FCE_IN2_CRC_Bits
|
||||
{
|
||||
unsigned int CRC:16; /**< \brief [15:0] CRC Register (rwh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_IN2_CRC_Bits;
|
||||
|
||||
/** \brief Input Register */
|
||||
typedef struct _Ifx_FCE_IN2_IR_Bits
|
||||
{
|
||||
unsigned int IR:16; /**< \brief [15:0] Input Register (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_IN2_IR_Bits;
|
||||
|
||||
/** \brief CRC Result Register */
|
||||
typedef struct _Ifx_FCE_IN2_RES_Bits
|
||||
{
|
||||
unsigned int RES:16; /**< \brief [15:0] Result Register (rh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_IN2_RES_Bits;
|
||||
|
||||
/** \brief CRC Check Register */
|
||||
typedef struct _Ifx_FCE_IN3_CHECK_Bits
|
||||
{
|
||||
unsigned int CHECK:8; /**< \brief [7:0] CHECK Register (rw) */
|
||||
unsigned int reserved_8:24; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_IN3_CHECK_Bits;
|
||||
|
||||
/** \brief CRC Register */
|
||||
typedef struct _Ifx_FCE_IN3_CRC_Bits
|
||||
{
|
||||
unsigned int CRC:8; /**< \brief [7:0] CRC Register (rwh) */
|
||||
unsigned int reserved_8:24; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_IN3_CRC_Bits;
|
||||
|
||||
/** \brief Input Register */
|
||||
typedef struct _Ifx_FCE_IN3_IR_Bits
|
||||
{
|
||||
unsigned int IR:8; /**< \brief [7:0] Input Register (rw) */
|
||||
unsigned int reserved_8:24; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_IN3_IR_Bits;
|
||||
|
||||
/** \brief CRC Result Register */
|
||||
typedef struct _Ifx_FCE_IN3_RES_Bits
|
||||
{
|
||||
unsigned int RES:8; /**< \brief [7:0] Result Register (rh) */
|
||||
unsigned int reserved_8:24; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_IN3_RES_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef struct _Ifx_FCE_KRST0_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rw) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_KRST0_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef struct _Ifx_FCE_KRST1_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_KRST1_Bits;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef struct _Ifx_FCE_KRSTCLR_Bits
|
||||
{
|
||||
unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_KRSTCLR_Bits;
|
||||
|
||||
/** \brief CRC Length Register */
|
||||
typedef struct _Ifx_FCE_LENGTH_Bits
|
||||
{
|
||||
unsigned int LENGTH:16; /**< \brief [15:0] Message Length Register (rwh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_LENGTH_Bits;
|
||||
|
||||
/** \brief CRC Status Register */
|
||||
typedef struct _Ifx_FCE_STS_Bits
|
||||
{
|
||||
unsigned int CMF:1; /**< \brief [0:0] CRC Mismatch Flag (rwh) */
|
||||
unsigned int CEF:1; /**< \brief [1:1] Configuration Error Flag (rwh) */
|
||||
unsigned int LEF:1; /**< \brief [2:2] Length Error Flag (rwh) */
|
||||
unsigned int BEF:1; /**< \brief [3:3] Bus Error Flag (rwh) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_FCE_STS_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Fce_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_ACCEN0;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_ACCEN1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_ACCEN1;
|
||||
|
||||
/** \brief CRC Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_CFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_CFG;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_CLC;
|
||||
|
||||
/** \brief CRC Test Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_CTR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_CTR;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_ID;
|
||||
|
||||
/** \brief CRC Check Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN0_CHECK_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN0_CHECK;
|
||||
|
||||
/** \brief CRC Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN0_CRC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN0_CRC;
|
||||
|
||||
/** \brief Input Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN0_IR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN0_IR;
|
||||
|
||||
/** \brief CRC Result Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN0_RES_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN0_RES;
|
||||
|
||||
/** \brief CRC Check Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN1_CHECK_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN1_CHECK;
|
||||
|
||||
/** \brief CRC Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN1_CRC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN1_CRC;
|
||||
|
||||
/** \brief Input Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN1_IR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN1_IR;
|
||||
|
||||
/** \brief CRC Result Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN1_RES_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN1_RES;
|
||||
|
||||
/** \brief CRC Check Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN2_CHECK_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN2_CHECK;
|
||||
|
||||
/** \brief CRC Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN2_CRC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN2_CRC;
|
||||
|
||||
/** \brief Input Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN2_IR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN2_IR;
|
||||
|
||||
/** \brief CRC Result Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN2_RES_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN2_RES;
|
||||
|
||||
/** \brief CRC Check Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN3_CHECK_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN3_CHECK;
|
||||
|
||||
/** \brief CRC Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN3_CRC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN3_CRC;
|
||||
|
||||
/** \brief Input Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN3_IR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN3_IR;
|
||||
|
||||
/** \brief CRC Result Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_IN3_RES_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_IN3_RES;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_KRST0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_KRST0;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_KRST1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_KRST1;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_KRSTCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_KRSTCLR;
|
||||
|
||||
/** \brief CRC Length Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_LENGTH_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_LENGTH;
|
||||
|
||||
/** \brief CRC Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FCE_STS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FCE_STS;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Fce_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L1
|
||||
* \{ */
|
||||
|
||||
/** \brief Input */
|
||||
typedef volatile struct _Ifx_FCE_IN0
|
||||
{
|
||||
Ifx_FCE_IN0_IR IR; /**< \brief 0, Input Register */
|
||||
Ifx_FCE_IN0_RES RES; /**< \brief 4, CRC Result Register */
|
||||
Ifx_FCE_CFG CFG; /**< \brief 8, CRC Configuration Register */
|
||||
Ifx_FCE_STS STS; /**< \brief C, CRC Status Register */
|
||||
Ifx_FCE_LENGTH LENGTH; /**< \brief 10, CRC Length Register */
|
||||
Ifx_FCE_IN0_CHECK CHECK; /**< \brief 14, CRC Check Register */
|
||||
Ifx_FCE_IN0_CRC CRC; /**< \brief 18, CRC Register */
|
||||
Ifx_FCE_CTR CTR; /**< \brief 1C, CRC Test Register */
|
||||
} Ifx_FCE_IN0;
|
||||
|
||||
/** \brief Input */
|
||||
typedef volatile struct _Ifx_FCE_IN1
|
||||
{
|
||||
Ifx_FCE_IN1_IR IR; /**< \brief 0, Input Register */
|
||||
Ifx_FCE_IN1_RES RES; /**< \brief 4, CRC Result Register */
|
||||
Ifx_FCE_CFG CFG; /**< \brief 8, CRC Configuration Register */
|
||||
Ifx_FCE_STS STS; /**< \brief C, CRC Status Register */
|
||||
Ifx_FCE_LENGTH LENGTH; /**< \brief 10, CRC Length Register */
|
||||
Ifx_FCE_IN1_CHECK CHECK; /**< \brief 14, CRC Check Register */
|
||||
Ifx_FCE_IN1_CRC CRC; /**< \brief 18, CRC Register */
|
||||
Ifx_FCE_CTR CTR; /**< \brief 1C, CRC Test Register */
|
||||
} Ifx_FCE_IN1;
|
||||
|
||||
/** \brief Input */
|
||||
typedef volatile struct _Ifx_FCE_IN2
|
||||
{
|
||||
Ifx_FCE_IN2_IR IR; /**< \brief 0, Input Register */
|
||||
Ifx_FCE_IN2_RES RES; /**< \brief 4, CRC Result Register */
|
||||
Ifx_FCE_CFG CFG; /**< \brief 8, CRC Configuration Register */
|
||||
Ifx_FCE_STS STS; /**< \brief C, CRC Status Register */
|
||||
Ifx_FCE_LENGTH LENGTH; /**< \brief 10, CRC Length Register */
|
||||
Ifx_FCE_IN2_CHECK CHECK; /**< \brief 14, CRC Check Register */
|
||||
Ifx_FCE_IN2_CRC CRC; /**< \brief 18, CRC Register */
|
||||
Ifx_FCE_CTR CTR; /**< \brief 1C, CRC Test Register */
|
||||
} Ifx_FCE_IN2;
|
||||
|
||||
/** \brief Input */
|
||||
typedef volatile struct _Ifx_FCE_IN3
|
||||
{
|
||||
Ifx_FCE_IN3_IR IR; /**< \brief 0, Input Register */
|
||||
Ifx_FCE_IN3_RES RES; /**< \brief 4, CRC Result Register */
|
||||
Ifx_FCE_CFG CFG; /**< \brief 8, CRC Configuration Register */
|
||||
Ifx_FCE_STS STS; /**< \brief C, CRC Status Register */
|
||||
Ifx_FCE_LENGTH LENGTH; /**< \brief 10, CRC Length Register */
|
||||
Ifx_FCE_IN3_CHECK CHECK; /**< \brief 14, CRC Check Register */
|
||||
Ifx_FCE_IN3_CRC CRC; /**< \brief 18, CRC Register */
|
||||
Ifx_FCE_CTR CTR; /**< \brief 1C, CRC Test Register */
|
||||
} Ifx_FCE_IN3;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Fce_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief FCE object */
|
||||
typedef volatile struct _Ifx_FCE
|
||||
{
|
||||
Ifx_FCE_CLC CLC; /**< \brief 0, Clock Control Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_FCE_ID ID; /**< \brief 8, Module Identification Register */
|
||||
unsigned char reserved_C[20]; /**< \brief C, \internal Reserved */
|
||||
Ifx_FCE_IN0 IN0; /**< \brief 20, Input */
|
||||
Ifx_FCE_IN1 IN1; /**< \brief 40, Input */
|
||||
Ifx_FCE_IN2 IN2; /**< \brief 60, Input */
|
||||
Ifx_FCE_IN3 IN3; /**< \brief 80, Input */
|
||||
unsigned char reserved_A0[76]; /**< \brief A0, \internal Reserved */
|
||||
Ifx_FCE_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
|
||||
Ifx_FCE_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
|
||||
Ifx_FCE_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
|
||||
Ifx_FCE_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
|
||||
Ifx_FCE_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
|
||||
} Ifx_FCE;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXFCE_REGDEF_H */
|
||||
@@ -1,360 +0,0 @@
|
||||
/**
|
||||
* \file IfxFft_bf.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Fft_BitfieldsMask Bitfields mask and offset
|
||||
* \ingroup IfxLld_Fft
|
||||
*
|
||||
*/
|
||||
#ifndef IFXFFT_BF_H
|
||||
#define IFXFFT_BF_H 1
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Fft_BitfieldsMask
|
||||
* \{ */
|
||||
|
||||
/** \brief Length for Ifx_FFT_CLC_Bits.DISR */
|
||||
#define IFX_FFT_CLC_DISR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_CLC_Bits.DISR */
|
||||
#define IFX_FFT_CLC_DISR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_CLC_Bits.DISR */
|
||||
#define IFX_FFT_CLC_DISR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_CLC_Bits.DISS */
|
||||
#define IFX_FFT_CLC_DISS_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_CLC_Bits.DISS */
|
||||
#define IFX_FFT_CLC_DISS_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_CLC_Bits.DISS */
|
||||
#define IFX_FFT_CLC_DISS_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_CSR_Bits.BUSY */
|
||||
#define IFX_FFT_CSR_BUSY_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_CSR_Bits.BUSY */
|
||||
#define IFX_FFT_CSR_BUSY_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_CSR_Bits.BUSY */
|
||||
#define IFX_FFT_CSR_BUSY_OFF (19u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_CSR_Bits.IFFT */
|
||||
#define IFX_FFT_CSR_IFFT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_CSR_Bits.IFFT */
|
||||
#define IFX_FFT_CSR_IFFT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_CSR_Bits.IFFT */
|
||||
#define IFX_FFT_CSR_IFFT_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_CSR_Bits.IN_FMT */
|
||||
#define IFX_FFT_CSR_IN_FMT_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_CSR_Bits.IN_FMT */
|
||||
#define IFX_FFT_CSR_IN_FMT_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_CSR_Bits.IN_FMT */
|
||||
#define IFX_FFT_CSR_IN_FMT_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_CSR_Bits.LENGTH */
|
||||
#define IFX_FFT_CSR_LENGTH_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_CSR_Bits.LENGTH */
|
||||
#define IFX_FFT_CSR_LENGTH_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_CSR_Bits.LENGTH */
|
||||
#define IFX_FFT_CSR_LENGTH_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_CSR_Bits.OUT_FMT */
|
||||
#define IFX_FFT_CSR_OUT_FMT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_CSR_Bits.OUT_FMT */
|
||||
#define IFX_FFT_CSR_OUT_FMT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_CSR_Bits.OUT_FMT */
|
||||
#define IFX_FFT_CSR_OUT_FMT_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_CSR_Bits.RFS */
|
||||
#define IFX_FFT_CSR_RFS_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_CSR_Bits.RFS */
|
||||
#define IFX_FFT_CSR_RFS_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_CSR_Bits.RFS */
|
||||
#define IFX_FFT_CSR_RFS_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_CSR_Bits.START */
|
||||
#define IFX_FFT_CSR_START_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_CSR_Bits.START */
|
||||
#define IFX_FFT_CSR_START_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_CSR_Bits.START */
|
||||
#define IFX_FFT_CSR_START_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_CSR_Bits.WIN_BYP */
|
||||
#define IFX_FFT_CSR_WIN_BYP_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_CSR_Bits.WIN_BYP */
|
||||
#define IFX_FFT_CSR_WIN_BYP_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_CSR_Bits.WIN_BYP */
|
||||
#define IFX_FFT_CSR_WIN_BYP_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_HISTORY0_Bits.BUSY */
|
||||
#define IFX_FFT_HISTORY0_BUSY_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_HISTORY0_Bits.BUSY */
|
||||
#define IFX_FFT_HISTORY0_BUSY_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_HISTORY0_Bits.BUSY */
|
||||
#define IFX_FFT_HISTORY0_BUSY_OFF (19u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_HISTORY0_Bits.IFFT */
|
||||
#define IFX_FFT_HISTORY0_IFFT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_HISTORY0_Bits.IFFT */
|
||||
#define IFX_FFT_HISTORY0_IFFT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_HISTORY0_Bits.IFFT */
|
||||
#define IFX_FFT_HISTORY0_IFFT_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_HISTORY0_Bits.IN_FMT */
|
||||
#define IFX_FFT_HISTORY0_IN_FMT_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_HISTORY0_Bits.IN_FMT */
|
||||
#define IFX_FFT_HISTORY0_IN_FMT_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_HISTORY0_Bits.IN_FMT */
|
||||
#define IFX_FFT_HISTORY0_IN_FMT_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_HISTORY0_Bits.LENGTH */
|
||||
#define IFX_FFT_HISTORY0_LENGTH_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_HISTORY0_Bits.LENGTH */
|
||||
#define IFX_FFT_HISTORY0_LENGTH_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_HISTORY0_Bits.LENGTH */
|
||||
#define IFX_FFT_HISTORY0_LENGTH_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_HISTORY0_Bits.OUT_FMT */
|
||||
#define IFX_FFT_HISTORY0_OUT_FMT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_HISTORY0_Bits.OUT_FMT */
|
||||
#define IFX_FFT_HISTORY0_OUT_FMT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_HISTORY0_Bits.OUT_FMT */
|
||||
#define IFX_FFT_HISTORY0_OUT_FMT_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_HISTORY0_Bits.RFS */
|
||||
#define IFX_FFT_HISTORY0_RFS_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_HISTORY0_Bits.RFS */
|
||||
#define IFX_FFT_HISTORY0_RFS_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_HISTORY0_Bits.RFS */
|
||||
#define IFX_FFT_HISTORY0_RFS_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_HISTORY0_Bits.WIN_BYP */
|
||||
#define IFX_FFT_HISTORY0_WIN_BYP_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_HISTORY0_Bits.WIN_BYP */
|
||||
#define IFX_FFT_HISTORY0_WIN_BYP_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_HISTORY0_Bits.WIN_BYP */
|
||||
#define IFX_FFT_HISTORY0_WIN_BYP_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_HISTORY1_Bits.BUSY */
|
||||
#define IFX_FFT_HISTORY1_BUSY_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_HISTORY1_Bits.BUSY */
|
||||
#define IFX_FFT_HISTORY1_BUSY_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_HISTORY1_Bits.BUSY */
|
||||
#define IFX_FFT_HISTORY1_BUSY_OFF (19u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_HISTORY1_Bits.IFFT */
|
||||
#define IFX_FFT_HISTORY1_IFFT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_HISTORY1_Bits.IFFT */
|
||||
#define IFX_FFT_HISTORY1_IFFT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_HISTORY1_Bits.IFFT */
|
||||
#define IFX_FFT_HISTORY1_IFFT_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_HISTORY1_Bits.IN_FMT */
|
||||
#define IFX_FFT_HISTORY1_IN_FMT_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_HISTORY1_Bits.IN_FMT */
|
||||
#define IFX_FFT_HISTORY1_IN_FMT_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_HISTORY1_Bits.IN_FMT */
|
||||
#define IFX_FFT_HISTORY1_IN_FMT_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_HISTORY1_Bits.LENGTH */
|
||||
#define IFX_FFT_HISTORY1_LENGTH_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_HISTORY1_Bits.LENGTH */
|
||||
#define IFX_FFT_HISTORY1_LENGTH_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_HISTORY1_Bits.LENGTH */
|
||||
#define IFX_FFT_HISTORY1_LENGTH_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_HISTORY1_Bits.OUT_FMT */
|
||||
#define IFX_FFT_HISTORY1_OUT_FMT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_HISTORY1_Bits.OUT_FMT */
|
||||
#define IFX_FFT_HISTORY1_OUT_FMT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_HISTORY1_Bits.OUT_FMT */
|
||||
#define IFX_FFT_HISTORY1_OUT_FMT_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_HISTORY1_Bits.RFS */
|
||||
#define IFX_FFT_HISTORY1_RFS_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_HISTORY1_Bits.RFS */
|
||||
#define IFX_FFT_HISTORY1_RFS_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_HISTORY1_Bits.RFS */
|
||||
#define IFX_FFT_HISTORY1_RFS_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_HISTORY1_Bits.WIN_BYP */
|
||||
#define IFX_FFT_HISTORY1_WIN_BYP_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_HISTORY1_Bits.WIN_BYP */
|
||||
#define IFX_FFT_HISTORY1_WIN_BYP_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_HISTORY1_Bits.WIN_BYP */
|
||||
#define IFX_FFT_HISTORY1_WIN_BYP_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_ID_Bits.MODNUMBER */
|
||||
#define IFX_FFT_ID_MODNUMBER_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_ID_Bits.MODNUMBER */
|
||||
#define IFX_FFT_ID_MODNUMBER_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_ID_Bits.MODNUMBER */
|
||||
#define IFX_FFT_ID_MODNUMBER_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_ID_Bits.MODREV */
|
||||
#define IFX_FFT_ID_MODREV_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_ID_Bits.MODREV */
|
||||
#define IFX_FFT_ID_MODREV_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_ID_Bits.MODREV */
|
||||
#define IFX_FFT_ID_MODREV_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_ID_Bits.MODTYPE */
|
||||
#define IFX_FFT_ID_MODTYPE_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_ID_Bits.MODTYPE */
|
||||
#define IFX_FFT_ID_MODTYPE_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_ID_Bits.MODTYPE */
|
||||
#define IFX_FFT_ID_MODTYPE_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_KRST0_Bits.RST */
|
||||
#define IFX_FFT_KRST0_RST_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_KRST0_Bits.RST */
|
||||
#define IFX_FFT_KRST0_RST_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_KRST0_Bits.RST */
|
||||
#define IFX_FFT_KRST0_RST_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_KRST0_Bits.RSTSTAT */
|
||||
#define IFX_FFT_KRST0_RSTSTAT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_KRST0_Bits.RSTSTAT */
|
||||
#define IFX_FFT_KRST0_RSTSTAT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_KRST0_Bits.RSTSTAT */
|
||||
#define IFX_FFT_KRST0_RSTSTAT_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_KRST1_Bits.RST */
|
||||
#define IFX_FFT_KRST1_RST_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_KRST1_Bits.RST */
|
||||
#define IFX_FFT_KRST1_RST_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_KRST1_Bits.RST */
|
||||
#define IFX_FFT_KRST1_RST_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_KRSTCLR_Bits.CLR */
|
||||
#define IFX_FFT_KRSTCLR_CLR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_KRSTCLR_Bits.CLR */
|
||||
#define IFX_FFT_KRSTCLR_CLR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_KRSTCLR_Bits.CLR */
|
||||
#define IFX_FFT_KRSTCLR_CLR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_OCS_Bits.SUS */
|
||||
#define IFX_FFT_OCS_SUS_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_OCS_Bits.SUS */
|
||||
#define IFX_FFT_OCS_SUS_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_OCS_Bits.SUS */
|
||||
#define IFX_FFT_OCS_SUS_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_OCS_Bits.SUS_P */
|
||||
#define IFX_FFT_OCS_SUS_P_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_OCS_Bits.SUS_P */
|
||||
#define IFX_FFT_OCS_SUS_P_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_OCS_Bits.SUS_P */
|
||||
#define IFX_FFT_OCS_SUS_P_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_OCS_Bits.SUSSTA */
|
||||
#define IFX_FFT_OCS_SUSSTA_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_OCS_Bits.SUSSTA */
|
||||
#define IFX_FFT_OCS_SUSSTA_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_OCS_Bits.SUSSTA */
|
||||
#define IFX_FFT_OCS_SUSSTA_OFF (29u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_ODA_Bits.DDREN */
|
||||
#define IFX_FFT_ODA_DDREN_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_ODA_Bits.DDREN */
|
||||
#define IFX_FFT_ODA_DDREN_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_ODA_Bits.DDREN */
|
||||
#define IFX_FFT_ODA_DDREN_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_FFT_ODA_Bits.DRDIS */
|
||||
#define IFX_FFT_ODA_DRDIS_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_FFT_ODA_Bits.DRDIS */
|
||||
#define IFX_FFT_ODA_DRDIS_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_FFT_ODA_Bits.DRDIS */
|
||||
#define IFX_FFT_ODA_DRDIS_OFF (1u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXFFT_BF_H */
|
||||
@@ -1,81 +0,0 @@
|
||||
/**
|
||||
* \file IfxFft_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Fft_Cfg Fft address
|
||||
* \ingroup IfxLld_Fft
|
||||
*
|
||||
* \defgroup IfxLld_Fft_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Fft_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Fft_Cfg_Fft 2-FFT
|
||||
* \ingroup IfxLld_Fft_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXFFT_REG_H
|
||||
#define IFXFFT_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxFft_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Fft_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief FFT object */
|
||||
#define MODULE_FFT /*lint --e(923)*/ (*(Ifx_FFT*)0xF8700C00u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Fft_Cfg_Fft
|
||||
* \{ */
|
||||
|
||||
/** \brief 0, FFT Clock Control Register */
|
||||
#define FFT_CLC /*lint --e(923)*/ (*(volatile Ifx_FFT_CLC*)0xF8700C00u)
|
||||
|
||||
/** \brief 40, FFT Control and Status Register */
|
||||
#define FFT_CSR /*lint --e(923)*/ (*(volatile Ifx_FFT_CSR*)0xF8700C40u)
|
||||
|
||||
/** \brief 60, FFT History0 Register */
|
||||
#define FFT_HISTORY0 /*lint --e(923)*/ (*(volatile Ifx_FFT_HISTORY0*)0xF8700C60u)
|
||||
|
||||
/** \brief 70, FFT History1 Register */
|
||||
#define FFT_HISTORY1 /*lint --e(923)*/ (*(volatile Ifx_FFT_HISTORY1*)0xF8700C70u)
|
||||
|
||||
/** \brief 8, FFT Identification Register */
|
||||
#define FFT_ID /*lint --e(923)*/ (*(volatile Ifx_FFT_ID*)0xF8700C08u)
|
||||
|
||||
/** \brief F4, FFT Kernel Reset Register 0 */
|
||||
#define FFT_KRST0 /*lint --e(923)*/ (*(volatile Ifx_FFT_KRST0*)0xF8700CF4u)
|
||||
|
||||
/** \brief F0, FFT Kernel Reset Register 1 */
|
||||
#define FFT_KRST1 /*lint --e(923)*/ (*(volatile Ifx_FFT_KRST1*)0xF8700CF0u)
|
||||
|
||||
/** \brief EC, FFT Kernel Reset Status Clear Register */
|
||||
#define FFT_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_FFT_KRSTCLR*)0xF8700CECu)
|
||||
|
||||
/** \brief E8, FFT OCDS Control and Status */
|
||||
#define FFT_OCS /*lint --e(923)*/ (*(volatile Ifx_FFT_OCS*)0xF8700CE8u)
|
||||
|
||||
/** \brief E4, FFT OCDS Debug Access Register */
|
||||
#define FFT_ODA /*lint --e(923)*/ (*(volatile Ifx_FFT_ODA*)0xF8700CE4u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXFFT_REG_H */
|
||||
@@ -1,264 +0,0 @@
|
||||
/**
|
||||
* \file IfxFft_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Fft Fft
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Fft_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Fft
|
||||
*
|
||||
* \defgroup IfxLld_Fft_union Union
|
||||
* \ingroup IfxLld_Fft
|
||||
*
|
||||
* \defgroup IfxLld_Fft_struct Struct
|
||||
* \ingroup IfxLld_Fft
|
||||
*
|
||||
*/
|
||||
#ifndef IFXFFT_REGDEF_H
|
||||
#define IFXFFT_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Fft_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief FFT Clock Control Register */
|
||||
typedef struct _Ifx_FFT_CLC_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit DISR:1; /**< \brief [0:0] FFT Disable Request Bit (rw) */
|
||||
Ifx_Strict_32Bit DISS:1; /**< \brief [1:1] FFT Disable Status Bit (rh) */
|
||||
Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_FFT_CLC_Bits;
|
||||
|
||||
/** \brief FFT Control and Status Register */
|
||||
typedef struct _Ifx_FFT_CSR_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit START:1; /**< \brief [0:0] Start Transform (rwh) */
|
||||
Ifx_Strict_32Bit reserved_1:7; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit LENGTH:4; /**< \brief [11:8] Length of Transform (rw) */
|
||||
Ifx_Strict_32Bit IFFT:1; /**< \brief [12:12] Inverse FFT (rw) */
|
||||
Ifx_Strict_32Bit WIN_BYP:1; /**< \brief [13:13] Window Bypass (rw) */
|
||||
Ifx_Strict_32Bit reserved_14:2; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit IN_FMT:2; /**< \brief [17:16] Input Format (rw) */
|
||||
Ifx_Strict_32Bit OUT_FMT:1; /**< \brief [18:18] Output Format (rw) */
|
||||
Ifx_Strict_32Bit BUSY:1; /**< \brief [19:19] FFT Engine Busy (rh) */
|
||||
Ifx_Strict_32Bit RFS:1; /**< \brief [20:20] Ready For Start (rh) */
|
||||
Ifx_Strict_32Bit reserved_21:11; /**< \brief \internal Reserved */
|
||||
} Ifx_FFT_CSR_Bits;
|
||||
|
||||
/** \brief FFT History0 Register */
|
||||
typedef struct _Ifx_FFT_HISTORY0_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit reserved_0:8; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit LENGTH:4; /**< \brief [11:8] Length of Transform (rh) */
|
||||
Ifx_Strict_32Bit IFFT:1; /**< \brief [12:12] Inverse FFT (rh) */
|
||||
Ifx_Strict_32Bit WIN_BYP:1; /**< \brief [13:13] Window Bypass (rh) */
|
||||
Ifx_Strict_32Bit reserved_14:2; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit IN_FMT:2; /**< \brief [17:16] Input Format (rh) */
|
||||
Ifx_Strict_32Bit OUT_FMT:1; /**< \brief [18:18] Output Format (rh) */
|
||||
Ifx_Strict_32Bit BUSY:1; /**< \brief [19:19] FFT Engine Busy (rh) */
|
||||
Ifx_Strict_32Bit RFS:1; /**< \brief [20:20] Ready For Start (rh) */
|
||||
Ifx_Strict_32Bit reserved_21:11; /**< \brief \internal Reserved */
|
||||
} Ifx_FFT_HISTORY0_Bits;
|
||||
|
||||
/** \brief FFT History1 Register */
|
||||
typedef struct _Ifx_FFT_HISTORY1_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit reserved_0:8; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit LENGTH:4; /**< \brief [11:8] Length of Transform (rh) */
|
||||
Ifx_Strict_32Bit IFFT:1; /**< \brief [12:12] Inverse FFT (rh) */
|
||||
Ifx_Strict_32Bit WIN_BYP:1; /**< \brief [13:13] Window Bypass (rh) */
|
||||
Ifx_Strict_32Bit reserved_14:2; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit IN_FMT:2; /**< \brief [17:16] Input Format (rh) */
|
||||
Ifx_Strict_32Bit OUT_FMT:1; /**< \brief [18:18] Output Format (rh) */
|
||||
Ifx_Strict_32Bit BUSY:1; /**< \brief [19:19] FFT Engine Busy (rh) */
|
||||
Ifx_Strict_32Bit RFS:1; /**< \brief [20:20] Ready For Start (rh) */
|
||||
Ifx_Strict_32Bit reserved_21:11; /**< \brief \internal Reserved */
|
||||
} Ifx_FFT_HISTORY1_Bits;
|
||||
|
||||
/** \brief FFT Identification Register */
|
||||
typedef struct _Ifx_FFT_ID_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
Ifx_Strict_32Bit MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
Ifx_Strict_32Bit MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_FFT_ID_Bits;
|
||||
|
||||
/** \brief FFT Kernel Reset Register 0 */
|
||||
typedef struct _Ifx_FFT_KRST0_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
Ifx_Strict_32Bit RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
|
||||
Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_FFT_KRST0_Bits;
|
||||
|
||||
/** \brief FFT Kernel Reset Register 1 */
|
||||
typedef struct _Ifx_FFT_KRST1_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_FFT_KRST1_Bits;
|
||||
|
||||
/** \brief FFT Kernel Reset Status Clear Register */
|
||||
typedef struct _Ifx_FFT_KRSTCLR_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
|
||||
Ifx_Strict_32Bit reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_FFT_KRSTCLR_Bits;
|
||||
|
||||
/** \brief FFT OCDS Control and Status */
|
||||
typedef struct _Ifx_FFT_OCS_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit reserved_0:24; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
|
||||
Ifx_Strict_32Bit SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
|
||||
Ifx_Strict_32Bit SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
|
||||
Ifx_Strict_32Bit reserved_30:2; /**< \brief \internal Reserved */
|
||||
} Ifx_FFT_OCS_Bits;
|
||||
|
||||
/** \brief FFT OCDS Debug Access Register */
|
||||
typedef struct _Ifx_FFT_ODA_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit DDREN:1; /**< \brief [0:0] Destructive Debug Read Enable (rw) */
|
||||
Ifx_Strict_32Bit DRDIS:1; /**< \brief [1:1] Destructive Read Disable (rw) */
|
||||
Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_FFT_ODA_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Fft_union
|
||||
* \{ */
|
||||
|
||||
/** \brief FFT Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FFT_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FFT_CLC;
|
||||
|
||||
/** \brief FFT Control and Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FFT_CSR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FFT_CSR;
|
||||
|
||||
/** \brief FFT History0 Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FFT_HISTORY0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FFT_HISTORY0;
|
||||
|
||||
/** \brief FFT History1 Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FFT_HISTORY1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FFT_HISTORY1;
|
||||
|
||||
/** \brief FFT Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FFT_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FFT_ID;
|
||||
|
||||
/** \brief FFT Kernel Reset Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FFT_KRST0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FFT_KRST0;
|
||||
|
||||
/** \brief FFT Kernel Reset Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FFT_KRST1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FFT_KRST1;
|
||||
|
||||
/** \brief FFT Kernel Reset Status Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FFT_KRSTCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FFT_KRSTCLR;
|
||||
|
||||
/** \brief FFT OCDS Control and Status */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FFT_OCS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FFT_OCS;
|
||||
|
||||
/** \brief FFT OCDS Debug Access Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FFT_ODA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FFT_ODA;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Fft_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief FFT object */
|
||||
typedef volatile struct _Ifx_FFT
|
||||
{
|
||||
Ifx_FFT_CLC CLC; /**< \brief 0, FFT Clock Control Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_FFT_ID ID; /**< \brief 8, FFT Identification Register */
|
||||
unsigned char reserved_C[52]; /**< \brief C, \internal Reserved */
|
||||
Ifx_FFT_CSR CSR; /**< \brief 40, FFT Control and Status Register */
|
||||
unsigned char reserved_44[28]; /**< \brief 44, \internal Reserved */
|
||||
Ifx_FFT_HISTORY0 HISTORY0; /**< \brief 60, FFT History0 Register */
|
||||
unsigned char reserved_64[12]; /**< \brief 64, \internal Reserved */
|
||||
Ifx_FFT_HISTORY1 HISTORY1; /**< \brief 70, FFT History1 Register */
|
||||
unsigned char reserved_74[112]; /**< \brief 74, \internal Reserved */
|
||||
Ifx_FFT_ODA ODA; /**< \brief E4, FFT OCDS Debug Access Register */
|
||||
Ifx_FFT_OCS OCS; /**< \brief E8, FFT OCDS Control and Status */
|
||||
Ifx_FFT_KRSTCLR KRSTCLR; /**< \brief EC, FFT Kernel Reset Status Clear Register */
|
||||
Ifx_FFT_KRST1 KRST1; /**< \brief F0, FFT Kernel Reset Register 1 */
|
||||
Ifx_FFT_KRST0 KRST0; /**< \brief F4, FFT Kernel Reset Register 0 */
|
||||
unsigned char reserved_F8[8]; /**< \brief F8, \internal Reserved */
|
||||
} Ifx_FFT;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXFFT_REGDEF_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,282 +0,0 @@
|
||||
/**
|
||||
* \file IfxFlash_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Flash_Cfg Flash address
|
||||
* \ingroup IfxLld_Flash
|
||||
*
|
||||
* \defgroup IfxLld_Flash_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Flash_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Flash_Cfg_Flash0 2-FLASH0
|
||||
* \ingroup IfxLld_Flash_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXFLASH_REG_H
|
||||
#define IFXFLASH_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxFlash_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Flash_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief FLASH object. */
|
||||
#define MODULE_FLASH0 /*lint --e(923)*/ (*(Ifx_FLASH*)0xF8001000u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Flash_Cfg_Flash0
|
||||
* \{ */
|
||||
|
||||
/** \brief 13FC, Access Enable Register 0 */
|
||||
#define FLASH0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_ACCEN0*)0xF80023FCu)
|
||||
|
||||
/** \brief 13F8, Access Enable Register 1 */
|
||||
#define FLASH0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_ACCEN1*)0xF80023F8u)
|
||||
|
||||
/** \brief 10B4, CBAB Configuration */
|
||||
#define FLASH0_CBAB0_CFG /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_CFG*)0xF80020B4u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_CBAB0_CFG.
|
||||
* To use register names with standard convension, please use FLASH0_CBAB0_CFG.
|
||||
*/
|
||||
#define FLASH0_CBABCFG0 (FLASH0_CBAB0_CFG)
|
||||
|
||||
/** \brief 10B8, CBAB Status */
|
||||
#define FLASH0_CBAB0_STAT /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_STAT*)0xF80020B8u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_CBAB0_STAT.
|
||||
* To use register names with standard convension, please use FLASH0_CBAB0_STAT.
|
||||
*/
|
||||
#define FLASH0_CBABSTAT0 (FLASH0_CBAB0_STAT)
|
||||
|
||||
/** \brief 10BC, CBAB FIFO TOP Entry */
|
||||
#define FLASH0_CBAB0_TOP /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_TOP*)0xF80020BCu)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_CBAB0_TOP.
|
||||
* To use register names with standard convension, please use FLASH0_CBAB0_TOP.
|
||||
*/
|
||||
#define FLASH0_CBABTOP0 (FLASH0_CBAB0_TOP)
|
||||
|
||||
/** \brief 10C0, CBAB Configuration */
|
||||
#define FLASH0_CBAB1_CFG /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_CFG*)0xF80020C0u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_CBAB1_CFG.
|
||||
* To use register names with standard convension, please use FLASH0_CBAB1_CFG.
|
||||
*/
|
||||
#define FLASH0_CBABCFG1 (FLASH0_CBAB1_CFG)
|
||||
|
||||
/** \brief 10C4, CBAB Status */
|
||||
#define FLASH0_CBAB1_STAT /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_STAT*)0xF80020C4u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_CBAB1_STAT.
|
||||
* To use register names with standard convension, please use FLASH0_CBAB1_STAT.
|
||||
*/
|
||||
#define FLASH0_CBABSTAT1 (FLASH0_CBAB1_STAT)
|
||||
|
||||
/** \brief 10C8, CBAB FIFO TOP Entry */
|
||||
#define FLASH0_CBAB1_TOP /*lint --e(923)*/ (*(volatile Ifx_FLASH_CBAB_TOP*)0xF80020C8u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_CBAB1_TOP.
|
||||
* To use register names with standard convension, please use FLASH0_CBAB1_TOP.
|
||||
*/
|
||||
#define FLASH0_CBABTOP1 (FLASH0_CBAB1_TOP)
|
||||
|
||||
/** \brief 0, FSI Communication Register 0 */
|
||||
#define FLASH0_COMM0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_COMM0*)0xF8001000u)
|
||||
|
||||
/** \brief 4, FSI Communication Register 1 */
|
||||
#define FLASH0_COMM1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_COMM1*)0xF8001004u)
|
||||
|
||||
/** \brief 8, FSI Communication Register 2 */
|
||||
#define FLASH0_COMM2 /*lint --e(923)*/ (*(volatile Ifx_FLASH_COMM2*)0xF8001008u)
|
||||
|
||||
/** \brief 10A4, ECC Read Register DF */
|
||||
#define FLASH0_ECCRD /*lint --e(923)*/ (*(volatile Ifx_FLASH_ECCRD*)0xF80020A4u)
|
||||
|
||||
/** \brief 1094, ECC Read Register for ports */
|
||||
#define FLASH0_ECCRP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_ECCRP*)0xF8002094u)
|
||||
|
||||
/** \brief 1098, ECC Read Register for ports */
|
||||
#define FLASH0_ECCRP1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_ECCRP*)0xF8002098u)
|
||||
|
||||
/** \brief 1090, ECC Write Register */
|
||||
#define FLASH0_ECCW /*lint --e(923)*/ (*(volatile Ifx_FLASH_ECCW*)0xF8002090u)
|
||||
|
||||
/** \brief 1014, Flash Configuration Register */
|
||||
#define FLASH0_FCON /*lint --e(923)*/ (*(volatile Ifx_FLASH_FCON*)0xF8002014u)
|
||||
|
||||
/** \brief 101C, Flash Protection Control and Status Register */
|
||||
#define FLASH0_FPRO /*lint --e(923)*/ (*(volatile Ifx_FLASH_FPRO*)0xF800201Cu)
|
||||
|
||||
/** \brief 1010, Flash Status Register */
|
||||
#define FLASH0_FSR /*lint --e(923)*/ (*(volatile Ifx_FLASH_FSR*)0xF8002010u)
|
||||
|
||||
/** \brief 1008, Flash Module Identification Register */
|
||||
#define FLASH0_ID /*lint --e(923)*/ (*(volatile Ifx_FLASH_ID*)0xF8002008u)
|
||||
|
||||
/** \brief 10AC, Margin Control Register DFlash */
|
||||
#define FLASH0_MARD /*lint --e(923)*/ (*(volatile Ifx_FLASH_MARD*)0xF80020ACu)
|
||||
|
||||
/** \brief 10A8, Margin Control Register PFlash */
|
||||
#define FLASH0_MARP /*lint --e(923)*/ (*(volatile Ifx_FLASH_MARP*)0xF80020A8u)
|
||||
|
||||
/** \brief 1030, DFlash Protection Configuration */
|
||||
#define FLASH0_PROCOND /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCOND*)0xF8002030u)
|
||||
|
||||
/** \brief 1058, Debug Interface Protection Configuration */
|
||||
#define FLASH0_PROCONDBG /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONDBG*)0xF8002058u)
|
||||
|
||||
/** \brief 105C, HSM Interface Configuration */
|
||||
#define FLASH0_PROCONHSM /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONHSM*)0xF800205Cu)
|
||||
|
||||
/** \brief 1034, HSM Code Flash OTP Protection Configuration */
|
||||
#define FLASH0_PROCONHSMCOTP /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONHSMCOTP*)0xF8002034u)
|
||||
|
||||
/** \brief 1038, OTP Protection Configuration for ports */
|
||||
#define FLASH0_PROCONOTP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONOTP*)0xF8002038u)
|
||||
|
||||
/** \brief 103C, OTP Protection Configuration for ports */
|
||||
#define FLASH0_PROCONOTP1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONOTP*)0xF800203Cu)
|
||||
|
||||
/** \brief 1020, PFlash Protection Configuration for ports */
|
||||
#define FLASH0_PROCONP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONP*)0xF8002020u)
|
||||
|
||||
/** \brief 1024, PFlash Protection Configuration for ports */
|
||||
#define FLASH0_PROCONP1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONP*)0xF8002024u)
|
||||
|
||||
/** \brief 1048, Write-Once Protection Configuration for ports */
|
||||
#define FLASH0_PROCONWOP0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONWOP*)0xF8002048u)
|
||||
|
||||
/** \brief 104C, Write-Once Protection Configuration for ports */
|
||||
#define FLASH0_PROCONWOP1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_PROCONWOP*)0xF800204Cu)
|
||||
|
||||
/** \brief 1060, Read Buffer Cfg 0 */
|
||||
#define FLASH0_RDBCFG0_CFG0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG0*)0xF8002060u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_RDBCFG0_CFG0.
|
||||
* To use register names with standard convension, please use FLASH0_RDBCFG0_CFG0.
|
||||
*/
|
||||
#define FLASH0_RDBCFG00 (FLASH0_RDBCFG0_CFG0)
|
||||
|
||||
/** \brief 1064, Read Buffer Cfg 1 */
|
||||
#define FLASH0_RDBCFG0_CFG1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG1*)0xF8002064u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_RDBCFG0_CFG1.
|
||||
* To use register names with standard convension, please use FLASH0_RDBCFG0_CFG1.
|
||||
*/
|
||||
#define FLASH0_RDBCFG01 (FLASH0_RDBCFG0_CFG1)
|
||||
|
||||
/** \brief 1068, Read Buffer Cfg 2 */
|
||||
#define FLASH0_RDBCFG0_CFG2 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG2*)0xF8002068u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_RDBCFG0_CFG2.
|
||||
* To use register names with standard convension, please use FLASH0_RDBCFG0_CFG2.
|
||||
*/
|
||||
#define FLASH0_RDBCFG02 (FLASH0_RDBCFG0_CFG2)
|
||||
|
||||
/** \brief 106C, Read Buffer Cfg 0 */
|
||||
#define FLASH0_RDBCFG1_CFG0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG0*)0xF800206Cu)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_RDBCFG1_CFG0.
|
||||
* To use register names with standard convension, please use FLASH0_RDBCFG1_CFG0.
|
||||
*/
|
||||
#define FLASH0_RDBCFG10 (FLASH0_RDBCFG1_CFG0)
|
||||
|
||||
/** \brief 1070, Read Buffer Cfg 1 */
|
||||
#define FLASH0_RDBCFG1_CFG1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG1*)0xF8002070u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_RDBCFG1_CFG1.
|
||||
* To use register names with standard convension, please use FLASH0_RDBCFG1_CFG1.
|
||||
*/
|
||||
#define FLASH0_RDBCFG11 (FLASH0_RDBCFG1_CFG1)
|
||||
|
||||
/** \brief 1074, Read Buffer Cfg 2 */
|
||||
#define FLASH0_RDBCFG1_CFG2 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RDB_CFG2*)0xF8002074u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_RDBCFG1_CFG2.
|
||||
* To use register names with standard convension, please use FLASH0_RDBCFG1_CFG2.
|
||||
*/
|
||||
#define FLASH0_RDBCFG12 (FLASH0_RDBCFG1_CFG2)
|
||||
|
||||
/** \brief 114C, Requested Read Address Register */
|
||||
#define FLASH0_RRAD /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRAD*)0xF800214Cu)
|
||||
|
||||
/** \brief 1140, Requested Read Control Register */
|
||||
#define FLASH0_RRCT /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRCT*)0xF8002140u)
|
||||
|
||||
/** \brief 1144, Requested Read Data Register 0 */
|
||||
#define FLASH0_RRD0 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRD0*)0xF8002144u)
|
||||
|
||||
/** \brief 1148, Requested Read Data Register 1 */
|
||||
#define FLASH0_RRD1 /*lint --e(923)*/ (*(volatile Ifx_FLASH_RRD1*)0xF8002148u)
|
||||
|
||||
/** \brief 10E4, UBAB Configuration */
|
||||
#define FLASH0_UBAB0_CFG /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_CFG*)0xF80020E4u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_UBAB0_CFG.
|
||||
* To use register names with standard convension, please use FLASH0_UBAB0_CFG.
|
||||
*/
|
||||
#define FLASH0_UBABCFG0 (FLASH0_UBAB0_CFG)
|
||||
|
||||
/** \brief 10E8, UBAB Status */
|
||||
#define FLASH0_UBAB0_STAT /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_STAT*)0xF80020E8u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_UBAB0_STAT.
|
||||
* To use register names with standard convension, please use FLASH0_UBAB0_STAT.
|
||||
*/
|
||||
#define FLASH0_UBABSTAT0 (FLASH0_UBAB0_STAT)
|
||||
|
||||
/** \brief 10EC, UBAB FIFO TOP Entry */
|
||||
#define FLASH0_UBAB0_TOP /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_TOP*)0xF80020ECu)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_UBAB0_TOP.
|
||||
* To use register names with standard convension, please use FLASH0_UBAB0_TOP.
|
||||
*/
|
||||
#define FLASH0_UBABTOP0 (FLASH0_UBAB0_TOP)
|
||||
|
||||
/** \brief 10F0, UBAB Configuration */
|
||||
#define FLASH0_UBAB1_CFG /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_CFG*)0xF80020F0u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_UBAB1_CFG.
|
||||
* To use register names with standard convension, please use FLASH0_UBAB1_CFG.
|
||||
*/
|
||||
#define FLASH0_UBABCFG1 (FLASH0_UBAB1_CFG)
|
||||
|
||||
/** \brief 10F4, UBAB Status */
|
||||
#define FLASH0_UBAB1_STAT /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_STAT*)0xF80020F4u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_UBAB1_STAT.
|
||||
* To use register names with standard convension, please use FLASH0_UBAB1_STAT.
|
||||
*/
|
||||
#define FLASH0_UBABSTAT1 (FLASH0_UBAB1_STAT)
|
||||
|
||||
/** \brief 10F8, UBAB FIFO TOP Entry */
|
||||
#define FLASH0_UBAB1_TOP /*lint --e(923)*/ (*(volatile Ifx_FLASH_UBAB_TOP*)0xF80020F8u)
|
||||
|
||||
/** Alias (User Manual Name) for FLASH0_UBAB1_TOP.
|
||||
* To use register names with standard convension, please use FLASH0_UBAB1_TOP.
|
||||
*/
|
||||
#define FLASH0_UBABTOP1 (FLASH0_UBAB1_TOP)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXFLASH_REG_H */
|
||||
@@ -1,901 +0,0 @@
|
||||
/**
|
||||
* \file IfxFlash_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Flash Flash
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Flash_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Flash
|
||||
*
|
||||
* \defgroup IfxLld_Flash_union Union
|
||||
* \ingroup IfxLld_Flash
|
||||
*
|
||||
* \defgroup IfxLld_Flash_struct Struct
|
||||
* \ingroup IfxLld_Flash
|
||||
*
|
||||
*/
|
||||
#ifndef IFXFLASH_REGDEF_H
|
||||
#define IFXFLASH_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Flash_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_FLASH_ACCEN0_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_FLASH_ACCEN0_Bits;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef struct _Ifx_FLASH_ACCEN1_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_ACCEN1_Bits;
|
||||
|
||||
/** \brief CBAB Configuration */
|
||||
typedef struct _Ifx_FLASH_CBAB_CFG_Bits
|
||||
{
|
||||
unsigned int SEL:6; /**< \brief [5:0] Select Bit-Errors (rw) */
|
||||
unsigned int reserved_6:2; /**< \brief \internal Reserved */
|
||||
unsigned int CLR:1; /**< \brief [8:8] Clear (w) */
|
||||
unsigned int DIS:1; /**< \brief [9:9] Disable (rw) */
|
||||
unsigned int reserved_10:22; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_CBAB_CFG_Bits;
|
||||
|
||||
/** \brief CBAB Status */
|
||||
typedef struct _Ifx_FLASH_CBAB_STAT_Bits
|
||||
{
|
||||
unsigned int VLD0:1; /**< \brief [0:0] Filling Level (rh) */
|
||||
unsigned int VLD1:1; /**< \brief [1:1] Filling Level (rh) */
|
||||
unsigned int VLD2:1; /**< \brief [2:2] Filling Level (rh) */
|
||||
unsigned int VLD3:1; /**< \brief [3:3] Filling Level (rh) */
|
||||
unsigned int VLD4:1; /**< \brief [4:4] Filling Level (rh) */
|
||||
unsigned int VLD5:1; /**< \brief [5:5] Filling Level (rh) */
|
||||
unsigned int VLD6:1; /**< \brief [6:6] Filling Level (rh) */
|
||||
unsigned int VLD7:1; /**< \brief [7:7] Filling Level (rh) */
|
||||
unsigned int VLD8:1; /**< \brief [8:8] Filling Level (rh) */
|
||||
unsigned int VLD9:1; /**< \brief [9:9] Filling Level (rh) */
|
||||
unsigned int reserved_10:22; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_CBAB_STAT_Bits;
|
||||
|
||||
/** \brief CBAB FIFO TOP Entry */
|
||||
typedef struct _Ifx_FLASH_CBAB_TOP_Bits
|
||||
{
|
||||
unsigned int reserved_0:5; /**< \brief \internal Reserved */
|
||||
unsigned int ADDR:19; /**< \brief [23:5] Address (rh) */
|
||||
unsigned int ERR:6; /**< \brief [29:24] Error Type (rh) */
|
||||
unsigned int VLD:1; /**< \brief [30:30] Valid (rh) */
|
||||
unsigned int CLR:1; /**< \brief [31:31] Clear (w) */
|
||||
} Ifx_FLASH_CBAB_TOP_Bits;
|
||||
|
||||
/** \brief FSI Communication Register 0 */
|
||||
typedef struct _Ifx_FLASH_COMM0_Bits
|
||||
{
|
||||
unsigned int STATUS:8; /**< \brief [7:0] Status (rh) */
|
||||
unsigned int reserved_8:24; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_COMM0_Bits;
|
||||
|
||||
/** \brief FSI Communication Register 1 */
|
||||
typedef struct _Ifx_FLASH_COMM1_Bits
|
||||
{
|
||||
unsigned int STATUS:8; /**< \brief [7:0] Status (rh) */
|
||||
unsigned int DATA:8; /**< \brief [15:8] Data (rwh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_COMM1_Bits;
|
||||
|
||||
/** \brief FSI Communication Register 2 */
|
||||
typedef struct _Ifx_FLASH_COMM2_Bits
|
||||
{
|
||||
unsigned int STATUS:8; /**< \brief [7:0] Status (rh) */
|
||||
unsigned int DATA:8; /**< \brief [15:8] Data (rwh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_COMM2_Bits;
|
||||
|
||||
/** \brief ECC Read Register DF */
|
||||
typedef struct _Ifx_FLASH_ECCRD_Bits
|
||||
{
|
||||
unsigned int RCODE:22; /**< \brief [21:0] Error Correction Read Code (rh) */
|
||||
unsigned int reserved_22:8; /**< \brief \internal Reserved */
|
||||
unsigned int EDCERRINJ:1; /**< \brief [30:30] EDC Error Injection (rw) */
|
||||
unsigned int ECCORDIS:1; /**< \brief [31:31] ECC Correction Disable (rw) */
|
||||
} Ifx_FLASH_ECCRD_Bits;
|
||||
|
||||
/** \brief ECC Read Register */
|
||||
typedef struct _Ifx_FLASH_ECCRP_Bits
|
||||
{
|
||||
unsigned int RCODE:22; /**< \brief [21:0] Error Correction Read Code (rh) */
|
||||
unsigned int reserved_22:8; /**< \brief \internal Reserved */
|
||||
unsigned int EDCERRINJ:1; /**< \brief [30:30] EDC Error Injection (rw) */
|
||||
unsigned int ECCORDIS:1; /**< \brief [31:31] ECC Correction Disable (rw) */
|
||||
} Ifx_FLASH_ECCRP_Bits;
|
||||
|
||||
/** \brief ECC Write Register */
|
||||
typedef struct _Ifx_FLASH_ECCW_Bits
|
||||
{
|
||||
unsigned int WCODE:22; /**< \brief [21:0] Error Correction Write Code (rw) */
|
||||
unsigned int reserved_22:8; /**< \brief \internal Reserved */
|
||||
unsigned int DECENCDIS:1; /**< \brief [30:30] DF_EEPROM ECC Encoding Disable (rw) */
|
||||
unsigned int PECENCDIS:1; /**< \brief [31:31] PFlash ECC Encoding Disable (rw) */
|
||||
} Ifx_FLASH_ECCW_Bits;
|
||||
|
||||
/** \brief Flash Configuration Register */
|
||||
typedef struct _Ifx_FLASH_FCON_Bits
|
||||
{
|
||||
unsigned int WSPFLASH:4; /**< \brief [3:0] Wait States for read access to PFlash (rw) */
|
||||
unsigned int WSECPF:2; /**< \brief [5:4] Wait States for Error Correction of PFlash (rw) */
|
||||
unsigned int WSDFLASH:6; /**< \brief [11:6] Wait States for read access to DFlash (rw) */
|
||||
unsigned int WSECDF:3; /**< \brief [14:12] Wait State for Error Correction of DFlash (rw) */
|
||||
unsigned int IDLE:1; /**< \brief [15:15] Dynamic Flash Idle (rw) */
|
||||
unsigned int ESLDIS:1; /**< \brief [16:16] External Sleep Request Disable (rw) */
|
||||
unsigned int SLEEP:1; /**< \brief [17:17] Flash SLEEP (rw) */
|
||||
unsigned int NSAFECC:1; /**< \brief [18:18] Non-Safety PFlash ECC (rw) */
|
||||
unsigned int STALL:1; /**< \brief [19:19] Stall SRI (rw) */
|
||||
unsigned int RES21:2; /**< \brief [21:20] Reserved (rh) */
|
||||
unsigned int RES23:2; /**< \brief [23:22] Reserved (rh) */
|
||||
unsigned int VOPERM:1; /**< \brief [24:24] Verify and Operation Error Interrupt Mask (rw) */
|
||||
unsigned int SQERM:1; /**< \brief [25:25] Command Sequence Error Interrupt Mask (rw) */
|
||||
unsigned int PROERM:1; /**< \brief [26:26] Protection Error Interrupt Mask (rw) */
|
||||
unsigned int reserved_27:3; /**< \brief \internal Reserved */
|
||||
unsigned int PR5V:1; /**< \brief [30:30] Programming Supply 5V (rw) */
|
||||
unsigned int EOBM:1; /**< \brief [31:31] End of Busy Interrupt Mask (rw) */
|
||||
} Ifx_FLASH_FCON_Bits;
|
||||
|
||||
/** \brief Flash Protection Control and Status Register */
|
||||
typedef struct _Ifx_FLASH_FPRO_Bits
|
||||
{
|
||||
unsigned int PROINP:1; /**< \brief [0:0] PFlash Protection (rh) */
|
||||
unsigned int PRODISP:1; /**< \brief [1:1] PFlash Protection Disabled (rh) */
|
||||
unsigned int PROIND:1; /**< \brief [2:2] DFlash Protection (rh) */
|
||||
unsigned int PRODISD:1; /**< \brief [3:3] DFlash Protection Disabled (rh) */
|
||||
unsigned int PROINHSMCOTP:1; /**< \brief [4:4] HSM OTP Protection (rh) */
|
||||
unsigned int RES5:1; /**< \brief [5:5] Reserved (rh) */
|
||||
unsigned int PROINOTP:1; /**< \brief [6:6] OTP and Write-Once Protection (rh) */
|
||||
unsigned int RES7:1; /**< \brief [7:7] Reserved (rh) */
|
||||
unsigned int PROINDBG:1; /**< \brief [8:8] Debug Interface Password Protection (rh) */
|
||||
unsigned int PRODISDBG:1; /**< \brief [9:9] Debug Interface Password Protection Disabled (rh) */
|
||||
unsigned int PROINHSM:1; /**< \brief [10:10] HSM Configuration (rh) */
|
||||
unsigned int reserved_11:5; /**< \brief \internal Reserved */
|
||||
unsigned int DCFP:1; /**< \brief [16:16] Disable Code Fetch from PFlash Memory for CPU0 PMI (rwh) */
|
||||
unsigned int DDFP:1; /**< \brief [17:17] Disable Read from PFlash for CPU0 DMI (rwh) */
|
||||
unsigned int DDFPX:1; /**< \brief [18:18] Disable Read from PFlash for Other Masters (rwh) */
|
||||
unsigned int reserved_19:1; /**< \brief \internal Reserved */
|
||||
unsigned int DDFD:1; /**< \brief [20:20] Disable Data Fetch from DFlash Memory (rwh) */
|
||||
unsigned int reserved_21:1; /**< \brief \internal Reserved */
|
||||
unsigned int ENPE:2; /**< \brief [23:22] Enable Program/Erase (rw) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_FPRO_Bits;
|
||||
|
||||
/** \brief Flash Status Register */
|
||||
typedef struct _Ifx_FLASH_FSR_Bits
|
||||
{
|
||||
unsigned int FABUSY:1; /**< \brief [0:0] Flash Array Busy (rh) */
|
||||
unsigned int D0BUSY:1; /**< \brief [1:1] Data Flash Bank 0 Busy (rh) */
|
||||
unsigned int RES1:1; /**< \brief [2:2] Reserved for Data Flash Bank 1 Busy (rh) */
|
||||
unsigned int P0BUSY:1; /**< \brief [3:3] Program Flash PF0 Busy (rh) */
|
||||
unsigned int P1BUSY:1; /**< \brief [4:4] Program Flash PF1 Busy (rh) */
|
||||
unsigned int RES5:1; /**< \brief [5:5] Reserved for Program Flash PF2 Busy (rh) */
|
||||
unsigned int RES6:1; /**< \brief [6:6] Reserved for Program Flash PF3 Busy (rh) */
|
||||
unsigned int PROG:1; /**< \brief [7:7] Programming State (rwh) */
|
||||
unsigned int ERASE:1; /**< \brief [8:8] Erase State (rwh) */
|
||||
unsigned int PFPAGE:1; /**< \brief [9:9] Program Flash in Page Mode (rh) */
|
||||
unsigned int DFPAGE:1; /**< \brief [10:10] Data Flash in Page Mode (rh) */
|
||||
unsigned int OPER:1; /**< \brief [11:11] Flash Operation Error (rwh) */
|
||||
unsigned int SQER:1; /**< \brief [12:12] Command Sequence Error (rwh) */
|
||||
unsigned int PROER:1; /**< \brief [13:13] Protection Error (rwh) */
|
||||
unsigned int PFSBER:1; /**< \brief [14:14] PFlash Single-Bit Error and Correction (rwh) */
|
||||
unsigned int PFDBER:1; /**< \brief [15:15] PFlash Double-Bit Error (rwh) */
|
||||
unsigned int PFMBER:1; /**< \brief [16:16] PFlash Uncorrectable Error (rwh) */
|
||||
unsigned int RES17:1; /**< \brief [17:17] Reserved (rwh) */
|
||||
unsigned int DFSBER:1; /**< \brief [18:18] DFlash Single-Bit Error (rwh) */
|
||||
unsigned int DFDBER:1; /**< \brief [19:19] DFlash Double-Bit Error (rwh) */
|
||||
unsigned int DFTBER:1; /**< \brief [20:20] DFlash Triple-Bit Error (rwh) */
|
||||
unsigned int DFMBER:1; /**< \brief [21:21] DFlash Uncorrectable Error (rwh) */
|
||||
unsigned int SRIADDERR:1; /**< \brief [22:22] SRI Bus Address ECC Error (rwh) */
|
||||
unsigned int reserved_23:2; /**< \brief \internal Reserved */
|
||||
unsigned int PVER:1; /**< \brief [25:25] Program Verify Error (rwh) */
|
||||
unsigned int EVER:1; /**< \brief [26:26] Erase Verify Error (rwh) */
|
||||
unsigned int SPND:1; /**< \brief [27:27] Operation Suspended (rwh) */
|
||||
unsigned int SLM:1; /**< \brief [28:28] Flash Sleep Mode (rh) */
|
||||
unsigned int reserved_29:1; /**< \brief \internal Reserved */
|
||||
unsigned int ORIER:1; /**< \brief [30:30] Original Error (rh) */
|
||||
unsigned int reserved_31:1; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_FSR_Bits;
|
||||
|
||||
/** \brief Flash Module Identification Register */
|
||||
typedef struct _Ifx_FLASH_ID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_FLASH_ID_Bits;
|
||||
|
||||
/** \brief Margin Control Register DFlash */
|
||||
typedef struct _Ifx_FLASH_MARD_Bits
|
||||
{
|
||||
unsigned int HMARGIN:1; /**< \brief [0:0] Hard Margin Selection (rw) */
|
||||
unsigned int SELD0:1; /**< \brief [1:1] DFLASH Bank Selection (rw) */
|
||||
unsigned int reserved_2:1; /**< \brief \internal Reserved */
|
||||
unsigned int SPND:1; /**< \brief [3:3] Suspend (rwh) */
|
||||
unsigned int SPNDERR:1; /**< \brief [4:4] Suspend Error (rwh) */
|
||||
unsigned int reserved_5:10; /**< \brief \internal Reserved */
|
||||
unsigned int TRAPDIS:1; /**< \brief [15:15] DFLASH Uncorrectable Bit Error Trap Disable (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_MARD_Bits;
|
||||
|
||||
/** \brief Margin Control Register PFlash */
|
||||
typedef struct _Ifx_FLASH_MARP_Bits
|
||||
{
|
||||
unsigned int SELP0:1; /**< \brief [0:0] PFLASH Bank PF0 Selection (rw) */
|
||||
unsigned int SELP1:1; /**< \brief [1:1] PFLASH Bank PF1 Selection (rw) */
|
||||
unsigned int RES2:1; /**< \brief [2:2] Reserved (rw) */
|
||||
unsigned int RES3:1; /**< \brief [3:3] Reserved (rw) */
|
||||
unsigned int reserved_4:11; /**< \brief \internal Reserved */
|
||||
unsigned int TRAPDIS:1; /**< \brief [15:15] PFLASH Uncorrectable Bit Error Trap Disable (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_MARP_Bits;
|
||||
|
||||
/** \brief DFlash Protection Configuration */
|
||||
typedef struct _Ifx_FLASH_PROCOND_Bits
|
||||
{
|
||||
unsigned int L:1; /**< \brief [0:0] DF_EEPROM Locked for Write Protection (rh) */
|
||||
unsigned int NSAFECC:1; /**< \brief [1:1] Non-Safety PFlash ECC (rh) */
|
||||
unsigned int RAMIN:2; /**< \brief [3:2] RAM Initialization by SSW Control (rh) */
|
||||
unsigned int RAMINSEL:4; /**< \brief [7:4] RAM Initialization Selection (rh) */
|
||||
unsigned int OSCCFG:1; /**< \brief [8:8] OSC Configuration by SSW (rh) */
|
||||
unsigned int MODE:2; /**< \brief [10:9] OSC Mode (rh) */
|
||||
unsigned int APREN:1; /**< \brief [11:11] OSC Amplitude Regulation Enable (rh) */
|
||||
unsigned int CAP0EN:1; /**< \brief [12:12] OSC Capacitance 0 Enable (rh) */
|
||||
unsigned int CAP1EN:1; /**< \brief [13:13] OSC Capacitance 1 Enable (rh) */
|
||||
unsigned int CAP2EN:1; /**< \brief [14:14] OSC Capacitance 2 Enable (rh) */
|
||||
unsigned int CAP3EN:1; /**< \brief [15:15] OSC Capacitance 3 Enable (rh) */
|
||||
unsigned int ESR0CNT:12; /**< \brief [27:16] ESR0 Prolongation Counter (rh) */
|
||||
unsigned int RES29:2; /**< \brief [29:28] Reserved (rh) */
|
||||
unsigned int RES30:1; /**< \brief [30:30] Reserved (rh) */
|
||||
unsigned int RPRO:1; /**< \brief [31:31] Read Protection Configuration (rh) */
|
||||
} Ifx_FLASH_PROCOND_Bits;
|
||||
|
||||
/** \brief Debug Interface Protection Configuration */
|
||||
typedef struct _Ifx_FLASH_PROCONDBG_Bits
|
||||
{
|
||||
unsigned int OCDSDIS:1; /**< \brief [0:0] OCDS Disabled (rh) */
|
||||
unsigned int DBGIFLCK:1; /**< \brief [1:1] Debug Interface Locked (rh) */
|
||||
unsigned int EDM:2; /**< \brief [3:2] Entered Debug Mode (rh) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_PROCONDBG_Bits;
|
||||
|
||||
/** \brief HSM Interface Configuration */
|
||||
typedef struct _Ifx_FLASH_PROCONHSM_Bits
|
||||
{
|
||||
unsigned int HSMDBGDIS:1; /**< \brief [0:0] HSM Debug Disable (rh) */
|
||||
unsigned int DBGIFLCK:1; /**< \brief [1:1] Debug Interface Locked (rh) */
|
||||
unsigned int TSTIFLCK:1; /**< \brief [2:2] Test Interface Locked (rh) */
|
||||
unsigned int HSMTSTDIS:1; /**< \brief [3:3] HSM Test Disable (rh) */
|
||||
unsigned int RES15:12; /**< \brief [15:4] Reserved (rh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_PROCONHSM_Bits;
|
||||
|
||||
/** \brief HSM Code Flash OTP Protection Configuration */
|
||||
typedef struct _Ifx_FLASH_PROCONHSMCOTP_Bits
|
||||
{
|
||||
unsigned int HSMBOOTEN:1; /**< \brief [0:0] HSM Boot Enable (rh) */
|
||||
unsigned int SSWWAIT:1; /**< \brief [1:1] SSW Wait (rh) */
|
||||
unsigned int HSMDX:1; /**< \brief [2:2] HSM Data Sectors Exclusive (rh) */
|
||||
unsigned int HSM6X:1; /**< \brief [3:3] HSM Code Sector 6 Exclusive (rh) */
|
||||
unsigned int HSM16X:1; /**< \brief [4:4] HSM Code Sector 16 Exclusive (rh) */
|
||||
unsigned int HSM17X:1; /**< \brief [5:5] HSM Code Sector 17 Exclusive (rh) */
|
||||
unsigned int S6ROM:1; /**< \brief [6:6] HSM Code Sector 6 Locked Forever (rh) */
|
||||
unsigned int HSMENPINS:2; /**< \brief [8:7] Enable HSM Forcing of Pins HSM1/2 (rh) */
|
||||
unsigned int HSMENRES:2; /**< \brief [10:9] Enable HSM Triggering Resets (rh) */
|
||||
unsigned int DESTDBG:2; /**< \brief [12:11] Destructive Debug Entry (rh) */
|
||||
unsigned int BLKFLAN:1; /**< \brief [13:13] Block Flash Analysis (rh) */
|
||||
unsigned int reserved_14:2; /**< \brief \internal Reserved */
|
||||
unsigned int S16ROM:1; /**< \brief [16:16] HSM Code Sector 16 Locked Forever (rh) */
|
||||
unsigned int S17ROM:1; /**< \brief [17:17] HSM Code Sector 17 Locked Forever (rh) */
|
||||
unsigned int reserved_18:14; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_PROCONHSMCOTP_Bits;
|
||||
|
||||
/** \brief OTP Protection Configuration */
|
||||
typedef struct _Ifx_FLASH_PROCONOTP_Bits
|
||||
{
|
||||
unsigned int S0ROM:1; /**< \brief [0:0] PFlash p Sector 0 Locked Forever (rh) */
|
||||
unsigned int S1ROM:1; /**< \brief [1:1] PFlash p Sector 1 Locked Forever (rh) */
|
||||
unsigned int S2ROM:1; /**< \brief [2:2] PFlash p Sector 2 Locked Forever (rh) */
|
||||
unsigned int S3ROM:1; /**< \brief [3:3] PFlash p Sector 3 Locked Forever (rh) */
|
||||
unsigned int S4ROM:1; /**< \brief [4:4] PFlash p Sector 4 Locked Forever (rh) */
|
||||
unsigned int S5ROM:1; /**< \brief [5:5] PFlash p Sector 5 Locked Forever (rh) */
|
||||
unsigned int S6ROM:1; /**< \brief [6:6] PFlash p Sector 6 Locked Forever (rh) */
|
||||
unsigned int S7ROM:1; /**< \brief [7:7] PFlash p Sector 7 Locked Forever (rh) */
|
||||
unsigned int S8ROM:1; /**< \brief [8:8] PFlash p Sector 8 Locked Forever (rh) */
|
||||
unsigned int S9ROM:1; /**< \brief [9:9] PFlash p Sector 9 Locked Forever (rh) */
|
||||
unsigned int S10ROM:1; /**< \brief [10:10] PFlash p Sector 10 Locked Forever (rh) */
|
||||
unsigned int S11ROM:1; /**< \brief [11:11] PFlash p Sector 11 Locked Forever (rh) */
|
||||
unsigned int S12ROM:1; /**< \brief [12:12] PFlash p Sector 12 Locked Forever (rh) */
|
||||
unsigned int S13ROM:1; /**< \brief [13:13] PFlash p Sector 13 Locked Forever (rh) */
|
||||
unsigned int S14ROM:1; /**< \brief [14:14] PFlash p Sector 14 Locked Forever (rh) */
|
||||
unsigned int S15ROM:1; /**< \brief [15:15] PFlash p Sector 15 Locked Forever (rh) */
|
||||
unsigned int S16ROM:1; /**< \brief [16:16] PFlash p Sector 16 Locked Forever (rh) */
|
||||
unsigned int S17ROM:1; /**< \brief [17:17] PFlash p Sector 17 Locked Forever (rh) */
|
||||
unsigned int S18ROM:1; /**< \brief [18:18] PFlash p Sector 18 Locked Forever (rh) */
|
||||
unsigned int S19ROM:1; /**< \brief [19:19] PFlash p Sector 19 Locked Forever (rh) */
|
||||
unsigned int S20ROM:1; /**< \brief [20:20] PFlash p Sector 20 Locked Forever (rh) */
|
||||
unsigned int S21ROM:1; /**< \brief [21:21] PFlash p Sector 21 Locked Forever (rh) */
|
||||
unsigned int S22ROM:1; /**< \brief [22:22] PFlash p Sector 22 Locked Forever (rh) */
|
||||
unsigned int S23ROM:1; /**< \brief [23:23] PFlash p Sector 23 Locked Forever (rh) */
|
||||
unsigned int S24ROM:1; /**< \brief [24:24] PFlash p Sector 24 Locked Forever (rh) */
|
||||
unsigned int S25ROM:1; /**< \brief [25:25] PFlash p Sector 25 Locked Forever (rh) */
|
||||
unsigned int S26ROM:1; /**< \brief [26:26] PFlash p Sector 26 Locked Forever (rh) */
|
||||
unsigned int reserved_27:2; /**< \brief \internal Reserved */
|
||||
unsigned int BML:2; /**< \brief [30:29] Boot Mode Lock (rh) */
|
||||
unsigned int TP:1; /**< \brief [31:31] Tuning Protection (rh) */
|
||||
} Ifx_FLASH_PROCONOTP_Bits;
|
||||
|
||||
/** \brief PFlash Protection Configuration */
|
||||
typedef struct _Ifx_FLASH_PROCONP_Bits
|
||||
{
|
||||
unsigned int S0L:1; /**< \brief [0:0] PFlash p Sector 0 Locked for Write Protection (rh) */
|
||||
unsigned int S1L:1; /**< \brief [1:1] PFlash p Sector 1 Locked for Write Protection (rh) */
|
||||
unsigned int S2L:1; /**< \brief [2:2] PFlash p Sector 2 Locked for Write Protection (rh) */
|
||||
unsigned int S3L:1; /**< \brief [3:3] PFlash p Sector 3 Locked for Write Protection (rh) */
|
||||
unsigned int S4L:1; /**< \brief [4:4] PFlash p Sector 4 Locked for Write Protection (rh) */
|
||||
unsigned int S5L:1; /**< \brief [5:5] PFlash p Sector 5 Locked for Write Protection (rh) */
|
||||
unsigned int S6L:1; /**< \brief [6:6] PFlash p Sector 6 Locked for Write Protection (rh) */
|
||||
unsigned int S7L:1; /**< \brief [7:7] PFlash p Sector 7 Locked for Write Protection (rh) */
|
||||
unsigned int S8L:1; /**< \brief [8:8] PFlash p Sector 8 Locked for Write Protection (rh) */
|
||||
unsigned int S9L:1; /**< \brief [9:9] PFlash p Sector 9 Locked for Write Protection (rh) */
|
||||
unsigned int S10L:1; /**< \brief [10:10] PFlash p Sector 10 Locked for Write Protection (rh) */
|
||||
unsigned int S11L:1; /**< \brief [11:11] PFlash p Sector 11 Locked for Write Protection (rh) */
|
||||
unsigned int S12L:1; /**< \brief [12:12] PFlash p Sector 12 Locked for Write Protection (rh) */
|
||||
unsigned int S13L:1; /**< \brief [13:13] PFlash p Sector 13 Locked for Write Protection (rh) */
|
||||
unsigned int S14L:1; /**< \brief [14:14] PFlash p Sector 14 Locked for Write Protection (rh) */
|
||||
unsigned int S15L:1; /**< \brief [15:15] PFlash p Sector 15 Locked for Write Protection (rh) */
|
||||
unsigned int S16L:1; /**< \brief [16:16] PFlash p Sector 16 Locked for Write Protection (rh) */
|
||||
unsigned int S17L:1; /**< \brief [17:17] PFlash p Sector 17 Locked for Write Protection (rh) */
|
||||
unsigned int S18L:1; /**< \brief [18:18] PFlash p Sector 18 Locked for Write Protection (rh) */
|
||||
unsigned int S19L:1; /**< \brief [19:19] PFlash p Sector 19 Locked for Write Protection (rh) */
|
||||
unsigned int S20L:1; /**< \brief [20:20] PFlash p Sector 20 Locked for Write Protection (rh) */
|
||||
unsigned int S21L:1; /**< \brief [21:21] PFlash p Sector 21 Locked for Write Protection (rh) */
|
||||
unsigned int S22L:1; /**< \brief [22:22] PFlash p Sector 22 Locked for Write Protection (rh) */
|
||||
unsigned int S23L:1; /**< \brief [23:23] PFlash p Sector 23 Locked for Write Protection (rh) */
|
||||
unsigned int S24L:1; /**< \brief [24:24] PFlash p Sector 24 Locked for Write Protection (rh) */
|
||||
unsigned int S25L:1; /**< \brief [25:25] PFlash p Sector 25 Locked for Write Protection (rh) */
|
||||
unsigned int S26L:1; /**< \brief [26:26] PFlash p Sector 26 Locked for Write Protection (rh) */
|
||||
unsigned int reserved_27:4; /**< \brief \internal Reserved */
|
||||
unsigned int RPRO:1; /**< \brief [31:31] Read Protection Configuration (rh) */
|
||||
} Ifx_FLASH_PROCONP_Bits;
|
||||
|
||||
/** \brief Write-Once Protection Configuration */
|
||||
typedef struct _Ifx_FLASH_PROCONWOP_Bits
|
||||
{
|
||||
unsigned int S0WOP:1; /**< \brief [0:0] PFlash p Sector 0 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S1WOP:1; /**< \brief [1:1] PFlash p Sector 1 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S2WOP:1; /**< \brief [2:2] PFlash p Sector 2 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S3WOP:1; /**< \brief [3:3] PFlash p Sector 3 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S4WOP:1; /**< \brief [4:4] PFlash p Sector 4 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S5WOP:1; /**< \brief [5:5] PFlash p Sector 5 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S6WOP:1; /**< \brief [6:6] PFlash p Sector 6 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S7WOP:1; /**< \brief [7:7] PFlash p Sector 7 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S8WOP:1; /**< \brief [8:8] PFlash p Sector 8 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S9WOP:1; /**< \brief [9:9] PFlash p Sector 9 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S10WOP:1; /**< \brief [10:10] PFlash p Sector 10 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S11WOP:1; /**< \brief [11:11] PFlash p Sector 11 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S12WOP:1; /**< \brief [12:12] PFlash p Sector 12 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S13WOP:1; /**< \brief [13:13] PFlash p Sector 13 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S14WOP:1; /**< \brief [14:14] PFlash p Sector 14 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S15WOP:1; /**< \brief [15:15] PFlash p Sector 15 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S16WOP:1; /**< \brief [16:16] PFlash p Sector 16 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S17WOP:1; /**< \brief [17:17] PFlash p Sector 17 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S18WOP:1; /**< \brief [18:18] PFlash p Sector 18 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S19WOP:1; /**< \brief [19:19] PFlash p Sector 19 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S20WOP:1; /**< \brief [20:20] PFlash p Sector 20 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S21WOP:1; /**< \brief [21:21] PFlash p Sector 21 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S22WOP:1; /**< \brief [22:22] PFlash p Sector 22 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S23WOP:1; /**< \brief [23:23] PFlash p Sector 23 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S24WOP:1; /**< \brief [24:24] PFlash p Sector 24 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S25WOP:1; /**< \brief [25:25] PFlash p Sector 25 Configured for Write-Once Protection (rh) */
|
||||
unsigned int S26WOP:1; /**< \brief [26:26] PFlash p Sector 26 Configured for Write-Once Protection (rh) */
|
||||
unsigned int reserved_27:4; /**< \brief \internal Reserved */
|
||||
unsigned int DATM:1; /**< \brief [31:31] Disable ATM (rh) */
|
||||
} Ifx_FLASH_PROCONWOP_Bits;
|
||||
|
||||
/** \brief Read Buffer Cfg 0 */
|
||||
typedef struct _Ifx_FLASH_RDB_CFG0_Bits
|
||||
{
|
||||
unsigned int TAG:6; /**< \brief [5:0] Master Tag (rw) */
|
||||
unsigned int reserved_6:26; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_RDB_CFG0_Bits;
|
||||
|
||||
/** \brief Read Buffer Cfg 1 */
|
||||
typedef struct _Ifx_FLASH_RDB_CFG1_Bits
|
||||
{
|
||||
unsigned int TAG:6; /**< \brief [5:0] Master Tag (rw) */
|
||||
unsigned int reserved_6:26; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_RDB_CFG1_Bits;
|
||||
|
||||
/** \brief Read Buffer Cfg 2 */
|
||||
typedef struct _Ifx_FLASH_RDB_CFG2_Bits
|
||||
{
|
||||
unsigned int TAG:6; /**< \brief [5:0] Master Tag (rw) */
|
||||
unsigned int reserved_6:26; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_RDB_CFG2_Bits;
|
||||
|
||||
/** \brief Requested Read Address Register */
|
||||
typedef struct _Ifx_FLASH_RRAD_Bits
|
||||
{
|
||||
unsigned int reserved_0:3; /**< \brief \internal Reserved */
|
||||
unsigned int ADD:29; /**< \brief [31:3] Address (rwh) */
|
||||
} Ifx_FLASH_RRAD_Bits;
|
||||
|
||||
/** \brief Requested Read Control Register */
|
||||
typedef struct _Ifx_FLASH_RRCT_Bits
|
||||
{
|
||||
unsigned int STRT:1; /**< \brief [0:0] Start Request (rwh) */
|
||||
unsigned int STP:1; /**< \brief [1:1] Stop (w) */
|
||||
unsigned int BUSY:1; /**< \brief [2:2] Flash Read Busy (rh) */
|
||||
unsigned int DONE:1; /**< \brief [3:3] Flash Read Done (rh) */
|
||||
unsigned int ERR:1; /**< \brief [4:4] Error (rh) */
|
||||
unsigned int reserved_5:3; /**< \brief \internal Reserved */
|
||||
unsigned int EOBM:1; /**< \brief [8:8] End of Busy Interrupt Mask (rw) */
|
||||
unsigned int reserved_9:7; /**< \brief \internal Reserved */
|
||||
unsigned int CNT:16; /**< \brief [31:16] Count (rwh) */
|
||||
} Ifx_FLASH_RRCT_Bits;
|
||||
|
||||
/** \brief Requested Read Data Register 0 */
|
||||
typedef struct _Ifx_FLASH_RRD0_Bits
|
||||
{
|
||||
unsigned int DATA:32; /**< \brief [31:0] Read Data (rh) */
|
||||
} Ifx_FLASH_RRD0_Bits;
|
||||
|
||||
/** \brief Requested Read Data Register 1 */
|
||||
typedef struct _Ifx_FLASH_RRD1_Bits
|
||||
{
|
||||
unsigned int DATA:32; /**< \brief [31:0] Read Data (rh) */
|
||||
} Ifx_FLASH_RRD1_Bits;
|
||||
|
||||
/** \brief UBAB Configuration */
|
||||
typedef struct _Ifx_FLASH_UBAB_CFG_Bits
|
||||
{
|
||||
unsigned int SEL:6; /**< \brief [5:0] Select Bit-Errors (rw) */
|
||||
unsigned int reserved_6:2; /**< \brief \internal Reserved */
|
||||
unsigned int CLR:1; /**< \brief [8:8] Clear (w) */
|
||||
unsigned int DIS:1; /**< \brief [9:9] Disable (rw) */
|
||||
unsigned int reserved_10:22; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_UBAB_CFG_Bits;
|
||||
|
||||
/** \brief UBAB Status */
|
||||
typedef struct _Ifx_FLASH_UBAB_STAT_Bits
|
||||
{
|
||||
unsigned int VLD0:1; /**< \brief [0:0] Filling Level (rh) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_FLASH_UBAB_STAT_Bits;
|
||||
|
||||
/** \brief UBAB FIFO TOP Entry */
|
||||
typedef struct _Ifx_FLASH_UBAB_TOP_Bits
|
||||
{
|
||||
unsigned int reserved_0:5; /**< \brief \internal Reserved */
|
||||
unsigned int ADDR:19; /**< \brief [23:5] Address (rh) */
|
||||
unsigned int ERR:6; /**< \brief [29:24] Error Type (rh) */
|
||||
unsigned int VLD:1; /**< \brief [30:30] Valid (rh) */
|
||||
unsigned int CLR:1; /**< \brief [31:31] Clear (w) */
|
||||
} Ifx_FLASH_UBAB_TOP_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Flash_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_ACCEN0;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_ACCEN1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_ACCEN1;
|
||||
|
||||
/** \brief CBAB Configuration */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_CBAB_CFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_CBAB_CFG;
|
||||
|
||||
/** \brief CBAB Status */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_CBAB_STAT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_CBAB_STAT;
|
||||
|
||||
/** \brief CBAB FIFO TOP Entry */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_CBAB_TOP_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_CBAB_TOP;
|
||||
|
||||
/** \brief FSI Communication Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_COMM0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_COMM0;
|
||||
|
||||
/** \brief FSI Communication Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_COMM1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_COMM1;
|
||||
|
||||
/** \brief FSI Communication Register 2 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_COMM2_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_COMM2;
|
||||
|
||||
/** \brief ECC Read Register DF */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_ECCRD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_ECCRD;
|
||||
|
||||
/** \brief ECC Read Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_ECCRP_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_ECCRP;
|
||||
|
||||
/** \brief ECC Write Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_ECCW_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_ECCW;
|
||||
|
||||
/** \brief Flash Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_FCON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_FCON;
|
||||
|
||||
/** \brief Flash Protection Control and Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_FPRO_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_FPRO;
|
||||
|
||||
/** \brief Flash Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_FSR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_FSR;
|
||||
|
||||
/** \brief Flash Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_ID;
|
||||
|
||||
/** \brief Margin Control Register DFlash */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_MARD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_MARD;
|
||||
|
||||
/** \brief Margin Control Register PFlash */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_MARP_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_MARP;
|
||||
|
||||
/** \brief DFlash Protection Configuration */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_PROCOND_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_PROCOND;
|
||||
|
||||
/** \brief Debug Interface Protection Configuration */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_PROCONDBG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_PROCONDBG;
|
||||
|
||||
/** \brief HSM Interface Configuration */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_PROCONHSM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_PROCONHSM;
|
||||
|
||||
/** \brief HSM Code Flash OTP Protection Configuration */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_PROCONHSMCOTP_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_PROCONHSMCOTP;
|
||||
|
||||
/** \brief OTP Protection Configuration */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_PROCONOTP_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_PROCONOTP;
|
||||
|
||||
/** \brief PFlash Protection Configuration */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_PROCONP_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_PROCONP;
|
||||
|
||||
/** \brief Write-Once Protection Configuration */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_PROCONWOP_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_PROCONWOP;
|
||||
|
||||
/** \brief Read Buffer Cfg 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_RDB_CFG0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_RDB_CFG0;
|
||||
|
||||
/** \brief Read Buffer Cfg 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_RDB_CFG1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_RDB_CFG1;
|
||||
|
||||
/** \brief Read Buffer Cfg 2 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_RDB_CFG2_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_RDB_CFG2;
|
||||
|
||||
/** \brief Requested Read Address Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_RRAD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_RRAD;
|
||||
|
||||
/** \brief Requested Read Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_RRCT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_RRCT;
|
||||
|
||||
/** \brief Requested Read Data Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_RRD0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_RRD0;
|
||||
|
||||
/** \brief Requested Read Data Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_RRD1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_RRD1;
|
||||
|
||||
/** \brief UBAB Configuration */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_UBAB_CFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_UBAB_CFG;
|
||||
|
||||
/** \brief UBAB Status */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_UBAB_STAT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_UBAB_STAT;
|
||||
|
||||
/** \brief UBAB FIFO TOP Entry */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_FLASH_UBAB_TOP_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_FLASH_UBAB_TOP;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Flash_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L1
|
||||
* \{ */
|
||||
|
||||
/** \brief Corrected Bits Address Buffer (CBAB) object */
|
||||
typedef volatile struct _Ifx_FLASH_CBAB
|
||||
{
|
||||
Ifx_FLASH_CBAB_CFG CFG; /**< \brief 0, CBAB Configuration */
|
||||
Ifx_FLASH_CBAB_STAT STAT; /**< \brief 4, CBAB Status */
|
||||
Ifx_FLASH_CBAB_TOP TOP; /**< \brief 8, CBAB FIFO TOP Entry */
|
||||
} Ifx_FLASH_CBAB;
|
||||
|
||||
/** \brief Read Buffer Configuration object */
|
||||
typedef volatile struct _Ifx_FLASH_RDB
|
||||
{
|
||||
Ifx_FLASH_RDB_CFG0 CFG0; /**< \brief 0, Read Buffer Cfg 0 */
|
||||
Ifx_FLASH_RDB_CFG1 CFG1; /**< \brief 4, Read Buffer Cfg 1 */
|
||||
Ifx_FLASH_RDB_CFG2 CFG2; /**< \brief 8, Read Buffer Cfg 2 */
|
||||
} Ifx_FLASH_RDB;
|
||||
|
||||
/** \brief Uncorrectable Bits Address Buffer (UBAB) object */
|
||||
typedef volatile struct _Ifx_FLASH_UBAB
|
||||
{
|
||||
Ifx_FLASH_UBAB_CFG CFG; /**< \brief 0, UBAB Configuration */
|
||||
Ifx_FLASH_UBAB_STAT STAT; /**< \brief 4, UBAB Status */
|
||||
Ifx_FLASH_UBAB_TOP TOP; /**< \brief 8, UBAB FIFO TOP Entry */
|
||||
} Ifx_FLASH_UBAB;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Flash_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief FLASH object. */
|
||||
typedef volatile struct _Ifx_FLASH
|
||||
{
|
||||
Ifx_FLASH_COMM0 COMM0; /**< \brief 0, FSI Communication Register 0 */
|
||||
Ifx_FLASH_COMM1 COMM1; /**< \brief 4, FSI Communication Register 1 */
|
||||
Ifx_FLASH_COMM2 COMM2; /**< \brief 8, FSI Communication Register 2 */
|
||||
unsigned char reserved_C[4092]; /**< \brief C, \internal Reserved */
|
||||
Ifx_FLASH_ID ID; /**< \brief 1008, Flash Module Identification Register */
|
||||
unsigned char reserved_100C[4]; /**< \brief 100C, \internal Reserved */
|
||||
Ifx_FLASH_FSR FSR; /**< \brief 1010, Flash Status Register */
|
||||
Ifx_FLASH_FCON FCON; /**< \brief 1014, Flash Configuration Register */
|
||||
unsigned char reserved_1018[4]; /**< \brief 1018, \internal Reserved */
|
||||
Ifx_FLASH_FPRO FPRO; /**< \brief 101C, Flash Protection Control and Status Register */
|
||||
Ifx_FLASH_PROCONP PROCONP[2]; /**< \brief 1020, PFlash Protection Configuration for ports */
|
||||
unsigned char reserved_1028[8]; /**< \brief 1028, \internal Reserved */
|
||||
Ifx_FLASH_PROCOND PROCOND; /**< \brief 1030, DFlash Protection Configuration */
|
||||
Ifx_FLASH_PROCONHSMCOTP PROCONHSMCOTP; /**< \brief 1034, HSM Code Flash OTP Protection Configuration */
|
||||
Ifx_FLASH_PROCONOTP PROCONOTP[2]; /**< \brief 1038, OTP Protection Configuration for ports */
|
||||
unsigned char reserved_1040[8]; /**< \brief 1040, \internal Reserved */
|
||||
Ifx_FLASH_PROCONWOP PROCONWOP[2]; /**< \brief 1048, Write-Once Protection Configuration for ports */
|
||||
unsigned char reserved_1050[8]; /**< \brief 1050, \internal Reserved */
|
||||
Ifx_FLASH_PROCONDBG PROCONDBG; /**< \brief 1058, Debug Interface Protection Configuration */
|
||||
Ifx_FLASH_PROCONHSM PROCONHSM; /**< \brief 105C, HSM Interface Configuration */
|
||||
Ifx_FLASH_RDB RDBCFG[2]; /**< \brief 1060, Read Buffer Configuration for ports */
|
||||
unsigned char reserved_1078[24]; /**< \brief 1078, \internal Reserved */
|
||||
Ifx_FLASH_ECCW ECCW; /**< \brief 1090, ECC Write Register */
|
||||
Ifx_FLASH_ECCRP ECCRP[2]; /**< \brief 1094, ECC Read Register for ports */
|
||||
unsigned char reserved_109C[8]; /**< \brief 109C, \internal Reserved */
|
||||
Ifx_FLASH_ECCRD ECCRD; /**< \brief 10A4, ECC Read Register DF */
|
||||
Ifx_FLASH_MARP MARP; /**< \brief 10A8, Margin Control Register PFlash */
|
||||
Ifx_FLASH_MARD MARD; /**< \brief 10AC, Margin Control Register DFlash */
|
||||
unsigned char reserved_10B0[4]; /**< \brief 10B0, \internal Reserved */
|
||||
Ifx_FLASH_CBAB CBAB[2]; /**< \brief 10B4, Corrected Bits Address Buffer for ports */
|
||||
unsigned char reserved_10CC[24]; /**< \brief 10CC, \internal Reserved */
|
||||
Ifx_FLASH_UBAB UBAB[2]; /**< \brief 10E4, Uncorrectable Bits Address Buffer for ports */
|
||||
unsigned char reserved_10FC[68]; /**< \brief 10FC, \internal Reserved */
|
||||
Ifx_FLASH_RRCT RRCT; /**< \brief 1140, Requested Read Control Register */
|
||||
Ifx_FLASH_RRD0 RRD0; /**< \brief 1144, Requested Read Data Register 0 */
|
||||
Ifx_FLASH_RRD1 RRD1; /**< \brief 1148, Requested Read Data Register 1 */
|
||||
Ifx_FLASH_RRAD RRAD; /**< \brief 114C, Requested Read Address Register */
|
||||
unsigned char reserved_1150[680]; /**< \brief 1150, \internal Reserved */
|
||||
Ifx_FLASH_ACCEN1 ACCEN1; /**< \brief 13F8, Access Enable Register 1 */
|
||||
Ifx_FLASH_ACCEN0 ACCEN0; /**< \brief 13FC, Access Enable Register 0 */
|
||||
} Ifx_FLASH;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXFLASH_REGDEF_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,111 +0,0 @@
|
||||
/**
|
||||
* \file IfxGpt12_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Gpt12_Cfg Gpt12 address
|
||||
* \ingroup IfxLld_Gpt12
|
||||
*
|
||||
* \defgroup IfxLld_Gpt12_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Gpt12_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Gpt12_Cfg_Gpt120 2-GPT120
|
||||
* \ingroup IfxLld_Gpt12_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXGPT12_REG_H
|
||||
#define IFXGPT12_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxGpt12_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Gpt12_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief GPT12 object */
|
||||
#define MODULE_GPT120 /*lint --e(923)*/ (*(Ifx_GPT12*)0xF0002E00u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Gpt12_Cfg_Gpt120
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define GPT120_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_GPT12_ACCEN0*)0xF0002EFCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define GPT120_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_GPT12_ACCEN1*)0xF0002EF8u)
|
||||
|
||||
/** \brief 30, Capture and Reload Register */
|
||||
#define GPT120_CAPREL /*lint --e(923)*/ (*(volatile Ifx_GPT12_CAPREL*)0xF0002E30u)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define GPT120_CLC /*lint --e(923)*/ (*(volatile Ifx_GPT12_CLC*)0xF0002E00u)
|
||||
|
||||
/** \brief 8, Identification Register */
|
||||
#define GPT120_ID /*lint --e(923)*/ (*(volatile Ifx_GPT12_ID*)0xF0002E08u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define GPT120_KRST0 /*lint --e(923)*/ (*(volatile Ifx_GPT12_KRST0*)0xF0002EF4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define GPT120_KRST1 /*lint --e(923)*/ (*(volatile Ifx_GPT12_KRST1*)0xF0002EF0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define GPT120_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_GPT12_KRSTCLR*)0xF0002EECu)
|
||||
|
||||
/** \brief E8, OCDS Control and Status Register */
|
||||
#define GPT120_OCS /*lint --e(923)*/ (*(volatile Ifx_GPT12_OCS*)0xF0002EE8u)
|
||||
|
||||
/** \brief 4, Port Input Select Register */
|
||||
#define GPT120_PISEL /*lint --e(923)*/ (*(volatile Ifx_GPT12_PISEL*)0xF0002E04u)
|
||||
|
||||
/** \brief 34, Timer T2 Register */
|
||||
#define GPT120_T2 /*lint --e(923)*/ (*(volatile Ifx_GPT12_T2*)0xF0002E34u)
|
||||
|
||||
/** \brief 10, Timer T2 Control Register */
|
||||
#define GPT120_T2CON /*lint --e(923)*/ (*(volatile Ifx_GPT12_T2CON*)0xF0002E10u)
|
||||
|
||||
/** \brief 38, Timer T3 Register */
|
||||
#define GPT120_T3 /*lint --e(923)*/ (*(volatile Ifx_GPT12_T3*)0xF0002E38u)
|
||||
|
||||
/** \brief 14, Timer T3 Control Register */
|
||||
#define GPT120_T3CON /*lint --e(923)*/ (*(volatile Ifx_GPT12_T3CON*)0xF0002E14u)
|
||||
|
||||
/** \brief 3C, Timer T4 Register */
|
||||
#define GPT120_T4 /*lint --e(923)*/ (*(volatile Ifx_GPT12_T4*)0xF0002E3Cu)
|
||||
|
||||
/** \brief 18, Timer T4 Control Register */
|
||||
#define GPT120_T4CON /*lint --e(923)*/ (*(volatile Ifx_GPT12_T4CON*)0xF0002E18u)
|
||||
|
||||
/** \brief 40, Timer T5 Register */
|
||||
#define GPT120_T5 /*lint --e(923)*/ (*(volatile Ifx_GPT12_T5*)0xF0002E40u)
|
||||
|
||||
/** \brief 1C, Timer T5 Control Register */
|
||||
#define GPT120_T5CON /*lint --e(923)*/ (*(volatile Ifx_GPT12_T5CON*)0xF0002E1Cu)
|
||||
|
||||
/** \brief 44, Timer T6 Register */
|
||||
#define GPT120_T6 /*lint --e(923)*/ (*(volatile Ifx_GPT12_T6*)0xF0002E44u)
|
||||
|
||||
/** \brief 20, Timer T6 Control Register */
|
||||
#define GPT120_T6CON /*lint --e(923)*/ (*(volatile Ifx_GPT12_T6CON*)0xF0002E20u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXGPT12_REG_H */
|
||||
@@ -1,487 +0,0 @@
|
||||
/**
|
||||
* \file IfxGpt12_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Gpt12 Gpt12
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Gpt12_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Gpt12
|
||||
*
|
||||
* \defgroup IfxLld_Gpt12_union Union
|
||||
* \ingroup IfxLld_Gpt12
|
||||
*
|
||||
* \defgroup IfxLld_Gpt12_struct Struct
|
||||
* \ingroup IfxLld_Gpt12
|
||||
*
|
||||
*/
|
||||
#ifndef IFXGPT12_REGDEF_H
|
||||
#define IFXGPT12_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Gpt12_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_GPT12_ACCEN0_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_GPT12_ACCEN0_Bits;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef struct _Ifx_GPT12_ACCEN1_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_ACCEN1_Bits;
|
||||
|
||||
/** \brief Capture and Reload Register */
|
||||
typedef struct _Ifx_GPT12_CAPREL_Bits
|
||||
{
|
||||
unsigned int CAPREL:16; /**< \brief [15:0] Current reload value or Captured value (rwh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_CAPREL_Bits;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef struct _Ifx_GPT12_CLC_Bits
|
||||
{
|
||||
unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
|
||||
unsigned int reserved_2:1; /**< \brief \internal Reserved */
|
||||
unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_CLC_Bits;
|
||||
|
||||
/** \brief Identification Register */
|
||||
typedef struct _Ifx_GPT12_ID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_GPT12_ID_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef struct _Ifx_GPT12_KRST0_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rw) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_KRST0_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef struct _Ifx_GPT12_KRST1_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_KRST1_Bits;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef struct _Ifx_GPT12_KRSTCLR_Bits
|
||||
{
|
||||
unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_KRSTCLR_Bits;
|
||||
|
||||
/** \brief OCDS Control and Status Register */
|
||||
typedef struct _Ifx_GPT12_OCS_Bits
|
||||
{
|
||||
unsigned int reserved_0:24; /**< \brief \internal Reserved */
|
||||
unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
|
||||
unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
|
||||
unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
|
||||
unsigned int reserved_30:2; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_OCS_Bits;
|
||||
|
||||
/** \brief Port Input Select Register */
|
||||
typedef struct _Ifx_GPT12_PISEL_Bits
|
||||
{
|
||||
unsigned int IST2IN:1; /**< \brief [0:0] Input Select for T2IN (rw) */
|
||||
unsigned int IST2EUD:1; /**< \brief [1:1] Input Select for T2EUD (rw) */
|
||||
unsigned int IST3IN:2; /**< \brief [3:2] Input Select for T3IN (rw) */
|
||||
unsigned int IST3EUD:2; /**< \brief [5:4] Input Select for T3EUD (rw) */
|
||||
unsigned int IST4IN:2; /**< \brief [7:6] Input Select for T4IN (rw) */
|
||||
unsigned int IST4EUD:2; /**< \brief [9:8] Input Select for T4EUD (rw) */
|
||||
unsigned int IST5IN:1; /**< \brief [10:10] Input Select for T5IN (rw) */
|
||||
unsigned int IST5EUD:1; /**< \brief [11:11] Input Select for T5EUD (rw) */
|
||||
unsigned int IST6IN:1; /**< \brief [12:12] Input Select for T6IN (rw) */
|
||||
unsigned int IST6EUD:1; /**< \brief [13:13] Input Select for T6EUD (rw) */
|
||||
unsigned int ISCAPIN:2; /**< \brief [15:14] Input Select for CAPIN (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_PISEL_Bits;
|
||||
|
||||
/** \brief Timer T2 Register */
|
||||
typedef struct _Ifx_GPT12_T2_Bits
|
||||
{
|
||||
unsigned int T2:16; /**< \brief [15:0] Timer T2 (rwh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_T2_Bits;
|
||||
|
||||
/** \brief Timer T2 Control Register */
|
||||
typedef struct _Ifx_GPT12_T2CON_Bits
|
||||
{
|
||||
unsigned int T2I:3; /**< \brief [2:0] Timer T2 Input Parameter Selection (rw) */
|
||||
unsigned int T2M:3; /**< \brief [5:3] Timer T2 Mode Control (Basic Operating Mode) (rw) */
|
||||
unsigned int T2R:1; /**< \brief [6:6] Timer T2 Run Bit (rw) */
|
||||
unsigned int T2UD:1; /**< \brief [7:7] Timer T2 Up/Down Control (rw) */
|
||||
unsigned int T2UDE:1; /**< \brief [8:8] Timer T2 External Up/Down Enable (rw) */
|
||||
unsigned int T2RC:1; /**< \brief [9:9] Timer T2 Remote Control (rw) */
|
||||
unsigned int reserved_10:2; /**< \brief \internal Reserved */
|
||||
unsigned int T2IRDIS:1; /**< \brief [12:12] Timer T2 Interrupt Disable (rw) */
|
||||
unsigned int T2EDGE:1; /**< \brief [13:13] Timer T2 Edge Detection (rwh) */
|
||||
unsigned int T2CHDIR:1; /**< \brief [14:14] Timer T2 Count Direction Change (rwh) */
|
||||
unsigned int T2RDIR:1; /**< \brief [15:15] Timer T2 Rotation Direction (rh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_T2CON_Bits;
|
||||
|
||||
/** \brief Timer T3 Register */
|
||||
typedef struct _Ifx_GPT12_T3_Bits
|
||||
{
|
||||
unsigned int T3:16; /**< \brief [15:0] Timer T3 (rwh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_T3_Bits;
|
||||
|
||||
/** \brief Timer T3 Control Register */
|
||||
typedef struct _Ifx_GPT12_T3CON_Bits
|
||||
{
|
||||
unsigned int T3I:3; /**< \brief [2:0] Timer T3 Input Parameter Selection (rw) */
|
||||
unsigned int T3M:3; /**< \brief [5:3] Timer T3 Mode Control (rw) */
|
||||
unsigned int T3R:1; /**< \brief [6:6] Timer T3 Run Bit (rw) */
|
||||
unsigned int T3UD:1; /**< \brief [7:7] Timer T3 Up/Down Control (rw) */
|
||||
unsigned int T3UDE:1; /**< \brief [8:8] Timer T3 External Up/Down Enable (rw) */
|
||||
unsigned int T3OE:1; /**< \brief [9:9] Overflow/Underflow Output Enable (rw) */
|
||||
unsigned int T3OTL:1; /**< \brief [10:10] Timer T3 Overflow Toggle Latch (rwh) */
|
||||
unsigned int BPS1:2; /**< \brief [12:11] GPT1 Block Prescaler Control (rw) */
|
||||
unsigned int T3EDGE:1; /**< \brief [13:13] Timer T3 Edge Detection Flag (rwh) */
|
||||
unsigned int T3CHDIR:1; /**< \brief [14:14] Timer T3 Count Direction Change Flag (rwh) */
|
||||
unsigned int T3RDIR:1; /**< \brief [15:15] Timer T3 Rotation Direction Flag (rh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_T3CON_Bits;
|
||||
|
||||
/** \brief Timer T4 Register */
|
||||
typedef struct _Ifx_GPT12_T4_Bits
|
||||
{
|
||||
unsigned int T4:16; /**< \brief [15:0] Timer T4 (rwh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_T4_Bits;
|
||||
|
||||
/** \brief Timer T4 Control Register */
|
||||
typedef struct _Ifx_GPT12_T4CON_Bits
|
||||
{
|
||||
unsigned int T4I:3; /**< \brief [2:0] Timer T4 Input Parameter Selection (rw) */
|
||||
unsigned int T4M:3; /**< \brief [5:3] Timer T4 Mode Control (Basic Operating Mode) (rw) */
|
||||
unsigned int T4R:1; /**< \brief [6:6] Timer T4 Run Bit (rw) */
|
||||
unsigned int T4UD:1; /**< \brief [7:7] Timer T4 Up/Down Control (rw) */
|
||||
unsigned int T4UDE:1; /**< \brief [8:8] Timer T4 External Up/Down Enable (rw) */
|
||||
unsigned int T4RC:1; /**< \brief [9:9] Timer T4 Remote Control (rw) */
|
||||
unsigned int CLRT2EN:1; /**< \brief [10:10] Clear Timer T2 Enable (rw) */
|
||||
unsigned int CLRT3EN:1; /**< \brief [11:11] Clear Timer T3 Enable (rw) */
|
||||
unsigned int T4IRDIS:1; /**< \brief [12:12] Timer T4 Interrupt Disable (rw) */
|
||||
unsigned int T4EDGE:1; /**< \brief [13:13] Timer T4 Edge Detection (rwh) */
|
||||
unsigned int T4CHDIR:1; /**< \brief [14:14] Timer T4 Count Direction Change (rwh) */
|
||||
unsigned int T4RDIR:1; /**< \brief [15:15] Timer T4 Rotation Direction (rh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_T4CON_Bits;
|
||||
|
||||
/** \brief Timer T5 Register */
|
||||
typedef struct _Ifx_GPT12_T5_Bits
|
||||
{
|
||||
unsigned int T5:16; /**< \brief [15:0] Timer T5 (rwh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_T5_Bits;
|
||||
|
||||
/** \brief Timer T5 Control Register */
|
||||
typedef struct _Ifx_GPT12_T5CON_Bits
|
||||
{
|
||||
unsigned int T5I:3; /**< \brief [2:0] Timer T5 Input Parameter Selection (rw) */
|
||||
unsigned int T5M:3; /**< \brief [5:3] Timer T5 Mode Control (Basic Operating Mode) (rw) */
|
||||
unsigned int T5R:1; /**< \brief [6:6] Timer T5 Run Bit (rw) */
|
||||
unsigned int T5UD:1; /**< \brief [7:7] Timer T5 Up/Down Control (rw) */
|
||||
unsigned int T5UDE:1; /**< \brief [8:8] Timer T5 External Up/Down Enable (rw) */
|
||||
unsigned int T5RC:1; /**< \brief [9:9] Timer T5 Remote Control (rw) */
|
||||
unsigned int CT3:1; /**< \brief [10:10] Timer T3 Capture Trigger Enable (rw) */
|
||||
unsigned int reserved_11:1; /**< \brief \internal Reserved */
|
||||
unsigned int CI:2; /**< \brief [13:12] Register CAPREL Capture Trigger Selection (rw) */
|
||||
unsigned int T5CLR:1; /**< \brief [14:14] Timer T5 Clear Enable Bit (rw) */
|
||||
unsigned int T5SC:1; /**< \brief [15:15] Timer T5 Capture Mode Enable (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_T5CON_Bits;
|
||||
|
||||
/** \brief Timer T6 Register */
|
||||
typedef struct _Ifx_GPT12_T6_Bits
|
||||
{
|
||||
unsigned int T6:16; /**< \brief [15:0] Timer T6 (rwh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_T6_Bits;
|
||||
|
||||
/** \brief Timer T6 Control Register */
|
||||
typedef struct _Ifx_GPT12_T6CON_Bits
|
||||
{
|
||||
unsigned int T6I:3; /**< \brief [2:0] Timer T6 Input Parameter Selection (rw) */
|
||||
unsigned int T6M:3; /**< \brief [5:3] Timer T6 Mode Control (Basic Operating Mode) (rw) */
|
||||
unsigned int T6R:1; /**< \brief [6:6] Timer T6 Run Bit (rw) */
|
||||
unsigned int T6UD:1; /**< \brief [7:7] Timer T6 Up/Down Control (rw) */
|
||||
unsigned int T6UDE:1; /**< \brief [8:8] Timer T6 External Up/Down Enable (rw) */
|
||||
unsigned int T6OE:1; /**< \brief [9:9] Overflow/Underflow Output Enable (rw) */
|
||||
unsigned int T6OTL:1; /**< \brief [10:10] Timer T6 Overflow Toggle Latch (rwh) */
|
||||
unsigned int BPS2:2; /**< \brief [12:11] GPT2 Block Prescaler Control (rw) */
|
||||
unsigned int reserved_13:1; /**< \brief \internal Reserved */
|
||||
unsigned int T6CLR:1; /**< \brief [14:14] Timer T6 Clear Enable Bit (rw) */
|
||||
unsigned int T6SR:1; /**< \brief [15:15] Timer T6 Reload Mode Enable (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_GPT12_T6CON_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Gpt12_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_ACCEN0;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_ACCEN1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_ACCEN1;
|
||||
|
||||
/** \brief Capture and Reload Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_CAPREL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_CAPREL;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_CLC;
|
||||
|
||||
/** \brief Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_ID;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_KRST0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_KRST0;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_KRST1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_KRST1;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_KRSTCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_KRSTCLR;
|
||||
|
||||
/** \brief OCDS Control and Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_OCS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_OCS;
|
||||
|
||||
/** \brief Port Input Select Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_PISEL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_PISEL;
|
||||
|
||||
/** \brief Timer T2 Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_T2_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_T2;
|
||||
|
||||
/** \brief Timer T2 Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_T2CON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_T2CON;
|
||||
|
||||
/** \brief Timer T3 Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_T3_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_T3;
|
||||
|
||||
/** \brief Timer T3 Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_T3CON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_T3CON;
|
||||
|
||||
/** \brief Timer T4 Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_T4_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_T4;
|
||||
|
||||
/** \brief Timer T4 Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_T4CON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_T4CON;
|
||||
|
||||
/** \brief Timer T5 Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_T5_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_T5;
|
||||
|
||||
/** \brief Timer T5 Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_T5CON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_T5CON;
|
||||
|
||||
/** \brief Timer T6 Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_T6_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_T6;
|
||||
|
||||
/** \brief Timer T6 Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_GPT12_T6CON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_GPT12_T6CON;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Gpt12_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief GPT12 object */
|
||||
typedef volatile struct _Ifx_GPT12
|
||||
{
|
||||
Ifx_GPT12_CLC CLC; /**< \brief 0, Clock Control Register */
|
||||
Ifx_GPT12_PISEL PISEL; /**< \brief 4, Port Input Select Register */
|
||||
Ifx_GPT12_ID ID; /**< \brief 8, Identification Register */
|
||||
unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
|
||||
Ifx_GPT12_T2CON T2CON; /**< \brief 10, Timer T2 Control Register */
|
||||
Ifx_GPT12_T3CON T3CON; /**< \brief 14, Timer T3 Control Register */
|
||||
Ifx_GPT12_T4CON T4CON; /**< \brief 18, Timer T4 Control Register */
|
||||
Ifx_GPT12_T5CON T5CON; /**< \brief 1C, Timer T5 Control Register */
|
||||
Ifx_GPT12_T6CON T6CON; /**< \brief 20, Timer T6 Control Register */
|
||||
unsigned char reserved_24[12]; /**< \brief 24, \internal Reserved */
|
||||
Ifx_GPT12_CAPREL CAPREL; /**< \brief 30, Capture and Reload Register */
|
||||
Ifx_GPT12_T2 T2; /**< \brief 34, Timer T2 Register */
|
||||
Ifx_GPT12_T3 T3; /**< \brief 38, Timer T3 Register */
|
||||
Ifx_GPT12_T4 T4; /**< \brief 3C, Timer T4 Register */
|
||||
Ifx_GPT12_T5 T5; /**< \brief 40, Timer T5 Register */
|
||||
Ifx_GPT12_T6 T6; /**< \brief 44, Timer T6 Register */
|
||||
unsigned char reserved_48[160]; /**< \brief 48, \internal Reserved */
|
||||
Ifx_GPT12_OCS OCS; /**< \brief E8, OCDS Control and Status Register */
|
||||
Ifx_GPT12_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
|
||||
Ifx_GPT12_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
|
||||
Ifx_GPT12_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
|
||||
Ifx_GPT12_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
|
||||
Ifx_GPT12_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
|
||||
} Ifx_GPT12;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXGPT12_REGDEF_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,117 +0,0 @@
|
||||
/**
|
||||
* \file IfxHsct_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Hsct_Cfg Hsct address
|
||||
* \ingroup IfxLld_Hsct
|
||||
*
|
||||
* \defgroup IfxLld_Hsct_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Hsct_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Hsct_Cfg_Hsct 2-HSCT
|
||||
* \ingroup IfxLld_Hsct_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXHSCT_REG_H
|
||||
#define IFXHSCT_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxHsct_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Hsct_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief HSCT object */
|
||||
#define MODULE_HSCT /*lint --e(923)*/ (*(Ifx_HSCT*)0xF0090000u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Hsct_Cfg_Hsct
|
||||
* \{ */
|
||||
|
||||
/** \brief FFFC, Access Enable Register 0 */
|
||||
#define HSCT_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_HSCT_ACCEN0*)0xF009FFFCu)
|
||||
|
||||
/** \brief FFF8, Access Enable Register 1 */
|
||||
#define HSCT_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_HSCT_ACCEN1*)0xF009FFF8u)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define HSCT_CLC /*lint --e(923)*/ (*(volatile Ifx_HSCT_CLC*)0xF0090000u)
|
||||
|
||||
/** \brief 30, Configuration physical layer register */
|
||||
#define HSCT_CONFIGPHY /*lint --e(923)*/ (*(volatile Ifx_HSCT_CONFIGPHY*)0xF0090030u)
|
||||
|
||||
/** \brief 1C, Clear To Send Control Register */
|
||||
#define HSCT_CTSCTRL /*lint --e(923)*/ (*(volatile Ifx_HSCT_CTSCTRL*)0xF009001Cu)
|
||||
|
||||
/** \brief 20, Transmission Disable Register */
|
||||
#define HSCT_DISABLE /*lint --e(923)*/ (*(volatile Ifx_HSCT_DISABLE*)0xF0090020u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define HSCT_ID /*lint --e(923)*/ (*(volatile Ifx_HSCT_ID*)0xF0090008u)
|
||||
|
||||
/** \brief 14, CPU transfer control register */
|
||||
#define HSCT_IFCTRL /*lint --e(923)*/ (*(volatile Ifx_HSCT_IFCTRL*)0xF0090014u)
|
||||
|
||||
/** \brief 28, Interface Status Register */
|
||||
#define HSCT_IFSTAT /*lint --e(923)*/ (*(volatile Ifx_HSCT_IFSTAT*)0xF0090028u)
|
||||
|
||||
/** \brief 10, Initialization register */
|
||||
#define HSCT_INIT /*lint --e(923)*/ (*(volatile Ifx_HSCT_INIT*)0xF0090010u)
|
||||
|
||||
/** \brief 40, Interrupt register */
|
||||
#define HSCT_IRQ /*lint --e(923)*/ (*(volatile Ifx_HSCT_IRQ*)0xF0090040u)
|
||||
|
||||
/** \brief 48, Interrupt clear register */
|
||||
#define HSCT_IRQCLR /*lint --e(923)*/ (*(volatile Ifx_HSCT_IRQCLR*)0xF0090048u)
|
||||
|
||||
/** \brief 44, Interrupt enable register */
|
||||
#define HSCT_IRQEN /*lint --e(923)*/ (*(volatile Ifx_HSCT_IRQEN*)0xF0090044u)
|
||||
|
||||
/** \brief FFF4, Reset Register 0 */
|
||||
#define HSCT_KRST0 /*lint --e(923)*/ (*(volatile Ifx_HSCT_KRST0*)0xF009FFF4u)
|
||||
|
||||
/** \brief FFF0, Reset Register 1 */
|
||||
#define HSCT_KRST1 /*lint --e(923)*/ (*(volatile Ifx_HSCT_KRST1*)0xF009FFF0u)
|
||||
|
||||
/** \brief FFEC, Reset Status Clear Register */
|
||||
#define HSCT_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_HSCT_KRSTCLR*)0xF009FFECu)
|
||||
|
||||
/** \brief FFE8, OCDS Control and Status */
|
||||
#define HSCT_OCS /*lint --e(923)*/ (*(volatile Ifx_HSCT_OCS*)0xF009FFE8u)
|
||||
|
||||
/** \brief 18, Sleep Control Register */
|
||||
#define HSCT_SLEEPCTRL /*lint --e(923)*/ (*(volatile Ifx_HSCT_SLEEPCTRL*)0xF0090018u)
|
||||
|
||||
/** \brief 24, Status Register */
|
||||
#define HSCT_STAT /*lint --e(923)*/ (*(volatile Ifx_HSCT_STAT*)0xF0090024u)
|
||||
|
||||
/** \brief 34, STATPHY */
|
||||
#define HSCT_STATPHY /*lint --e(923)*/ (*(volatile Ifx_HSCT_STATPHY*)0xF0090034u)
|
||||
|
||||
/** \brief 50, Unsolicited Status Message Received */
|
||||
#define HSCT_USMR /*lint --e(923)*/ (*(volatile Ifx_HSCT_USMR*)0xF0090050u)
|
||||
|
||||
/** \brief 54, Unsolicited Status Message Send */
|
||||
#define HSCT_USMS /*lint --e(923)*/ (*(volatile Ifx_HSCT_USMS*)0xF0090054u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXHSCT_REG_H */
|
||||
@@ -1,538 +0,0 @@
|
||||
/**
|
||||
* \file IfxHsct_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Hsct Hsct
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Hsct_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Hsct
|
||||
*
|
||||
* \defgroup IfxLld_Hsct_union Union
|
||||
* \ingroup IfxLld_Hsct
|
||||
*
|
||||
* \defgroup IfxLld_Hsct_struct Struct
|
||||
* \ingroup IfxLld_Hsct
|
||||
*
|
||||
*/
|
||||
#ifndef IFXHSCT_REGDEF_H
|
||||
#define IFXHSCT_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Hsct_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_HSCT_ACCEN0_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_HSCT_ACCEN0_Bits;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef struct _Ifx_HSCT_ACCEN1_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_ACCEN1_Bits;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef struct _Ifx_HSCT_CLC_Bits
|
||||
{
|
||||
unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (r) */
|
||||
unsigned int reserved_2:1; /**< \brief \internal Reserved */
|
||||
unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_CLC_Bits;
|
||||
|
||||
/** \brief Configuration physical layer register */
|
||||
typedef struct _Ifx_HSCT_CONFIGPHY_Bits
|
||||
{
|
||||
unsigned int reserved_0:1; /**< \brief \internal Reserved */
|
||||
unsigned int PLLPON:1; /**< \brief [1:1] PLL Power On (Master Mode only) (rw) */
|
||||
unsigned int PLLPE:6; /**< \brief [7:2] PLL phase enable - allows to enable/disable each of the 6 Phase outputs. (rw) */
|
||||
unsigned int PLLWMF:6; /**< \brief [13:8] PLL frequency control word multiplication factor (rw) */
|
||||
unsigned int PLLKPKI:1; /**< \brief [14:14] KP/KI Setting (rw) */
|
||||
unsigned int PHYRST:1; /**< \brief [15:15] Physical Layer Reset (rw) */
|
||||
unsigned int PLLKP:3; /**< \brief [18:16] KP of PLL - Configuration of PLL beta coefficients of proportional part of loop filter (rw) */
|
||||
unsigned int PLLKI:3; /**< \brief [21:19] KI of PLL - Configuration of PLL alpha coefficients of integral part of loop filter (rw) */
|
||||
unsigned int PLLIVR:4; /**< \brief [25:22] Adjustment for integrated voltage regulator (rw) */
|
||||
unsigned int reserved_26:2; /**< \brief \internal Reserved */
|
||||
unsigned int OSCCLKEN:1; /**< \brief [28:28] Enable Oscillator Clock as PLL reference clock (rw) */
|
||||
unsigned int reserved_29:3; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_CONFIGPHY_Bits;
|
||||
|
||||
/** \brief Clear To Send Control Register */
|
||||
typedef struct _Ifx_HSCT_CTSCTRL_Bits
|
||||
{
|
||||
unsigned int CTS_FRAME:1; /**< \brief [0:0] Transmit CTS Frame Generation (rw) */
|
||||
unsigned int CTS_TXD:1; /**< \brief [1:1] Disable TX CTS signaling (rw) */
|
||||
unsigned int CTS_RXD:1; /**< \brief [2:2] Disable RX CTS detection (rw) */
|
||||
unsigned int HSSL_CTS_FBD:1; /**< \brief [3:3] Disable HSSL interface CTS Frame Blocking (rw) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_CTSCTRL_Bits;
|
||||
|
||||
/** \brief Transmission Disable Register */
|
||||
typedef struct _Ifx_HSCT_DISABLE_Bits
|
||||
{
|
||||
unsigned int TX_DIS:1; /**< \brief [0:0] Disable HSCT Transmit path in Master interface (rw) */
|
||||
unsigned int RX_DIS:1; /**< \brief [1:1] Disable HSCT Receive path in Master interface (rw) */
|
||||
unsigned int RX_HEPD:1; /**< \brief [2:2] Disable RX Header Error Discard Payload data. (rw) */
|
||||
unsigned int reserved_3:29; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_DISABLE_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_HSCT_ID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_HSCT_ID_Bits;
|
||||
|
||||
/** \brief CPU transfer control register */
|
||||
typedef struct _Ifx_HSCT_IFCTRL_Bits
|
||||
{
|
||||
unsigned int IFCVS:8; /**< \brief [7:0] Master Mode - Interface Control Value to be send to Slave interface (rw) */
|
||||
unsigned int SIFCV:1; /**< \brief [8:8] Master Mode - Slave IF control frame trigger (w) */
|
||||
unsigned int reserved_9:7; /**< \brief \internal Reserved */
|
||||
unsigned int MRXSPEED:2; /**< \brief [17:16] Master Mode RX speed (rw) */
|
||||
unsigned int MTXSPEED:2; /**< \brief [19:18] Master Mode TX speed (rw) */
|
||||
unsigned int IFTESTMD:1; /**< \brief [20:20] Master Mode Interface Test Mode (rw) */
|
||||
unsigned int reserved_21:11; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_IFCTRL_Bits;
|
||||
|
||||
/** \brief Interface Status Register */
|
||||
typedef struct _Ifx_HSCT_IFSTAT_Bits
|
||||
{
|
||||
unsigned int RX_STAT:3; /**< \brief [2:0] HSCT slave interface Status for RX link (rh) */
|
||||
unsigned int TX_STAT:2; /**< \brief [4:3] HSCT slave interface Status for TX link (rh) */
|
||||
unsigned int reserved_5:27; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_IFSTAT_Bits;
|
||||
|
||||
/** \brief Initialization register */
|
||||
typedef struct _Ifx_HSCT_INIT_Bits
|
||||
{
|
||||
unsigned int reserved_0:1; /**< \brief \internal Reserved */
|
||||
unsigned int SYS_CLK_EN:1; /**< \brief [1:1] Enable SysClk in Master interface (rw) */
|
||||
unsigned int SRCF:1; /**< \brief [2:2] Select SysClk / Reference Clock Frequency rate (rw) */
|
||||
unsigned int IFM:1; /**< \brief [3:3] Select Interface Mode (rw) */
|
||||
unsigned int reserved_4:6; /**< \brief \internal Reserved */
|
||||
unsigned int LHLR:1; /**< \brief [10:10] Loopback path at Slave interface side at higher layer system RAM. (rw) */
|
||||
unsigned int reserved_11:5; /**< \brief \internal Reserved */
|
||||
unsigned int TXHD:3; /**< \brief [18:16] Transmit High Speed Divider. (rw) */
|
||||
unsigned int RXHD:3; /**< \brief [21:19] Receive High Speed Divider. (rw) */
|
||||
unsigned int reserved_22:10; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_INIT_Bits;
|
||||
|
||||
/** \brief Interrupt register */
|
||||
typedef struct _Ifx_HSCT_IRQ_Bits
|
||||
{
|
||||
unsigned int reserved_0:1; /**< \brief \internal Reserved */
|
||||
unsigned int HER:1; /**< \brief [1:1] Header error detected (rh) */
|
||||
unsigned int PYER:1; /**< \brief [2:2] Payload error detected (rh) */
|
||||
unsigned int CER:1; /**< \brief [3:3] HSCT command error (rh) */
|
||||
unsigned int IFCFS:1; /**< \brief [4:4] HSCT interface control frame send (rh) */
|
||||
unsigned int SMER:1; /**< \brief [5:5] Speed Mode Switch Error (Master Mode only) (rh) */
|
||||
unsigned int USMSF:1; /**< \brief [6:6] Unsolicited message frame send finished (rh) */
|
||||
unsigned int PLER:1; /**< \brief [7:7] PLL lost lock error (rh) */
|
||||
unsigned int USM:1; /**< \brief [8:8] Unsolicited Message Received (rh) */
|
||||
unsigned int PAR:1; /**< \brief [9:9] PING Answer Received (rh) */
|
||||
unsigned int TXTE:1; /**< \brief [10:10] TX transfer error occurred on a disabled TX channel. (rh) */
|
||||
unsigned int SFO:1; /**< \brief [11:11] Synchronization FIFO overflow (in RX direction) (rh) */
|
||||
unsigned int SFU:1; /**< \brief [12:12] Synchronization FIFO underflow (in TX direction) (rh) */
|
||||
unsigned int reserved_13:19; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_IRQ_Bits;
|
||||
|
||||
/** \brief Interrupt clear register */
|
||||
typedef struct _Ifx_HSCT_IRQCLR_Bits
|
||||
{
|
||||
unsigned int reserved_0:1; /**< \brief \internal Reserved */
|
||||
unsigned int HERCLR:1; /**< \brief [1:1] Header error detected interrupt clear (w) */
|
||||
unsigned int PYERCLR:1; /**< \brief [2:2] Payload error detected interrupt clear (w) */
|
||||
unsigned int CERCLR:1; /**< \brief [3:3] HSCT command error interrupt clear (w) */
|
||||
unsigned int IFCFSCLR:1; /**< \brief [4:4] HSCT interface control command send interrupt clear (w) */
|
||||
unsigned int SMERCLR:1; /**< \brief [5:5] Speed Mode Switch Error interrupt clear (w) */
|
||||
unsigned int USMSFCLR:1; /**< \brief [6:6] Unsolicited message frame send finished interrupt clear (w) */
|
||||
unsigned int PLERCLR:1; /**< \brief [7:7] PLL lost lock error interrupt clear (w) */
|
||||
unsigned int USMCLR:1; /**< \brief [8:8] Unsolicited Message received clear (w) */
|
||||
unsigned int PARCLR:1; /**< \brief [9:9] PING Answer received clear (w) */
|
||||
unsigned int TXTECLR:1; /**< \brief [10:10] TX disable error interrupt clear (w) */
|
||||
unsigned int SFOCLR:1; /**< \brief [11:11] Synchronization FIFO overflow (in RX direction) interrupt clear (w) */
|
||||
unsigned int SFUCLR:1; /**< \brief [12:12] Synchronization FIFO underflow (in TX direction) interrupt clear (w) */
|
||||
unsigned int reserved_13:19; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_IRQCLR_Bits;
|
||||
|
||||
/** \brief Interrupt enable register */
|
||||
typedef struct _Ifx_HSCT_IRQEN_Bits
|
||||
{
|
||||
unsigned int reserved_0:1; /**< \brief \internal Reserved */
|
||||
unsigned int HEREN:1; /**< \brief [1:1] Header error detected interrupt enable (rw) */
|
||||
unsigned int PYEREN:1; /**< \brief [2:2] Payload error detected interrupt enable (rw) */
|
||||
unsigned int CEREN:1; /**< \brief [3:3] HSCT command error interrupt enable (rw) */
|
||||
unsigned int IFCFSEN:1; /**< \brief [4:4] HSCT interface control command send enable (rw) */
|
||||
unsigned int SMEREN:1; /**< \brief [5:5] Speed Mode Switch Error interrupt enable (rw) */
|
||||
unsigned int USMSFEN:1; /**< \brief [6:6] Unsolicited message frame send finished (rw) */
|
||||
unsigned int PLEREN:1; /**< \brief [7:7] PLL lost lock error interrupt enable (rw) */
|
||||
unsigned int USMEN:1; /**< \brief [8:8] Unsolicited Message received enable (rw) */
|
||||
unsigned int PAREN:1; /**< \brief [9:9] PING Answer Received enable (rw) */
|
||||
unsigned int TXTEEN:1; /**< \brief [10:10] TX disable error interrupt enable (rw) */
|
||||
unsigned int SFOEN:1; /**< \brief [11:11] Synchronization FIFO overflow (in RX direction) interrupt enable (rw) */
|
||||
unsigned int SFUEN:1; /**< \brief [12:12] Synchronization FIFO underflow (in TX direction) interrupt enable (rw) */
|
||||
unsigned int reserved_13:19; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_IRQEN_Bits;
|
||||
|
||||
/** \brief Reset Register 0 */
|
||||
typedef struct _Ifx_HSCT_KRST0_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_KRST0_Bits;
|
||||
|
||||
/** \brief Reset Register 1 */
|
||||
typedef struct _Ifx_HSCT_KRST1_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_KRST1_Bits;
|
||||
|
||||
/** \brief Reset Status Clear Register */
|
||||
typedef struct _Ifx_HSCT_KRSTCLR_Bits
|
||||
{
|
||||
unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_KRSTCLR_Bits;
|
||||
|
||||
/** \brief OCDS Control and Status */
|
||||
typedef struct _Ifx_HSCT_OCS_Bits
|
||||
{
|
||||
unsigned int TGS:2; /**< \brief [1:0] Trigger Set for OTGB0/1 (rw) */
|
||||
unsigned int TGB:1; /**< \brief [2:2] OTGB0/1 Bus Select (rw) */
|
||||
unsigned int TG_P:1; /**< \brief [3:3] TGS, TGB Write Protection (w) */
|
||||
unsigned int reserved_4:20; /**< \brief \internal Reserved */
|
||||
unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
|
||||
unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
|
||||
unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
|
||||
unsigned int reserved_30:2; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_OCS_Bits;
|
||||
|
||||
/** \brief Sleep Control Register */
|
||||
typedef struct _Ifx_HSCT_SLEEPCTRL_Bits
|
||||
{
|
||||
unsigned int SLPEN:1; /**< \brief [0:0] Sleep mode enabled (rw) */
|
||||
unsigned int SLPCLKG:1; /**< \brief [1:1] Clock Gating in Sleep Mode (rw) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_SLEEPCTRL_Bits;
|
||||
|
||||
/** \brief Status Register */
|
||||
typedef struct _Ifx_HSCT_STAT_Bits
|
||||
{
|
||||
unsigned int RX_PSIZE:3; /**< \brief [2:0] RX (receiving) Payload Size (rh) */
|
||||
unsigned int RX_CHANNEL:4; /**< \brief [6:3] RX (receiving) Logical Channel Type (rh) */
|
||||
unsigned int RX_SLEEP:1; /**< \brief [7:7] RX (receiving) Sleep Mode Status (rh) */
|
||||
unsigned int TX_SLEEP:1; /**< \brief [8:8] TX (transmitting) Sleep Mode Status (rh) */
|
||||
unsigned int reserved_9:3; /**< \brief \internal Reserved */
|
||||
unsigned int TX_PSIZE:3; /**< \brief [14:12] Transmission Payload Size (rh) */
|
||||
unsigned int reserved_15:1; /**< \brief \internal Reserved */
|
||||
unsigned int TX_CHANNEL_TYPE:4; /**< \brief [19:16] Transmission Logical Channel Type (rh) */
|
||||
unsigned int reserved_20:4; /**< \brief \internal Reserved */
|
||||
unsigned int LIFCCMDR:8; /**< \brief [31:24] Last Interface Control Command Received (rh) */
|
||||
} Ifx_HSCT_STAT_Bits;
|
||||
|
||||
/** \brief STATPHY */
|
||||
typedef struct _Ifx_HSCT_STATPHY_Bits
|
||||
{
|
||||
unsigned int PLOCK:1; /**< \brief [0:0] PLL locked (rh) */
|
||||
unsigned int RXLSA:1; /**< \brief [1:1] Receiver in Low speed (rh) */
|
||||
unsigned int TXLSA:1; /**< \brief [2:2] Transmitter in Low speed (rh) */
|
||||
unsigned int reserved_3:29; /**< \brief \internal Reserved */
|
||||
} Ifx_HSCT_STATPHY_Bits;
|
||||
|
||||
/** \brief Unsolicited Status Message Received */
|
||||
typedef struct _Ifx_HSCT_USMR_Bits
|
||||
{
|
||||
unsigned int USMR:32; /**< \brief [31:0] Unsolicited status message received (rh) */
|
||||
} Ifx_HSCT_USMR_Bits;
|
||||
|
||||
/** \brief Unsolicited Status Message Send */
|
||||
typedef struct _Ifx_HSCT_USMS_Bits
|
||||
{
|
||||
unsigned int USMS:32; /**< \brief [31:0] Unsolicited status message send (rw) */
|
||||
} Ifx_HSCT_USMS_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Hsct_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_ACCEN0;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_ACCEN1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_ACCEN1;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_CLC;
|
||||
|
||||
/** \brief Configuration physical layer register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_CONFIGPHY_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_CONFIGPHY;
|
||||
|
||||
/** \brief Clear To Send Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_CTSCTRL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_CTSCTRL;
|
||||
|
||||
/** \brief Transmission Disable Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_DISABLE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_DISABLE;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_ID;
|
||||
|
||||
/** \brief CPU transfer control register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_IFCTRL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_IFCTRL;
|
||||
|
||||
/** \brief Interface Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_IFSTAT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_IFSTAT;
|
||||
|
||||
/** \brief Initialization register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_INIT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_INIT;
|
||||
|
||||
/** \brief Interrupt register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_IRQ_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_IRQ;
|
||||
|
||||
/** \brief Interrupt clear register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_IRQCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_IRQCLR;
|
||||
|
||||
/** \brief Interrupt enable register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_IRQEN_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_IRQEN;
|
||||
|
||||
/** \brief Reset Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_KRST0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_KRST0;
|
||||
|
||||
/** \brief Reset Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_KRST1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_KRST1;
|
||||
|
||||
/** \brief Reset Status Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_KRSTCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_KRSTCLR;
|
||||
|
||||
/** \brief OCDS Control and Status */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_OCS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_OCS;
|
||||
|
||||
/** \brief Sleep Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_SLEEPCTRL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_SLEEPCTRL;
|
||||
|
||||
/** \brief Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_STAT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_STAT;
|
||||
|
||||
/** \brief STATPHY */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_STATPHY_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_STATPHY;
|
||||
|
||||
/** \brief Unsolicited Status Message Received */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_USMR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_USMR;
|
||||
|
||||
/** \brief Unsolicited Status Message Send */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSCT_USMS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSCT_USMS;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Hsct_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief HSCT object */
|
||||
typedef volatile struct _Ifx_HSCT
|
||||
{
|
||||
Ifx_HSCT_CLC CLC; /**< \brief 0, Clock Control Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_HSCT_ID ID; /**< \brief 8, Module Identification Register */
|
||||
unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
|
||||
Ifx_HSCT_INIT INIT; /**< \brief 10, Initialization register */
|
||||
Ifx_HSCT_IFCTRL IFCTRL; /**< \brief 14, CPU transfer control register */
|
||||
Ifx_HSCT_SLEEPCTRL SLEEPCTRL; /**< \brief 18, Sleep Control Register */
|
||||
Ifx_HSCT_CTSCTRL CTSCTRL; /**< \brief 1C, Clear To Send Control Register */
|
||||
Ifx_HSCT_DISABLE DISABLE; /**< \brief 20, Transmission Disable Register */
|
||||
Ifx_HSCT_STAT STAT; /**< \brief 24, Status Register */
|
||||
Ifx_HSCT_IFSTAT IFSTAT; /**< \brief 28, Interface Status Register */
|
||||
unsigned char reserved_2C[4]; /**< \brief 2C, \internal Reserved */
|
||||
Ifx_HSCT_CONFIGPHY CONFIGPHY; /**< \brief 30, Configuration physical layer register */
|
||||
Ifx_HSCT_STATPHY STATPHY; /**< \brief 34, STATPHY */
|
||||
unsigned char reserved_38[8]; /**< \brief 38, \internal Reserved */
|
||||
Ifx_HSCT_IRQ IRQ; /**< \brief 40, Interrupt register */
|
||||
Ifx_HSCT_IRQEN IRQEN; /**< \brief 44, Interrupt enable register */
|
||||
Ifx_HSCT_IRQCLR IRQCLR; /**< \brief 48, Interrupt clear register */
|
||||
unsigned char reserved_4C[4]; /**< \brief 4C, \internal Reserved */
|
||||
Ifx_HSCT_USMR USMR; /**< \brief 50, Unsolicited Status Message Received */
|
||||
Ifx_HSCT_USMS USMS; /**< \brief 54, Unsolicited Status Message Send */
|
||||
unsigned char reserved_58[65424]; /**< \brief 58, \internal Reserved */
|
||||
Ifx_HSCT_OCS OCS; /**< \brief FFE8, OCDS Control and Status */
|
||||
Ifx_HSCT_KRSTCLR KRSTCLR; /**< \brief FFEC, Reset Status Clear Register */
|
||||
Ifx_HSCT_KRST1 KRST1; /**< \brief FFF0, Reset Register 1 */
|
||||
Ifx_HSCT_KRST0 KRST0; /**< \brief FFF4, Reset Register 0 */
|
||||
Ifx_HSCT_ACCEN1 ACCEN1; /**< \brief FFF8, Access Enable Register 1 */
|
||||
Ifx_HSCT_ACCEN0 ACCEN0; /**< \brief FFFC, Access Enable Register 0 */
|
||||
} Ifx_HSCT;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXHSCT_REGDEF_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,428 +0,0 @@
|
||||
/**
|
||||
* \file IfxHssl_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Hssl_Cfg Hssl address
|
||||
* \ingroup IfxLld_Hssl
|
||||
*
|
||||
* \defgroup IfxLld_Hssl_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Hssl_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Hssl_Cfg_Hssl 2-HSSL
|
||||
* \ingroup IfxLld_Hssl_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXHSSL_REG_H
|
||||
#define IFXHSSL_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxHssl_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Hssl_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief HSSL object */
|
||||
#define MODULE_HSSL /*lint --e(923)*/ (*(Ifx_HSSL*)0xF0080000u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Hssl_Cfg_Hssl
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define HSSL_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_HSSL_ACCEN0*)0xF00800FCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define HSSL_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_HSSL_ACCEN1*)0xF00800F8u)
|
||||
|
||||
/** \brief E0, Access Rules Register */
|
||||
#define HSSL_AR /*lint --e(923)*/ (*(volatile Ifx_HSSL_AR*)0xF00800E0u)
|
||||
|
||||
/** \brief C4, Access Window End Register */
|
||||
#define HSSL_AW0_AWEND /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWEND*)0xF00800C4u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_AW0_AWEND.
|
||||
* To use register names with standard convension, please use HSSL_AW0_AWEND.
|
||||
*/
|
||||
#define HSSL_AWEND0 (HSSL_AW0_AWEND)
|
||||
|
||||
/** \brief C0, Access Window Start Register */
|
||||
#define HSSL_AW0_AWSTART /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWSTART*)0xF00800C0u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_AW0_AWSTART.
|
||||
* To use register names with standard convension, please use HSSL_AW0_AWSTART.
|
||||
*/
|
||||
#define HSSL_AWSTART0 (HSSL_AW0_AWSTART)
|
||||
|
||||
/** \brief CC, Access Window End Register */
|
||||
#define HSSL_AW1_AWEND /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWEND*)0xF00800CCu)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_AW1_AWEND.
|
||||
* To use register names with standard convension, please use HSSL_AW1_AWEND.
|
||||
*/
|
||||
#define HSSL_AWEND1 (HSSL_AW1_AWEND)
|
||||
|
||||
/** \brief C8, Access Window Start Register */
|
||||
#define HSSL_AW1_AWSTART /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWSTART*)0xF00800C8u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_AW1_AWSTART.
|
||||
* To use register names with standard convension, please use HSSL_AW1_AWSTART.
|
||||
*/
|
||||
#define HSSL_AWSTART1 (HSSL_AW1_AWSTART)
|
||||
|
||||
/** \brief D4, Access Window End Register */
|
||||
#define HSSL_AW2_AWEND /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWEND*)0xF00800D4u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_AW2_AWEND.
|
||||
* To use register names with standard convension, please use HSSL_AW2_AWEND.
|
||||
*/
|
||||
#define HSSL_AWEND2 (HSSL_AW2_AWEND)
|
||||
|
||||
/** \brief D0, Access Window Start Register */
|
||||
#define HSSL_AW2_AWSTART /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWSTART*)0xF00800D0u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_AW2_AWSTART.
|
||||
* To use register names with standard convension, please use HSSL_AW2_AWSTART.
|
||||
*/
|
||||
#define HSSL_AWSTART2 (HSSL_AW2_AWSTART)
|
||||
|
||||
/** \brief DC, Access Window End Register */
|
||||
#define HSSL_AW3_AWEND /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWEND*)0xF00800DCu)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_AW3_AWEND.
|
||||
* To use register names with standard convension, please use HSSL_AW3_AWEND.
|
||||
*/
|
||||
#define HSSL_AWEND3 (HSSL_AW3_AWEND)
|
||||
|
||||
/** \brief D8, Access Window Start Register */
|
||||
#define HSSL_AW3_AWSTART /*lint --e(923)*/ (*(volatile Ifx_HSSL_AW_AWSTART*)0xF00800D8u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_AW3_AWSTART.
|
||||
* To use register names with standard convension, please use HSSL_AW3_AWSTART.
|
||||
*/
|
||||
#define HSSL_AWSTART3 (HSSL_AW3_AWSTART)
|
||||
|
||||
/** \brief 10, Configuration Register */
|
||||
#define HSSL_CFG /*lint --e(923)*/ (*(volatile Ifx_HSSL_CFG*)0xF0080010u)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define HSSL_CLC /*lint --e(923)*/ (*(volatile Ifx_HSSL_CLC*)0xF0080000u)
|
||||
|
||||
/** \brief C, CRC Control Register */
|
||||
#define HSSL_CRC /*lint --e(923)*/ (*(volatile Ifx_HSSL_CRC*)0xF008000Cu)
|
||||
|
||||
/** \brief 34, Initiator Control Data Register */
|
||||
#define HSSL_I0_ICON /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_ICON*)0xF0080034u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I0_ICON.
|
||||
* To use register names with standard convension, please use HSSL_I0_ICON.
|
||||
*/
|
||||
#define HSSL_ICON0 (HSSL_I0_ICON)
|
||||
|
||||
/** \brief 3C, Initiator Read Data Register */
|
||||
#define HSSL_I0_IRD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRD*)0xF008003Cu)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I0_IRD.
|
||||
* To use register names with standard convension, please use HSSL_I0_IRD.
|
||||
*/
|
||||
#define HSSL_IRD0 (HSSL_I0_IRD)
|
||||
|
||||
/** \brief 38, Initiator Read Write Address Register */
|
||||
#define HSSL_I0_IRWA /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRWA*)0xF0080038u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I0_IRWA.
|
||||
* To use register names with standard convension, please use HSSL_I0_IRWA.
|
||||
*/
|
||||
#define HSSL_IRWA0 (HSSL_I0_IRWA)
|
||||
|
||||
/** \brief 30, Initiator Write Data Register */
|
||||
#define HSSL_I0_IWD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IWD*)0xF0080030u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I0_IWD.
|
||||
* To use register names with standard convension, please use HSSL_I0_IWD.
|
||||
*/
|
||||
#define HSSL_IWD0 (HSSL_I0_IWD)
|
||||
|
||||
/** \brief 44, Initiator Control Data Register */
|
||||
#define HSSL_I1_ICON /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_ICON*)0xF0080044u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I1_ICON.
|
||||
* To use register names with standard convension, please use HSSL_I1_ICON.
|
||||
*/
|
||||
#define HSSL_ICON1 (HSSL_I1_ICON)
|
||||
|
||||
/** \brief 4C, Initiator Read Data Register */
|
||||
#define HSSL_I1_IRD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRD*)0xF008004Cu)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I1_IRD.
|
||||
* To use register names with standard convension, please use HSSL_I1_IRD.
|
||||
*/
|
||||
#define HSSL_IRD1 (HSSL_I1_IRD)
|
||||
|
||||
/** \brief 48, Initiator Read Write Address Register */
|
||||
#define HSSL_I1_IRWA /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRWA*)0xF0080048u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I1_IRWA.
|
||||
* To use register names with standard convension, please use HSSL_I1_IRWA.
|
||||
*/
|
||||
#define HSSL_IRWA1 (HSSL_I1_IRWA)
|
||||
|
||||
/** \brief 40, Initiator Write Data Register */
|
||||
#define HSSL_I1_IWD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IWD*)0xF0080040u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I1_IWD.
|
||||
* To use register names with standard convension, please use HSSL_I1_IWD.
|
||||
*/
|
||||
#define HSSL_IWD1 (HSSL_I1_IWD)
|
||||
|
||||
/** \brief 54, Initiator Control Data Register */
|
||||
#define HSSL_I2_ICON /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_ICON*)0xF0080054u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I2_ICON.
|
||||
* To use register names with standard convension, please use HSSL_I2_ICON.
|
||||
*/
|
||||
#define HSSL_ICON2 (HSSL_I2_ICON)
|
||||
|
||||
/** \brief 5C, Initiator Read Data Register */
|
||||
#define HSSL_I2_IRD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRD*)0xF008005Cu)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I2_IRD.
|
||||
* To use register names with standard convension, please use HSSL_I2_IRD.
|
||||
*/
|
||||
#define HSSL_IRD2 (HSSL_I2_IRD)
|
||||
|
||||
/** \brief 58, Initiator Read Write Address Register */
|
||||
#define HSSL_I2_IRWA /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRWA*)0xF0080058u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I2_IRWA.
|
||||
* To use register names with standard convension, please use HSSL_I2_IRWA.
|
||||
*/
|
||||
#define HSSL_IRWA2 (HSSL_I2_IRWA)
|
||||
|
||||
/** \brief 50, Initiator Write Data Register */
|
||||
#define HSSL_I2_IWD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IWD*)0xF0080050u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I2_IWD.
|
||||
* To use register names with standard convension, please use HSSL_I2_IWD.
|
||||
*/
|
||||
#define HSSL_IWD2 (HSSL_I2_IWD)
|
||||
|
||||
/** \brief 64, Initiator Control Data Register */
|
||||
#define HSSL_I3_ICON /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_ICON*)0xF0080064u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I3_ICON.
|
||||
* To use register names with standard convension, please use HSSL_I3_ICON.
|
||||
*/
|
||||
#define HSSL_ICON3 (HSSL_I3_ICON)
|
||||
|
||||
/** \brief 6C, Initiator Read Data Register */
|
||||
#define HSSL_I3_IRD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRD*)0xF008006Cu)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I3_IRD.
|
||||
* To use register names with standard convension, please use HSSL_I3_IRD.
|
||||
*/
|
||||
#define HSSL_IRD3 (HSSL_I3_IRD)
|
||||
|
||||
/** \brief 68, Initiator Read Write Address Register */
|
||||
#define HSSL_I3_IRWA /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IRWA*)0xF0080068u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I3_IRWA.
|
||||
* To use register names with standard convension, please use HSSL_I3_IRWA.
|
||||
*/
|
||||
#define HSSL_IRWA3 (HSSL_I3_IRWA)
|
||||
|
||||
/** \brief 60, Initiator Write Data Register */
|
||||
#define HSSL_I3_IWD /*lint --e(923)*/ (*(volatile Ifx_HSSL_I_IWD*)0xF0080060u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_I3_IWD.
|
||||
* To use register names with standard convension, please use HSSL_I3_IWD.
|
||||
*/
|
||||
#define HSSL_IWD3 (HSSL_I3_IWD)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define HSSL_ID /*lint --e(923)*/ (*(volatile Ifx_HSSL_ID*)0xF0080008u)
|
||||
|
||||
/** \brief A8, Initiator Stream Current Address Register */
|
||||
#define HSSL_IS_CA /*lint --e(923)*/ (*(volatile Ifx_HSSL_IS_CA*)0xF00800A8u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_IS_CA.
|
||||
* To use register names with standard convension, please use HSSL_IS_CA.
|
||||
*/
|
||||
#define HSSL_ISCA (HSSL_IS_CA)
|
||||
|
||||
/** \brief AC, Initiator Stream Frame Count Register */
|
||||
#define HSSL_IS_FC /*lint --e(923)*/ (*(volatile Ifx_HSSL_IS_FC*)0xF00800ACu)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_IS_FC.
|
||||
* To use register names with standard convension, please use HSSL_IS_FC.
|
||||
*/
|
||||
#define HSSL_ISFC (HSSL_IS_FC)
|
||||
|
||||
/** \brief A0, Initiator Stream Start Address Register */
|
||||
#define HSSL_IS_SA0 /*lint --e(923)*/ (*(volatile Ifx_HSSL_ISSA*)0xF00800A0u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_IS_SA0.
|
||||
* To use register names with standard convension, please use HSSL_IS_SA0.
|
||||
*/
|
||||
#define HSSL_ISSA0 (HSSL_IS_SA0)
|
||||
|
||||
/** \brief A4, Initiator Stream Start Address Register */
|
||||
#define HSSL_IS_SA1 /*lint --e(923)*/ (*(volatile Ifx_HSSL_ISSA*)0xF00800A4u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_IS_SA1.
|
||||
* To use register names with standard convension, please use HSSL_IS_SA1.
|
||||
*/
|
||||
#define HSSL_ISSA1 (HSSL_IS_SA1)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define HSSL_KRST0 /*lint --e(923)*/ (*(volatile Ifx_HSSL_KRST0*)0xF00800F4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define HSSL_KRST1 /*lint --e(923)*/ (*(volatile Ifx_HSSL_KRST1*)0xF00800F0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define HSSL_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_HSSL_KRSTCLR*)0xF00800ECu)
|
||||
|
||||
/** \brief 18, Miscellaneous Flags Register */
|
||||
#define HSSL_MFLAGS /*lint --e(923)*/ (*(volatile Ifx_HSSL_MFLAGS*)0xF0080018u)
|
||||
|
||||
/** \brief 20, Miscellaneous Flags Clear Register */
|
||||
#define HSSL_MFLAGSCL /*lint --e(923)*/ (*(volatile Ifx_HSSL_MFLAGSCL*)0xF0080020u)
|
||||
|
||||
/** \brief 24, Flags Enable Register */
|
||||
#define HSSL_MFLAGSEN /*lint --e(923)*/ (*(volatile Ifx_HSSL_MFLAGSEN*)0xF0080024u)
|
||||
|
||||
/** \brief 1C, Miscellaneous Flags Set Register */
|
||||
#define HSSL_MFLAGSSET /*lint --e(923)*/ (*(volatile Ifx_HSSL_MFLAGSSET*)0xF008001Cu)
|
||||
|
||||
/** \brief E8, OCDS Control and Status */
|
||||
#define HSSL_OCS /*lint --e(923)*/ (*(volatile Ifx_HSSL_OCS*)0xF00800E8u)
|
||||
|
||||
/** \brief 14, Request Flags Register */
|
||||
#define HSSL_QFLAGS /*lint --e(923)*/ (*(volatile Ifx_HSSL_QFLAGS*)0xF0080014u)
|
||||
|
||||
/** \brief 28, Stream FIFOs Status Flags Register */
|
||||
#define HSSL_SFSFLAGS /*lint --e(923)*/ (*(volatile Ifx_HSSL_SFSFLAGS*)0xF0080028u)
|
||||
|
||||
/** \brief 74, Target Current Address Register */
|
||||
#define HSSL_T0_TCA /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCA*)0xF0080074u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_T0_TCA.
|
||||
* To use register names with standard convension, please use HSSL_T0_TCA.
|
||||
*/
|
||||
#define HSSL_TCA0 (HSSL_T0_TCA)
|
||||
|
||||
/** \brief 70, Target Current Data Register */
|
||||
#define HSSL_T0_TCD /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCD*)0xF0080070u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_T0_TCD.
|
||||
* To use register names with standard convension, please use HSSL_T0_TCD.
|
||||
*/
|
||||
#define HSSL_TCD0 (HSSL_T0_TCD)
|
||||
|
||||
/** \brief 7C, Target Current Address Register */
|
||||
#define HSSL_T1_TCA /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCA*)0xF008007Cu)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_T1_TCA.
|
||||
* To use register names with standard convension, please use HSSL_T1_TCA.
|
||||
*/
|
||||
#define HSSL_TCA1 (HSSL_T1_TCA)
|
||||
|
||||
/** \brief 78, Target Current Data Register */
|
||||
#define HSSL_T1_TCD /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCD*)0xF0080078u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_T1_TCD.
|
||||
* To use register names with standard convension, please use HSSL_T1_TCD.
|
||||
*/
|
||||
#define HSSL_TCD1 (HSSL_T1_TCD)
|
||||
|
||||
/** \brief 84, Target Current Address Register */
|
||||
#define HSSL_T2_TCA /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCA*)0xF0080084u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_T2_TCA.
|
||||
* To use register names with standard convension, please use HSSL_T2_TCA.
|
||||
*/
|
||||
#define HSSL_TCA2 (HSSL_T2_TCA)
|
||||
|
||||
/** \brief 80, Target Current Data Register */
|
||||
#define HSSL_T2_TCD /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCD*)0xF0080080u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_T2_TCD.
|
||||
* To use register names with standard convension, please use HSSL_T2_TCD.
|
||||
*/
|
||||
#define HSSL_TCD2 (HSSL_T2_TCD)
|
||||
|
||||
/** \brief 8C, Target Current Address Register */
|
||||
#define HSSL_T3_TCA /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCA*)0xF008008Cu)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_T3_TCA.
|
||||
* To use register names with standard convension, please use HSSL_T3_TCA.
|
||||
*/
|
||||
#define HSSL_TCA3 (HSSL_T3_TCA)
|
||||
|
||||
/** \brief 88, Target Current Data Register */
|
||||
#define HSSL_T3_TCD /*lint --e(923)*/ (*(volatile Ifx_HSSL_T_TCD*)0xF0080088u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_T3_TCD.
|
||||
* To use register names with standard convension, please use HSSL_T3_TCD.
|
||||
*/
|
||||
#define HSSL_TCD3 (HSSL_T3_TCD)
|
||||
|
||||
/** \brief 94, Target ID Address Register */
|
||||
#define HSSL_TIDADD /*lint --e(923)*/ (*(volatile Ifx_HSSL_TIDADD*)0xF0080094u)
|
||||
|
||||
/** \brief B8, Target Stream Current Address Register */
|
||||
#define HSSL_TS_CA /*lint --e(923)*/ (*(volatile Ifx_HSSL_TS_CA*)0xF00800B8u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_TS_CA.
|
||||
* To use register names with standard convension, please use HSSL_TS_CA.
|
||||
*/
|
||||
#define HSSL_TSCA (HSSL_TS_CA)
|
||||
|
||||
/** \brief BC, Target Stream Frame Count Register */
|
||||
#define HSSL_TS_FC /*lint --e(923)*/ (*(volatile Ifx_HSSL_TS_FC*)0xF00800BCu)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_TS_FC.
|
||||
* To use register names with standard convension, please use HSSL_TS_FC.
|
||||
*/
|
||||
#define HSSL_TSFC (HSSL_TS_FC)
|
||||
|
||||
/** \brief B0, Target Stream Start Address Register */
|
||||
#define HSSL_TS_SA0 /*lint --e(923)*/ (*(volatile Ifx_HSSL_TSSA*)0xF00800B0u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_TS_SA0.
|
||||
* To use register names with standard convension, please use HSSL_TS_SA0.
|
||||
*/
|
||||
#define HSSL_TSSA0 (HSSL_TS_SA0)
|
||||
|
||||
/** \brief B4, Target Stream Start Address Register */
|
||||
#define HSSL_TS_SA1 /*lint --e(923)*/ (*(volatile Ifx_HSSL_TSSA*)0xF00800B4u)
|
||||
|
||||
/** Alias (User Manual Name) for HSSL_TS_SA1.
|
||||
* To use register names with standard convension, please use HSSL_TS_SA1.
|
||||
*/
|
||||
#define HSSL_TSSA1 (HSSL_TS_SA1)
|
||||
|
||||
/** \brief 90, Target Status Register */
|
||||
#define HSSL_TSTAT /*lint --e(923)*/ (*(volatile Ifx_HSSL_TSTAT*)0xF0080090u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXHSSL_REG_H */
|
||||
@@ -1,772 +0,0 @@
|
||||
/**
|
||||
* \file IfxHssl_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Hssl Hssl
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Hssl_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Hssl
|
||||
*
|
||||
* \defgroup IfxLld_Hssl_union Union
|
||||
* \ingroup IfxLld_Hssl
|
||||
*
|
||||
* \defgroup IfxLld_Hssl_struct Struct
|
||||
* \ingroup IfxLld_Hssl
|
||||
*
|
||||
*/
|
||||
#ifndef IFXHSSL_REGDEF_H
|
||||
#define IFXHSSL_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Hssl_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_HSSL_ACCEN0_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_HSSL_ACCEN0_Bits;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef struct _Ifx_HSSL_ACCEN1_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_HSSL_ACCEN1_Bits;
|
||||
|
||||
/** \brief Access Rules Register */
|
||||
typedef struct _Ifx_HSSL_AR_Bits
|
||||
{
|
||||
unsigned int ARW0:2; /**< \brief [1:0] Access Rule for Window 0 (rw) */
|
||||
unsigned int ARW1:2; /**< \brief [3:2] Access Rule for Window 1 (rw) */
|
||||
unsigned int ARW2:2; /**< \brief [5:4] Access Rule for Window 2 (rw) */
|
||||
unsigned int ARW3:2; /**< \brief [7:6] Access Rule for Window 3 (rw) */
|
||||
unsigned int reserved_8:8; /**< \brief \internal Reserved */
|
||||
unsigned int MAVCH:2; /**< \brief [17:16] Memory Access Violation Channel (rh) */
|
||||
unsigned int reserved_18:14; /**< \brief \internal Reserved */
|
||||
} Ifx_HSSL_AR_Bits;
|
||||
|
||||
/** \brief Access Window End Register */
|
||||
typedef struct _Ifx_HSSL_AW_AWEND_Bits
|
||||
{
|
||||
unsigned int reserved_0:8; /**< \brief \internal Reserved */
|
||||
unsigned int AWE:24; /**< \brief [31:8] Access Window End Address (rw) */
|
||||
} Ifx_HSSL_AW_AWEND_Bits;
|
||||
|
||||
/** \brief Access Window Start Register */
|
||||
typedef struct _Ifx_HSSL_AW_AWSTART_Bits
|
||||
{
|
||||
unsigned int reserved_0:8; /**< \brief \internal Reserved */
|
||||
unsigned int AWS:24; /**< \brief [31:8] Access Window Start Address (rw) */
|
||||
} Ifx_HSSL_AW_AWSTART_Bits;
|
||||
|
||||
/** \brief Configuration Register */
|
||||
typedef struct _Ifx_HSSL_CFG_Bits
|
||||
{
|
||||
unsigned int PREDIV:14; /**< \brief [13:0] Global Predivider (rw) */
|
||||
unsigned int reserved_14:2; /**< \brief \internal Reserved */
|
||||
unsigned int SMT:1; /**< \brief [16:16] Streaming Mode Transmitter (rw) */
|
||||
unsigned int SMR:1; /**< \brief [17:17] Streaming Mode Receiver (rw) */
|
||||
unsigned int SCM:1; /**< \brief [18:18] Streaming Channel Mode (rw) */
|
||||
unsigned int CCC:1; /**< \brief [19:19] Channel Code Control (rw) */
|
||||
unsigned int reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_HSSL_CFG_Bits;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef struct _Ifx_HSSL_CLC_Bits
|
||||
{
|
||||
unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
|
||||
unsigned int reserved_2:1; /**< \brief \internal Reserved */
|
||||
unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_HSSL_CLC_Bits;
|
||||
|
||||
/** \brief CRC Control Register */
|
||||
typedef struct _Ifx_HSSL_CRC_Bits
|
||||
{
|
||||
unsigned int XORMASK:16; /**< \brief [15:0] Value to be XORed with the Calculated CRC (rw) */
|
||||
unsigned int XEN:1; /**< \brief [16:16] Enable the Error Injection via XORMASK (rw) */
|
||||
unsigned int reserved_17:15; /**< \brief \internal Reserved */
|
||||
} Ifx_HSSL_CRC_Bits;
|
||||
|
||||
/** \brief Initiator Control Data Register */
|
||||
typedef struct _Ifx_HSSL_I_ICON_Bits
|
||||
{
|
||||
unsigned int IDQ:1; /**< \brief [0:0] Read ID Request (w) */
|
||||
unsigned int TQ:1; /**< \brief [1:1] Trigger Request (w) */
|
||||
unsigned int LETT:3; /**< \brief [4:2] Last Error Transaction Tag (rh) */
|
||||
unsigned int CETT:3; /**< \brief [7:5] Currently Expected Transaction Tag (rh) */
|
||||
unsigned int TOCV:8; /**< \brief [15:8] Time Out Current Value (rh) */
|
||||
unsigned int DATLEN:2; /**< \brief [17:16] Data Length (rw) */
|
||||
unsigned int RWT:2; /**< \brief [19:18] Read Write Trigger Command Type (rw) */
|
||||
unsigned int BSY:1; /**< \brief [20:20] Channel Busy (rh) */
|
||||
unsigned int ITTAG:3; /**< \brief [23:21] Initiator Transaction Tag (rh) */
|
||||
unsigned int TOREL:8; /**< \brief [31:24] Time Out Reload Value (rw) */
|
||||
} Ifx_HSSL_I_ICON_Bits;
|
||||
|
||||
/** \brief Initiator Read Data Register */
|
||||
typedef struct _Ifx_HSSL_I_IRD_Bits
|
||||
{
|
||||
unsigned int DATA:32; /**< \brief [31:0] Data Delivered by a Read Response Frame (rh) */
|
||||
} Ifx_HSSL_I_IRD_Bits;
|
||||
|
||||
/** \brief Initiator Read Write Address Register */
|
||||
typedef struct _Ifx_HSSL_I_IRWA_Bits
|
||||
{
|
||||
unsigned int ADDRESS:32; /**< \brief [31:0] Address Part of the Payload of a Write Frame (rw) */
|
||||
} Ifx_HSSL_I_IRWA_Bits;
|
||||
|
||||
/** \brief Initiator Write Data Register */
|
||||
typedef struct _Ifx_HSSL_I_IWD_Bits
|
||||
{
|
||||
unsigned int DATA:32; /**< \brief [31:0] Data Part of the Payload of a Write Frame (rw) */
|
||||
} Ifx_HSSL_I_IWD_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_HSSL_ID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_HSSL_ID_Bits;
|
||||
|
||||
/** \brief Initiator Stream Current Address Register */
|
||||
typedef struct _Ifx_HSSL_IS_CA_Bits
|
||||
{
|
||||
unsigned int reserved_0:5; /**< \brief \internal Reserved */
|
||||
unsigned int CURR:27; /**< \brief [31:5] Address of the Memory Location for the Current Transfer (rh) */
|
||||
} Ifx_HSSL_IS_CA_Bits;
|
||||
|
||||
/** \brief Initiator Stream Frame Count Register */
|
||||
typedef struct _Ifx_HSSL_IS_FC_Bits
|
||||
{
|
||||
unsigned int RELCOUNT:16; /**< \brief [15:0] Reload Count Number (rw) */
|
||||
unsigned int CURCOUNT:16; /**< \brief [31:16] Current Count Number (rh) */
|
||||
} Ifx_HSSL_IS_FC_Bits;
|
||||
|
||||
/** \brief Initiator Stream Start Address Register */
|
||||
typedef struct _Ifx_HSSL_ISSA_Bits
|
||||
{
|
||||
unsigned int reserved_0:5; /**< \brief \internal Reserved */
|
||||
unsigned int START:27; /**< \brief [31:5] Start Address for the Memory Range (rw) */
|
||||
} Ifx_HSSL_ISSA_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef struct _Ifx_HSSL_KRST0_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_HSSL_KRST0_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef struct _Ifx_HSSL_KRST1_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_HSSL_KRST1_Bits;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef struct _Ifx_HSSL_KRSTCLR_Bits
|
||||
{
|
||||
unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_HSSL_KRSTCLR_Bits;
|
||||
|
||||
/** \brief Miscellaneous Flags Register */
|
||||
typedef struct _Ifx_HSSL_MFLAGS_Bits
|
||||
{
|
||||
unsigned int NACK:4; /**< \brief [3:0] Not Acknowledge Error - Target Error (rh) */
|
||||
unsigned int TTE:4; /**< \brief [7:4] Transaction Tag Error (rh) */
|
||||
unsigned int TIMEOUT:4; /**< \brief [11:8] Timeout Error (rh) */
|
||||
unsigned int UNEXPECTED:4; /**< \brief [15:12] Unexpected Type of Frame Error (rh) */
|
||||
unsigned int reserved_16:2; /**< \brief \internal Reserved */
|
||||
unsigned int TMB:1; /**< \brief [18:18] Target Memory Block (rh) */
|
||||
unsigned int IMB:1; /**< \brief [19:19] Initiator Memory Block (rh) */
|
||||
unsigned int ISB:1; /**< \brief [20:20] Initiator Stream Block Request (rh) */
|
||||
unsigned int MAV:1; /**< \brief [21:21] Memory Access Violation (rh) */
|
||||
unsigned int SRIE:1; /**< \brief [22:22] SRI/SPB Bus Access Error (rh) */
|
||||
unsigned int PIE1:1; /**< \brief [23:23] PHY Inconsistency Error 1 (rh) */
|
||||
unsigned int PIE2:1; /**< \brief [24:24] PHY Inconsistency Error 2 (rh) */
|
||||
unsigned int CRCE:1; /**< \brief [25:25] CRC Error (rh) */
|
||||
unsigned int reserved_26:2; /**< \brief \internal Reserved */
|
||||
unsigned int TSE:1; /**< \brief [28:28] Target Stream Enable (rh) */
|
||||
unsigned int TEI:1; /**< \brief [29:29] Transmit Enable Input (rh) */
|
||||
unsigned int TEO:1; /**< \brief [30:30] Transmit Enable Output (rh) */
|
||||
unsigned int INI:1; /**< \brief [31:31] Initialize Mode (rh) */
|
||||
} Ifx_HSSL_MFLAGS_Bits;
|
||||
|
||||
/** \brief Miscellaneous Flags Clear Register */
|
||||
typedef struct _Ifx_HSSL_MFLAGSCL_Bits
|
||||
{
|
||||
unsigned int NACKC:4; /**< \brief [3:0] NACK Flags Clear (w) */
|
||||
unsigned int TTEC:4; /**< \brief [7:4] Transaction Tag Error Flags Clear (w) */
|
||||
unsigned int TIMEOUTC:4; /**< \brief [11:8] Timeout Error Flags Clear (w) */
|
||||
unsigned int UNEXPECTEDC:4; /**< \brief [15:12] Unexpected Error Flags Clear (w) */
|
||||
unsigned int reserved_16:2; /**< \brief \internal Reserved */
|
||||
unsigned int TMBC:1; /**< \brief [18:18] Target Memory Block Flag Clear (w) */
|
||||
unsigned int IMBC:1; /**< \brief [19:19] Initiator Memory Block Flag Clear (w) */
|
||||
unsigned int ISBC:1; /**< \brief [20:20] Initiator Stream Block Request Clear (w) */
|
||||
unsigned int MAVC:1; /**< \brief [21:21] MAV Flag Clear (w) */
|
||||
unsigned int SRIEC:1; /**< \brief [22:22] SRI/SPB Bus Access Error Flag Clear (w) */
|
||||
unsigned int PIE1C:1; /**< \brief [23:23] PIE1 Error Flag Clear (w) */
|
||||
unsigned int PIE2C:1; /**< \brief [24:24] PIE2 Error Flag Clear (w) */
|
||||
unsigned int CRCEC:1; /**< \brief [25:25] CRC Error Flag Clear (w) */
|
||||
unsigned int reserved_26:2; /**< \brief \internal Reserved */
|
||||
unsigned int TSEC:1; /**< \brief [28:28] Target Stream Enable Flag Clear (w) */
|
||||
unsigned int reserved_29:1; /**< \brief \internal Reserved */
|
||||
unsigned int TEOC:1; /**< \brief [30:30] Transmit Enable Flag Clear (w) */
|
||||
unsigned int INIC:1; /**< \brief [31:31] Initialize Mode Flag Clear (w) */
|
||||
} Ifx_HSSL_MFLAGSCL_Bits;
|
||||
|
||||
/** \brief Flags Enable Register */
|
||||
typedef struct _Ifx_HSSL_MFLAGSEN_Bits
|
||||
{
|
||||
unsigned int NACKEN:4; /**< \brief [3:0] Not Acknowledge Error Enable Bits (rw) */
|
||||
unsigned int TTEEN:4; /**< \brief [7:4] Transaction Tag Error Enable Bits (rw) */
|
||||
unsigned int TIMEOUTEN:4; /**< \brief [11:8] Timeout Error Enable Bits (rw) */
|
||||
unsigned int UNEXPECTEDEN:4; /**< \brief [15:12] Unexpected Error Enable Bits (rw) */
|
||||
unsigned int reserved_16:5; /**< \brief \internal Reserved */
|
||||
unsigned int MAVEN:1; /**< \brief [21:21] MAV Enable Bit (rw) */
|
||||
unsigned int SRIEEN:1; /**< \brief [22:22] SRI/SPB Bus Access Error Enable Bit (rw) */
|
||||
unsigned int PIE1EN:1; /**< \brief [23:23] PIE1 Error Enable Bit (rw) */
|
||||
unsigned int PIE2EN:1; /**< \brief [24:24] PIE2 Error Enable Bit (rw) */
|
||||
unsigned int CRCEEN:1; /**< \brief [25:25] CRC Error Enable Bit (rw) */
|
||||
unsigned int reserved_26:3; /**< \brief \internal Reserved */
|
||||
unsigned int TEIEN:1; /**< \brief [29:29] TEI Enable Bit (rw) */
|
||||
unsigned int reserved_30:2; /**< \brief \internal Reserved */
|
||||
} Ifx_HSSL_MFLAGSEN_Bits;
|
||||
|
||||
/** \brief Miscellaneous Flags Set Register */
|
||||
typedef struct _Ifx_HSSL_MFLAGSSET_Bits
|
||||
{
|
||||
unsigned int NACKS:4; /**< \brief [3:0] NACK Flags Set (w) */
|
||||
unsigned int TTES:4; /**< \brief [7:4] Transaction Tag Error Flags Set (w) */
|
||||
unsigned int TIMEOUTS:4; /**< \brief [11:8] Timeout Error Flags Set (w) */
|
||||
unsigned int UNEXPECTEDS:4; /**< \brief [15:12] Unexpected Error Flags Set (w) */
|
||||
unsigned int reserved_16:2; /**< \brief \internal Reserved */
|
||||
unsigned int TMBS:1; /**< \brief [18:18] Target Memory Block Flag Set (w) */
|
||||
unsigned int IMBS:1; /**< \brief [19:19] Initiator Memory Block Flag Set (w) */
|
||||
unsigned int ISBS:1; /**< \brief [20:20] Initiator Stream Block Request Set (w) */
|
||||
unsigned int MAVS:1; /**< \brief [21:21] MAV Flag Set (w) */
|
||||
unsigned int SRIES:1; /**< \brief [22:22] SRI/SPB Bus Access Error Flag Set (w) */
|
||||
unsigned int PIE1S:1; /**< \brief [23:23] PIE1 Error Flag Set (w) */
|
||||
unsigned int PIE2S:1; /**< \brief [24:24] PIE2 Error Flag Set (w) */
|
||||
unsigned int CRCES:1; /**< \brief [25:25] CRC Error Flag Set (w) */
|
||||
unsigned int reserved_26:2; /**< \brief \internal Reserved */
|
||||
unsigned int TSES:1; /**< \brief [28:28] Target Stream Enable Flag Set (w) */
|
||||
unsigned int reserved_29:1; /**< \brief \internal Reserved */
|
||||
unsigned int TEOS:1; /**< \brief [30:30] Transmit Enable Flag Set (w) */
|
||||
unsigned int INIS:1; /**< \brief [31:31] Initialize Mode Flag Set (w) */
|
||||
} Ifx_HSSL_MFLAGSSET_Bits;
|
||||
|
||||
/** \brief OCDS Control and Status */
|
||||
typedef struct _Ifx_HSSL_OCS_Bits
|
||||
{
|
||||
unsigned int TGS:2; /**< \brief [1:0] Trigger Set for OTGB0/1 (rw) */
|
||||
unsigned int TGB:1; /**< \brief [2:2] OTGB0/1 Bus Select (rw) */
|
||||
unsigned int TG_P:1; /**< \brief [3:3] TGS, TGB Write Protection (w) */
|
||||
unsigned int reserved_4:20; /**< \brief \internal Reserved */
|
||||
unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
|
||||
unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
|
||||
unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
|
||||
unsigned int reserved_30:2; /**< \brief \internal Reserved */
|
||||
} Ifx_HSSL_OCS_Bits;
|
||||
|
||||
/** \brief Request Flags Register */
|
||||
typedef struct _Ifx_HSSL_QFLAGS_Bits
|
||||
{
|
||||
unsigned int I:4; /**< \brief [3:0] Request Flags for Initiated Commands (rh) */
|
||||
unsigned int T:4; /**< \brief [7:4] Request Flags for Commands Arrived at Target (rh) */
|
||||
unsigned int R:4; /**< \brief [11:8] Request Flags for Response Frames at the Target (rh) */
|
||||
unsigned int reserved_12:4; /**< \brief \internal Reserved */
|
||||
unsigned int E0:2; /**< \brief [17:16] Expect Flags for Activated Timeout Timer 0 (rh) */
|
||||
unsigned int E1:2; /**< \brief [19:18] Expect Flags for Activated Timeout Timer 1 (rh) */
|
||||
unsigned int E2:2; /**< \brief [21:20] Expect Flags for Activated Timeout Timer 2 (rh) */
|
||||
unsigned int E3:2; /**< \brief [23:22] Expect Flags for Activated Timeout Timer 3 (rh) */
|
||||
unsigned int reserved_24:4; /**< \brief \internal Reserved */
|
||||
unsigned int IS:1; /**< \brief [28:28] I Flag for Stream Frames (rh) */
|
||||
unsigned int RS:1; /**< \brief [29:29] R Flag for Stream Frames (rh) */
|
||||
unsigned int TS:1; /**< \brief [30:30] T Flag for Stream Frames (rh) */
|
||||
unsigned int ES:1; /**< \brief [31:31] E Flag for Stream Frames (rh) */
|
||||
} Ifx_HSSL_QFLAGS_Bits;
|
||||
|
||||
/** \brief Stream FIFOs Status Flags Register */
|
||||
typedef struct _Ifx_HSSL_SFSFLAGS_Bits
|
||||
{
|
||||
unsigned int RXFL:2; /**< \brief [1:0] Stream RxFIFO Filling Level (rh) */
|
||||
unsigned int TXFL:2; /**< \brief [3:2] Stream TxFIFO Filling Level (rh) */
|
||||
unsigned int EXFL:2; /**< \brief [5:4] Stream Expect FIFO Filling Level (rh) */
|
||||
unsigned int reserved_6:9; /**< \brief \internal Reserved */
|
||||
unsigned int ISF:1; /**< \brief [15:15] Initiator Stream Frame Request (rh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_HSSL_SFSFLAGS_Bits;
|
||||
|
||||
/** \brief Target Current Address Register */
|
||||
typedef struct _Ifx_HSSL_T_TCA_Bits
|
||||
{
|
||||
unsigned int A:32; /**< \brief [31:0] Address Part of the Payload of a Write Command Frame or a Read Command Frame or ID Frame (rh) */
|
||||
} Ifx_HSSL_T_TCA_Bits;
|
||||
|
||||
/** \brief Target Current Data Register */
|
||||
typedef struct _Ifx_HSSL_T_TCD_Bits
|
||||
{
|
||||
unsigned int D:32; /**< \brief [31:0] Data Part of the Payload of a Write Command Frame or Read Data of a Read Command Frame (rh) */
|
||||
} Ifx_HSSL_T_TCD_Bits;
|
||||
|
||||
/** \brief Target ID Address Register */
|
||||
typedef struct _Ifx_HSSL_TIDADD_Bits
|
||||
{
|
||||
unsigned int A:32; /**< \brief [31:0] Address Pointer (rw) */
|
||||
} Ifx_HSSL_TIDADD_Bits;
|
||||
|
||||
/** \brief Target Stream Current Address Register */
|
||||
typedef struct _Ifx_HSSL_TS_CA_Bits
|
||||
{
|
||||
unsigned int reserved_0:5; /**< \brief \internal Reserved */
|
||||
unsigned int CURR:27; /**< \brief [31:5] Address of the Memory Location for the Current Transfer (rh) */
|
||||
} Ifx_HSSL_TS_CA_Bits;
|
||||
|
||||
/** \brief Target Stream Frame Count Register */
|
||||
typedef struct _Ifx_HSSL_TS_FC_Bits
|
||||
{
|
||||
unsigned int RELCOUNT:16; /**< \brief [15:0] Reload Count Number (rw) */
|
||||
unsigned int CURCOUNT:16; /**< \brief [31:16] Current Count Number (rh) */
|
||||
} Ifx_HSSL_TS_FC_Bits;
|
||||
|
||||
/** \brief Target Stream Start Address Register */
|
||||
typedef struct _Ifx_HSSL_TSSA_Bits
|
||||
{
|
||||
unsigned int reserved_0:5; /**< \brief \internal Reserved */
|
||||
unsigned int ADDR:27; /**< \brief [31:5] Start Address for the Memory Range (rw) */
|
||||
} Ifx_HSSL_TSSA_Bits;
|
||||
|
||||
/** \brief Target Status Register */
|
||||
typedef struct _Ifx_HSSL_TSTAT_Bits
|
||||
{
|
||||
unsigned int LASTCC0:5; /**< \brief [4:0] Last Command Code (rh) */
|
||||
unsigned int LASTTT0:3; /**< \brief [7:5] Last Transaction Tag (rh) */
|
||||
unsigned int LASTCC1:5; /**< \brief [12:8] Last Command Code (rh) */
|
||||
unsigned int LASTTT1:3; /**< \brief [15:13] Last Transaction Tag (rh) */
|
||||
unsigned int LASTCC2:5; /**< \brief [20:16] Last Command Code (rh) */
|
||||
unsigned int LASTTT2:3; /**< \brief [23:21] Last Transaction Tag (rh) */
|
||||
unsigned int LASTCC3:5; /**< \brief [28:24] Last Command Code (rh) */
|
||||
unsigned int LASTTT3:3; /**< \brief [31:29] Last Transaction Tag (rh) */
|
||||
} Ifx_HSSL_TSTAT_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Hssl_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_ACCEN0;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_ACCEN1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_ACCEN1;
|
||||
|
||||
/** \brief Access Rules Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_AR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_AR;
|
||||
|
||||
/** \brief Access Window End Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_AW_AWEND_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_AW_AWEND;
|
||||
|
||||
/** \brief Access Window Start Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_AW_AWSTART_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_AW_AWSTART;
|
||||
|
||||
/** \brief Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_CFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_CFG;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_CLC;
|
||||
|
||||
/** \brief CRC Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_CRC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_CRC;
|
||||
|
||||
/** \brief Initiator Control Data Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_I_ICON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_I_ICON;
|
||||
|
||||
/** \brief Initiator Read Data Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_I_IRD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_I_IRD;
|
||||
|
||||
/** \brief Initiator Read Write Address Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_I_IRWA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_I_IRWA;
|
||||
|
||||
/** \brief Initiator Write Data Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_I_IWD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_I_IWD;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_ID;
|
||||
|
||||
/** \brief Initiator Stream Current Address Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_IS_CA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_IS_CA;
|
||||
|
||||
/** \brief Initiator Stream Frame Count Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_IS_FC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_IS_FC;
|
||||
|
||||
/** \brief Initiator Stream Start Address Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_ISSA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_ISSA;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_KRST0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_KRST0;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_KRST1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_KRST1;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_KRSTCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_KRSTCLR;
|
||||
|
||||
/** \brief Miscellaneous Flags Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_MFLAGS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_MFLAGS;
|
||||
|
||||
/** \brief Miscellaneous Flags Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_MFLAGSCL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_MFLAGSCL;
|
||||
|
||||
/** \brief Flags Enable Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_MFLAGSEN_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_MFLAGSEN;
|
||||
|
||||
/** \brief Miscellaneous Flags Set Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_MFLAGSSET_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_MFLAGSSET;
|
||||
|
||||
/** \brief OCDS Control and Status */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_OCS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_OCS;
|
||||
|
||||
/** \brief Request Flags Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_QFLAGS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_QFLAGS;
|
||||
|
||||
/** \brief Stream FIFOs Status Flags Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_SFSFLAGS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_SFSFLAGS;
|
||||
|
||||
/** \brief Target Current Address Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_T_TCA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_T_TCA;
|
||||
|
||||
/** \brief Target Current Data Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_T_TCD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_T_TCD;
|
||||
|
||||
/** \brief Target ID Address Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_TIDADD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_TIDADD;
|
||||
|
||||
/** \brief Target Stream Current Address Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_TS_CA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_TS_CA;
|
||||
|
||||
/** \brief Target Stream Frame Count Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_TS_FC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_TS_FC;
|
||||
|
||||
/** \brief Target Stream Start Address Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_TSSA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_TSSA;
|
||||
|
||||
/** \brief Target Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_HSSL_TSTAT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_HSSL_TSTAT;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Hssl_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L1
|
||||
* \{ */
|
||||
|
||||
/** \brief Access window */
|
||||
typedef volatile struct _Ifx_HSSL_AW
|
||||
{
|
||||
Ifx_HSSL_AW_AWSTART AWSTART; /**< \brief 0, Access Window Start Register */
|
||||
Ifx_HSSL_AW_AWEND AWEND; /**< \brief 4, Access Window End Register */
|
||||
} Ifx_HSSL_AW;
|
||||
|
||||
/** \brief Initiator */
|
||||
typedef volatile struct _Ifx_HSSL_I
|
||||
{
|
||||
Ifx_HSSL_I_IWD IWD; /**< \brief 0, Initiator Write Data Register */
|
||||
Ifx_HSSL_I_ICON ICON; /**< \brief 4, Initiator Control Data Register */
|
||||
Ifx_HSSL_I_IRWA IRWA; /**< \brief 8, Initiator Read Write Address Register */
|
||||
Ifx_HSSL_I_IRD IRD; /**< \brief C, Initiator Read Data Register */
|
||||
} Ifx_HSSL_I;
|
||||
|
||||
/** \brief Initiator stream */
|
||||
typedef volatile struct _Ifx_HSSL_IS
|
||||
{
|
||||
Ifx_HSSL_ISSA SA[2]; /**< \brief 0, Initiator Stream Start Address Register */
|
||||
Ifx_HSSL_IS_CA CA; /**< \brief 8, Initiator Stream Current Address Register */
|
||||
Ifx_HSSL_IS_FC FC; /**< \brief C, Initiator Stream Frame Count Register */
|
||||
} Ifx_HSSL_IS;
|
||||
|
||||
/** \brief target */
|
||||
typedef volatile struct _Ifx_HSSL_T
|
||||
{
|
||||
Ifx_HSSL_T_TCD TCD; /**< \brief 0, Target Current Data Register */
|
||||
Ifx_HSSL_T_TCA TCA; /**< \brief 4, Target Current Address Register */
|
||||
} Ifx_HSSL_T;
|
||||
|
||||
/** \brief Target stream */
|
||||
typedef volatile struct _Ifx_HSSL_TS
|
||||
{
|
||||
Ifx_HSSL_TSSA SA[2]; /**< \brief 0, Target Stream Start Address Register */
|
||||
Ifx_HSSL_TS_CA CA; /**< \brief 8, Target Stream Current Address Register */
|
||||
Ifx_HSSL_TS_FC FC; /**< \brief C, Target Stream Frame Count Register */
|
||||
} Ifx_HSSL_TS;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Hssl_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief HSSL object */
|
||||
typedef volatile struct _Ifx_HSSL
|
||||
{
|
||||
Ifx_HSSL_CLC CLC; /**< \brief 0, Clock Control Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_HSSL_ID ID; /**< \brief 8, Module Identification Register */
|
||||
Ifx_HSSL_CRC CRC; /**< \brief C, CRC Control Register */
|
||||
Ifx_HSSL_CFG CFG; /**< \brief 10, Configuration Register */
|
||||
Ifx_HSSL_QFLAGS QFLAGS; /**< \brief 14, Request Flags Register */
|
||||
Ifx_HSSL_MFLAGS MFLAGS; /**< \brief 18, Miscellaneous Flags Register */
|
||||
Ifx_HSSL_MFLAGSSET MFLAGSSET; /**< \brief 1C, Miscellaneous Flags Set Register */
|
||||
Ifx_HSSL_MFLAGSCL MFLAGSCL; /**< \brief 20, Miscellaneous Flags Clear Register */
|
||||
Ifx_HSSL_MFLAGSEN MFLAGSEN; /**< \brief 24, Flags Enable Register */
|
||||
Ifx_HSSL_SFSFLAGS SFSFLAGS; /**< \brief 28, Stream FIFOs Status Flags Register */
|
||||
unsigned char reserved_2C[4]; /**< \brief 2C, \internal Reserved */
|
||||
Ifx_HSSL_I I[4]; /**< \brief 30, Initiator */
|
||||
Ifx_HSSL_T T[4]; /**< \brief 70, target */
|
||||
Ifx_HSSL_TSTAT TSTAT; /**< \brief 90, Target Status Register */
|
||||
Ifx_HSSL_TIDADD TIDADD; /**< \brief 94, Target ID Address Register */
|
||||
unsigned char reserved_98[8]; /**< \brief 98, \internal Reserved */
|
||||
Ifx_HSSL_IS IS; /**< \brief A0, Initiator stream */
|
||||
Ifx_HSSL_TS TS; /**< \brief B0, Target stream */
|
||||
Ifx_HSSL_AW AW[4]; /**< \brief C0, Access window */
|
||||
Ifx_HSSL_AR AR; /**< \brief E0, Access Rules Register */
|
||||
unsigned char reserved_E4[4]; /**< \brief E4, \internal Reserved */
|
||||
Ifx_HSSL_OCS OCS; /**< \brief E8, OCDS Control and Status */
|
||||
Ifx_HSSL_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
|
||||
Ifx_HSSL_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
|
||||
Ifx_HSSL_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
|
||||
Ifx_HSSL_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
|
||||
Ifx_HSSL_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
|
||||
unsigned char reserved_100[768]; /**< \brief 100, \internal Reserved */
|
||||
} Ifx_HSSL;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXHSSL_REGDEF_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,156 +0,0 @@
|
||||
/**
|
||||
* \file IfxI2c_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_I2c_Cfg I2c address
|
||||
* \ingroup IfxLld_I2c
|
||||
*
|
||||
* \defgroup IfxLld_I2c_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_I2c_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_I2c_Cfg_I2c0 2-I2C0
|
||||
* \ingroup IfxLld_I2c_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXI2C_REG_H
|
||||
#define IFXI2C_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxI2c_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_I2c_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief I2C object */
|
||||
#define MODULE_I2C0 /*lint --e(923)*/ (*(Ifx_I2C*)0xF00C0000u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_I2c_Cfg_I2c0
|
||||
* \{ */
|
||||
|
||||
/** \brief 1000C, Access Enable Register 0 */
|
||||
#define I2C0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_I2C_ACCEN0*)0xF00D000Cu)
|
||||
|
||||
/** \brief 10010, Access Enable Register 1 */
|
||||
#define I2C0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_I2C_ACCEN1*)0xF00D0010u)
|
||||
|
||||
/** \brief 20, Address Configuration Register */
|
||||
#define I2C0_ADDRCFG /*lint --e(923)*/ (*(volatile Ifx_I2C_ADDRCFG*)0xF00C0020u)
|
||||
|
||||
/** \brief 24, Bus Status Register */
|
||||
#define I2C0_BUSSTAT /*lint --e(923)*/ (*(volatile Ifx_I2C_BUSSTAT*)0xF00C0024u)
|
||||
|
||||
/** \brief 10000, Clock Control Register */
|
||||
#define I2C0_CLC /*lint --e(923)*/ (*(volatile Ifx_I2C_CLC*)0xF00D0000u)
|
||||
|
||||
/** \brief 0, Clock Control 1 Register */
|
||||
#define I2C0_CLC1 /*lint --e(923)*/ (*(volatile Ifx_I2C_CLC1*)0xF00C0000u)
|
||||
|
||||
/** \brief 14, End Data Control Register */
|
||||
#define I2C0_ENDDCTRL /*lint --e(923)*/ (*(volatile Ifx_I2C_ENDDCTRL*)0xF00C0014u)
|
||||
|
||||
/** \brief 68, Error Interrupt Request Source Clear Register */
|
||||
#define I2C0_ERRIRQSC /*lint --e(923)*/ (*(volatile Ifx_I2C_ERRIRQSC*)0xF00C0068u)
|
||||
|
||||
/** \brief 60, Error Interrupt Request Source Mask Register */
|
||||
#define I2C0_ERRIRQSM /*lint --e(923)*/ (*(volatile Ifx_I2C_ERRIRQSM*)0xF00C0060u)
|
||||
|
||||
/** \brief 64, Error Interrupt Request Source Status Register */
|
||||
#define I2C0_ERRIRQSS /*lint --e(923)*/ (*(volatile Ifx_I2C_ERRIRQSS*)0xF00C0064u)
|
||||
|
||||
/** \brief 18, Fractional Divider Configuration Register */
|
||||
#define I2C0_FDIVCFG /*lint --e(923)*/ (*(volatile Ifx_I2C_FDIVCFG*)0xF00C0018u)
|
||||
|
||||
/** \brief 1C, Fractional Divider High-speed Mode Configuration Register */
|
||||
#define I2C0_FDIVHIGHCFG /*lint --e(923)*/ (*(volatile Ifx_I2C_FDIVHIGHCFG*)0xF00C001Cu)
|
||||
|
||||
/** \brief 38, Filled FIFO Stages Status Register */
|
||||
#define I2C0_FFSSTAT /*lint --e(923)*/ (*(volatile Ifx_I2C_FFSSTAT*)0xF00C0038u)
|
||||
|
||||
/** \brief 28, FIFO Configuration Register */
|
||||
#define I2C0_FIFOCFG /*lint --e(923)*/ (*(volatile Ifx_I2C_FIFOCFG*)0xF00C0028u)
|
||||
|
||||
/** \brief 10008, General Purpose Control Register */
|
||||
#define I2C0_GPCTL /*lint --e(923)*/ (*(volatile Ifx_I2C_GPCTL*)0xF00D0008u)
|
||||
|
||||
/** \brief 8C, Interrupt Clear Register */
|
||||
#define I2C0_ICR /*lint --e(923)*/ (*(volatile Ifx_I2C_ICR*)0xF00C008Cu)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define I2C0_ID /*lint --e(923)*/ (*(volatile Ifx_I2C_ID*)0xF00C0008u)
|
||||
|
||||
/** \brief 84, Interrupt Mask Control Register */
|
||||
#define I2C0_IMSC /*lint --e(923)*/ (*(volatile Ifx_I2C_IMSC*)0xF00C0084u)
|
||||
|
||||
/** \brief 90, Interrupt Set Register */
|
||||
#define I2C0_ISR /*lint --e(923)*/ (*(volatile Ifx_I2C_ISR*)0xF00C0090u)
|
||||
|
||||
/** \brief 10014, Kernel Reset Register 0 */
|
||||
#define I2C0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_I2C_KRST0*)0xF00D0014u)
|
||||
|
||||
/** \brief 10018, Kernel Reset Register 1 */
|
||||
#define I2C0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_I2C_KRST1*)0xF00D0018u)
|
||||
|
||||
/** \brief 1001C, Kernel Reset Status Clear Register */
|
||||
#define I2C0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_I2C_KRSTCLR*)0xF00D001Cu)
|
||||
|
||||
/** \brief 88, Masked Interrupt Status Register */
|
||||
#define I2C0_MIS /*lint --e(923)*/ (*(volatile Ifx_I2C_MIS*)0xF00C0088u)
|
||||
|
||||
/** \brief 10004, Module Identification Register */
|
||||
#define I2C0_MODID /*lint --e(923)*/ (*(volatile Ifx_I2C_MODID*)0xF00D0004u)
|
||||
|
||||
/** \brief 2C, Maximum Received Packet Size Control Register */
|
||||
#define I2C0_MRPSCTRL /*lint --e(923)*/ (*(volatile Ifx_I2C_MRPSCTRL*)0xF00C002Cu)
|
||||
|
||||
/** \brief 78, Protocol Interrupt Request Source Clear Register */
|
||||
#define I2C0_PIRQSC /*lint --e(923)*/ (*(volatile Ifx_I2C_PIRQSC*)0xF00C0078u)
|
||||
|
||||
/** \brief 70, Protocol Interrupt Request Source Mask Register */
|
||||
#define I2C0_PIRQSM /*lint --e(923)*/ (*(volatile Ifx_I2C_PIRQSM*)0xF00C0070u)
|
||||
|
||||
/** \brief 74, Protocol Interrupt Request Source Status Register */
|
||||
#define I2C0_PIRQSS /*lint --e(923)*/ (*(volatile Ifx_I2C_PIRQSS*)0xF00C0074u)
|
||||
|
||||
/** \brief 80, Raw Interrupt Status Register */
|
||||
#define I2C0_RIS /*lint --e(923)*/ (*(volatile Ifx_I2C_RIS*)0xF00C0080u)
|
||||
|
||||
/** \brief 30, Received Packet Size Status Register */
|
||||
#define I2C0_RPSSTAT /*lint --e(923)*/ (*(volatile Ifx_I2C_RPSSTAT*)0xF00C0030u)
|
||||
|
||||
/** \brief 10, RUN Control Register */
|
||||
#define I2C0_RUNCTRL /*lint --e(923)*/ (*(volatile Ifx_I2C_RUNCTRL*)0xF00C0010u)
|
||||
|
||||
/** \brief C000, Reception Data Register */
|
||||
#define I2C0_RXD /*lint --e(923)*/ (*(volatile Ifx_I2C_RXD*)0xF00CC000u)
|
||||
|
||||
/** \brief 40, Timing Configuration Register */
|
||||
#define I2C0_TIMCFG /*lint --e(923)*/ (*(volatile Ifx_I2C_TIMCFG*)0xF00C0040u)
|
||||
|
||||
/** \brief 34, Transmit Packet Size Control Register */
|
||||
#define I2C0_TPSCTRL /*lint --e(923)*/ (*(volatile Ifx_I2C_TPSCTRL*)0xF00C0034u)
|
||||
|
||||
/** \brief 8000, Transmission Data Register */
|
||||
#define I2C0_TXD /*lint --e(923)*/ (*(volatile Ifx_I2C_TXD*)0xF00C8000u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXI2C_REG_H */
|
||||
@@ -1,753 +0,0 @@
|
||||
/**
|
||||
* \file IfxI2c_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_I2c I2c
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_I2c_Bitfields Bitfields
|
||||
* \ingroup IfxLld_I2c
|
||||
*
|
||||
* \defgroup IfxLld_I2c_union Union
|
||||
* \ingroup IfxLld_I2c
|
||||
*
|
||||
* \defgroup IfxLld_I2c_struct Struct
|
||||
* \ingroup IfxLld_I2c
|
||||
*
|
||||
*/
|
||||
#ifndef IFXI2C_REGDEF_H
|
||||
#define IFXI2C_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_I2c_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_I2C_ACCEN0_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_I2C_ACCEN0_Bits;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef struct _Ifx_I2C_ACCEN1_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_ACCEN1_Bits;
|
||||
|
||||
/** \brief Address Configuration Register */
|
||||
typedef struct _Ifx_I2C_ADDRCFG_Bits
|
||||
{
|
||||
unsigned int ADR:10; /**< \brief [9:0] I2C-bus Device Address (rw) */
|
||||
unsigned int reserved_10:6; /**< \brief \internal Reserved */
|
||||
unsigned int TBAM:1; /**< \brief [16:16] Ten Bit Address Mode (rw) */
|
||||
unsigned int GCE:1; /**< \brief [17:17] General Call Enable (rw) */
|
||||
unsigned int MCE:1; /**< \brief [18:18] Master Code Enable (rw) */
|
||||
unsigned int MnS:1; /**< \brief [19:19] Master / not Slave (rw) */
|
||||
unsigned int SONA:1; /**< \brief [20:20] Stop on Not-acknowledge (rw) */
|
||||
unsigned int SOPE:1; /**< \brief [21:21] Stop on Packet End (rw) */
|
||||
unsigned int reserved_22:10; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_ADDRCFG_Bits;
|
||||
|
||||
/** \brief Bus Status Register */
|
||||
typedef struct _Ifx_I2C_BUSSTAT_Bits
|
||||
{
|
||||
unsigned int BS:2; /**< \brief [1:0] Bus Status (rh) */
|
||||
unsigned int RnW:1; /**< \brief [2:2] Read/not Write (rh) */
|
||||
unsigned int reserved_3:29; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_BUSSTAT_Bits;
|
||||
|
||||
/** \brief Clock Control 1 Register */
|
||||
typedef struct _Ifx_I2C_CLC1_Bits
|
||||
{
|
||||
unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
|
||||
unsigned int SPEN:1; /**< \brief [2:2] Module Suspend Enable Bit for OCDS (rw) */
|
||||
unsigned int EDIS:1; /**< \brief [3:3] External Request Disable (rw) */
|
||||
unsigned int SBWE:1; /**< \brief [4:4] Module Suspend Bit Write Enable for OCDS (w) */
|
||||
unsigned int FSOE:1; /**< \brief [5:5] Fast Switch Off Enable (rw) */
|
||||
unsigned int reserved_6:2; /**< \brief \internal Reserved */
|
||||
unsigned int RMC:8; /**< \brief [15:8] Clock Divider for Standard Run Mode (rwh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_CLC1_Bits;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef struct _Ifx_I2C_CLC_Bits
|
||||
{
|
||||
unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_CLC_Bits;
|
||||
|
||||
/** \brief End Data Control Register */
|
||||
typedef struct _Ifx_I2C_ENDDCTRL_Bits
|
||||
{
|
||||
unsigned int SETRSC:1; /**< \brief [0:0] Set Restart Condition (w) */
|
||||
unsigned int SETEND:1; /**< \brief [1:1] Set End of Transmission (w) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_ENDDCTRL_Bits;
|
||||
|
||||
/** \brief Error Interrupt Request Source Clear Register */
|
||||
typedef struct _Ifx_I2C_ERRIRQSC_Bits
|
||||
{
|
||||
unsigned int RXF_UFL:1; /**< \brief [0:0] RX FIFO Underflow (w) */
|
||||
unsigned int RXF_OFL:1; /**< \brief [1:1] RX FIFO Overflow (w) */
|
||||
unsigned int TXF_UFL:1; /**< \brief [2:2] TX FIFO Underflow (w) */
|
||||
unsigned int TXF_OFL:1; /**< \brief [3:3] TX FIFO Overflow (w) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_ERRIRQSC_Bits;
|
||||
|
||||
/** \brief Error Interrupt Request Source Mask Register */
|
||||
typedef struct _Ifx_I2C_ERRIRQSM_Bits
|
||||
{
|
||||
unsigned int RXF_UFL:1; /**< \brief [0:0] RX FIFO Underflow (rw) */
|
||||
unsigned int RXF_OFL:1; /**< \brief [1:1] RX FIFO Overflow (rw) */
|
||||
unsigned int TXF_UFL:1; /**< \brief [2:2] TX FIFO Underflow (rw) */
|
||||
unsigned int TXF_OFL:1; /**< \brief [3:3] TX FIFO Overflow (rw) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_ERRIRQSM_Bits;
|
||||
|
||||
/** \brief Error Interrupt Request Source Status Register */
|
||||
typedef struct _Ifx_I2C_ERRIRQSS_Bits
|
||||
{
|
||||
unsigned int RXF_UFL:1; /**< \brief [0:0] RX FIFO Underflow (rh) */
|
||||
unsigned int RXF_OFL:1; /**< \brief [1:1] RX FIFO Overflow (rh) */
|
||||
unsigned int TXF_UFL:1; /**< \brief [2:2] TX FIFO Underflow (rh) */
|
||||
unsigned int TXF_OFL:1; /**< \brief [3:3] TX FIFO Overflow (rh) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_ERRIRQSS_Bits;
|
||||
|
||||
/** \brief Fractional Divider Configuration Register */
|
||||
typedef struct _Ifx_I2C_FDIVCFG_Bits
|
||||
{
|
||||
unsigned int DEC:11; /**< \brief [10:0] Decrement Value of Fractional Divider (rw) */
|
||||
unsigned int reserved_11:5; /**< \brief \internal Reserved */
|
||||
unsigned int INC:8; /**< \brief [23:16] Increment Value of Fractional Divider (rw) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_FDIVCFG_Bits;
|
||||
|
||||
/** \brief Fractional Divider High-speed Mode Configuration Register */
|
||||
typedef struct _Ifx_I2C_FDIVHIGHCFG_Bits
|
||||
{
|
||||
unsigned int DEC:11; /**< \brief [10:0] Decrement Value of Fractional Divider (rw) */
|
||||
unsigned int reserved_11:5; /**< \brief \internal Reserved */
|
||||
unsigned int INC:8; /**< \brief [23:16] Increment Value of Fractional Divider (rw) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_FDIVHIGHCFG_Bits;
|
||||
|
||||
/** \brief Filled FIFO Stages Status Register */
|
||||
typedef struct _Ifx_I2C_FFSSTAT_Bits
|
||||
{
|
||||
unsigned int FFS:6; /**< \brief [5:0] Filled FIFO Stages (rh) */
|
||||
unsigned int reserved_6:26; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_FFSSTAT_Bits;
|
||||
|
||||
/** \brief FIFO Configuration Register */
|
||||
typedef struct _Ifx_I2C_FIFOCFG_Bits
|
||||
{
|
||||
unsigned int RXBS:2; /**< \brief [1:0] RX Burst Size (rw) */
|
||||
unsigned int reserved_2:2; /**< \brief \internal Reserved */
|
||||
unsigned int TXBS:2; /**< \brief [5:4] TX Burst Size (rw) */
|
||||
unsigned int reserved_6:2; /**< \brief \internal Reserved */
|
||||
unsigned int RXFA:2; /**< \brief [9:8] RX FIFO Alignment (rw) */
|
||||
unsigned int reserved_10:2; /**< \brief \internal Reserved */
|
||||
unsigned int TXFA:2; /**< \brief [13:12] TX FIFO Alignment (rw) */
|
||||
unsigned int reserved_14:2; /**< \brief \internal Reserved */
|
||||
unsigned int RXFC:1; /**< \brief [16:16] RX FIFO Flow Control (rw) */
|
||||
unsigned int TXFC:1; /**< \brief [17:17] TX FIFO Flow Control (rw) */
|
||||
unsigned int reserved_18:14; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_FIFOCFG_Bits;
|
||||
|
||||
/** \brief General Purpose Control Register */
|
||||
typedef struct _Ifx_I2C_GPCTL_Bits
|
||||
{
|
||||
unsigned int PISEL:3; /**< \brief [2:0] Port Input Select (rw) */
|
||||
unsigned int reserved_3:29; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_GPCTL_Bits;
|
||||
|
||||
/** \brief Interrupt Clear Register */
|
||||
typedef struct _Ifx_I2C_ICR_Bits
|
||||
{
|
||||
unsigned int LSREQ_INT:1; /**< \brief [0:0] Last Single Request Interrupt (w) */
|
||||
unsigned int SREQ_INT:1; /**< \brief [1:1] Single Request Interrupt (w) */
|
||||
unsigned int LBREQ_INT:1; /**< \brief [2:2] Last Burst Request Interrupt (w) */
|
||||
unsigned int BREQ_INT:1; /**< \brief [3:3] Burst Request Interrupt (w) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_ICR_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_I2C_ID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODNUMBER:8; /**< \brief [15:8] Module Number Value (r) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_ID_Bits;
|
||||
|
||||
/** \brief Interrupt Mask Control Register */
|
||||
typedef struct _Ifx_I2C_IMSC_Bits
|
||||
{
|
||||
unsigned int LSREQ_INT:1; /**< \brief [0:0] Last Single Request Interrupt (rw) */
|
||||
unsigned int SREQ_INT:1; /**< \brief [1:1] Single Request Interrupt (rw) */
|
||||
unsigned int LBREQ_INT:1; /**< \brief [2:2] Last Burst Request Interrupt (rw) */
|
||||
unsigned int BREQ_INT:1; /**< \brief [3:3] Burst Request Interrupt (rw) */
|
||||
unsigned int I2C_ERR_INT:1; /**< \brief [4:4] I2C Error Interrupt (rw) */
|
||||
unsigned int I2C_P_INT:1; /**< \brief [5:5] I2C Protocol Interrupt (rw) */
|
||||
unsigned int reserved_6:26; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_IMSC_Bits;
|
||||
|
||||
/** \brief Interrupt Set Register */
|
||||
typedef struct _Ifx_I2C_ISR_Bits
|
||||
{
|
||||
unsigned int LSREQ_INT:1; /**< \brief [0:0] Last Single Request Interrupt (w) */
|
||||
unsigned int SREQ_INT:1; /**< \brief [1:1] Single Request Interrupt (w) */
|
||||
unsigned int LBREQ_INT:1; /**< \brief [2:2] Last Burst Request Interrupt (w) */
|
||||
unsigned int BREQ_INT:1; /**< \brief [3:3] Burst Request Interrupt (w) */
|
||||
unsigned int I2C_ERR_INT:1; /**< \brief [4:4] I2C Error Interrupt (w) */
|
||||
unsigned int I2C_P_INT:1; /**< \brief [5:5] I2C Protocol Interrupt (w) */
|
||||
unsigned int reserved_6:26; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_ISR_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef struct _Ifx_I2C_KRST0_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_KRST0_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef struct _Ifx_I2C_KRST1_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_KRST1_Bits;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef struct _Ifx_I2C_KRSTCLR_Bits
|
||||
{
|
||||
unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_KRSTCLR_Bits;
|
||||
|
||||
/** \brief Masked Interrupt Status Register */
|
||||
typedef struct _Ifx_I2C_MIS_Bits
|
||||
{
|
||||
unsigned int LSREQ_INT:1; /**< \brief [0:0] Last Single Request Interrupt (rh) */
|
||||
unsigned int SREQ_INT:1; /**< \brief [1:1] Single Request Interrupt (rh) */
|
||||
unsigned int LBREQ_INT:1; /**< \brief [2:2] Last Burst Request Interrupt (rh) */
|
||||
unsigned int BREQ_INT:1; /**< \brief [3:3] Burst Request Interrupt (rh) */
|
||||
unsigned int I2C_ERR_INT:1; /**< \brief [4:4] I2C Error Interrupt (rh) */
|
||||
unsigned int I2C_P_INT:1; /**< \brief [5:5] I2C Protocol Interrupt (rh) */
|
||||
unsigned int reserved_6:26; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_MIS_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_I2C_MODID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_I2C_MODID_Bits;
|
||||
|
||||
/** \brief Maximum Received Packet Size Control Register */
|
||||
typedef struct _Ifx_I2C_MRPSCTRL_Bits
|
||||
{
|
||||
unsigned int MRPS:14; /**< \brief [13:0] Maximum Received Packet Size (rwh) */
|
||||
unsigned int reserved_14:18; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_MRPSCTRL_Bits;
|
||||
|
||||
/** \brief Protocol Interrupt Request Source Clear Register */
|
||||
typedef struct _Ifx_I2C_PIRQSC_Bits
|
||||
{
|
||||
unsigned int AM:1; /**< \brief [0:0] Address Match (w) */
|
||||
unsigned int GC:1; /**< \brief [1:1] General Call (w) */
|
||||
unsigned int MC:1; /**< \brief [2:2] Master Code (w) */
|
||||
unsigned int AL:1; /**< \brief [3:3] Arbitration Lost (w) */
|
||||
unsigned int NACK:1; /**< \brief [4:4] Not-acknowledge Received (w) */
|
||||
unsigned int TX_END:1; /**< \brief [5:5] Transmission End (w) */
|
||||
unsigned int RX:1; /**< \brief [6:6] Receive Mode (w) */
|
||||
unsigned int reserved_7:25; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_PIRQSC_Bits;
|
||||
|
||||
/** \brief Protocol Interrupt Request Source Mask Register */
|
||||
typedef struct _Ifx_I2C_PIRQSM_Bits
|
||||
{
|
||||
unsigned int AM:1; /**< \brief [0:0] Address Match (rw) */
|
||||
unsigned int GC:1; /**< \brief [1:1] General Call (rw) */
|
||||
unsigned int MC:1; /**< \brief [2:2] Master Code (rw) */
|
||||
unsigned int AL:1; /**< \brief [3:3] Arbitration Lost (rw) */
|
||||
unsigned int NACK:1; /**< \brief [4:4] Not-acknowledge Received (rw) */
|
||||
unsigned int TX_END:1; /**< \brief [5:5] Transmission End (rw) */
|
||||
unsigned int RX:1; /**< \brief [6:6] Receive Mode (rw) */
|
||||
unsigned int reserved_7:25; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_PIRQSM_Bits;
|
||||
|
||||
/** \brief Protocol Interrupt Request Source Status Register */
|
||||
typedef struct _Ifx_I2C_PIRQSS_Bits
|
||||
{
|
||||
unsigned int AM:1; /**< \brief [0:0] Address Match (rh) */
|
||||
unsigned int GC:1; /**< \brief [1:1] General Call (rh) */
|
||||
unsigned int MC:1; /**< \brief [2:2] Master Code (rh) */
|
||||
unsigned int AL:1; /**< \brief [3:3] Arbitration Lost (rh) */
|
||||
unsigned int NACK:1; /**< \brief [4:4] Not-acknowledge Received (rh) */
|
||||
unsigned int TX_END:1; /**< \brief [5:5] Transmission End (rh) */
|
||||
unsigned int RX:1; /**< \brief [6:6] Receive Mode (rh) */
|
||||
unsigned int reserved_7:25; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_PIRQSS_Bits;
|
||||
|
||||
/** \brief Raw Interrupt Status Register */
|
||||
typedef struct _Ifx_I2C_RIS_Bits
|
||||
{
|
||||
unsigned int LSREQ_INT:1; /**< \brief [0:0] Last Single Request Interrupt (rh) */
|
||||
unsigned int SREQ_INT:1; /**< \brief [1:1] Single Request Interrupt (rh) */
|
||||
unsigned int LBREQ_INT:1; /**< \brief [2:2] Last Burst Request Interrupt (rh) */
|
||||
unsigned int BREQ_INT:1; /**< \brief [3:3] Burst Request Interrupt (rh) */
|
||||
unsigned int I2C_ERR_INT:1; /**< \brief [4:4] I2C Error Interrupt (rh) */
|
||||
unsigned int I2C_P_INT:1; /**< \brief [5:5] I2C Protocol Interrupt (rh) */
|
||||
unsigned int reserved_6:26; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_RIS_Bits;
|
||||
|
||||
/** \brief Received Packet Size Status Register */
|
||||
typedef struct _Ifx_I2C_RPSSTAT_Bits
|
||||
{
|
||||
unsigned int RPS:14; /**< \brief [13:0] Received Packet Size (rh) */
|
||||
unsigned int reserved_14:18; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_RPSSTAT_Bits;
|
||||
|
||||
/** \brief RUN Control Register */
|
||||
typedef struct _Ifx_I2C_RUNCTRL_Bits
|
||||
{
|
||||
unsigned int RUN:1; /**< \brief [0:0] Enable I2C-bus Interface (rw) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_RUNCTRL_Bits;
|
||||
|
||||
/** \brief Reception Data Register */
|
||||
typedef struct _Ifx_I2C_RXD_Bits
|
||||
{
|
||||
unsigned int RXD:32; /**< \brief [31:0] Reception Data (rh) */
|
||||
} Ifx_I2C_RXD_Bits;
|
||||
|
||||
/** \brief Timing Configuration Register */
|
||||
typedef struct _Ifx_I2C_TIMCFG_Bits
|
||||
{
|
||||
unsigned int SDA_DEL_HD_DAT:6; /**< \brief [5:0] SDA Delay Stages for Data Hold Time (rw) */
|
||||
unsigned int HS_SDA_DEL_HD_DAT:3; /**< \brief [8:6] SDA Delay Stages for Data Hold Time in High-speed Mode (rw) */
|
||||
unsigned int SCL_DEL_HD_STA:3; /**< \brief [11:9] SCL Delay Stages for Hold Time Start (Restart) Bit (rw) */
|
||||
unsigned int reserved_12:2; /**< \brief \internal Reserved */
|
||||
unsigned int EN_SCL_LOW_LEN:1; /**< \brief [14:14] Enable Direct Configuration of SCL Low Period Length in Fast Mode (rw) */
|
||||
unsigned int FS_SCL_LOW:1; /**< \brief [15:15] Set Fast Mode SCL Low Period Timing (rw) */
|
||||
unsigned int HS_SDA_DEL:3; /**< \brief [18:16] SDA Delay Stages for Start/Stop bit in High-speed Mode (rw) */
|
||||
unsigned int reserved_19:5; /**< \brief \internal Reserved */
|
||||
unsigned int SCL_LOW_LEN:8; /**< \brief [31:24] SCL Low Length in Fast Mode (rw) */
|
||||
} Ifx_I2C_TIMCFG_Bits;
|
||||
|
||||
/** \brief Transmit Packet Size Control Register */
|
||||
typedef struct _Ifx_I2C_TPSCTRL_Bits
|
||||
{
|
||||
unsigned int TPS:14; /**< \brief [13:0] Transmit Packet Size (rwh) */
|
||||
unsigned int reserved_14:18; /**< \brief \internal Reserved */
|
||||
} Ifx_I2C_TPSCTRL_Bits;
|
||||
|
||||
/** \brief Transmission Data Register */
|
||||
typedef struct _Ifx_I2C_TXD_Bits
|
||||
{
|
||||
unsigned int TXD:32; /**< \brief [31:0] Transmission Data (rw) */
|
||||
} Ifx_I2C_TXD_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_I2c_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_ACCEN0;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_ACCEN1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_ACCEN1;
|
||||
|
||||
/** \brief Address Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_ADDRCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_ADDRCFG;
|
||||
|
||||
/** \brief Bus Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_BUSSTAT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_BUSSTAT;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_CLC;
|
||||
|
||||
/** \brief Clock Control 1 Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_CLC1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_CLC1;
|
||||
|
||||
/** \brief End Data Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_ENDDCTRL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_ENDDCTRL;
|
||||
|
||||
/** \brief Error Interrupt Request Source Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_ERRIRQSC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_ERRIRQSC;
|
||||
|
||||
/** \brief Error Interrupt Request Source Mask Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_ERRIRQSM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_ERRIRQSM;
|
||||
|
||||
/** \brief Error Interrupt Request Source Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_ERRIRQSS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_ERRIRQSS;
|
||||
|
||||
/** \brief Fractional Divider Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_FDIVCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_FDIVCFG;
|
||||
|
||||
/** \brief Fractional Divider High-speed Mode Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_FDIVHIGHCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_FDIVHIGHCFG;
|
||||
|
||||
/** \brief Filled FIFO Stages Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_FFSSTAT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_FFSSTAT;
|
||||
|
||||
/** \brief FIFO Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_FIFOCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_FIFOCFG;
|
||||
|
||||
/** \brief General Purpose Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_GPCTL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_GPCTL;
|
||||
|
||||
/** \brief Interrupt Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_ICR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_ICR;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_ID;
|
||||
|
||||
/** \brief Interrupt Mask Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_IMSC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_IMSC;
|
||||
|
||||
/** \brief Interrupt Set Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_ISR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_ISR;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_KRST0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_KRST0;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_KRST1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_KRST1;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_KRSTCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_KRSTCLR;
|
||||
|
||||
/** \brief Masked Interrupt Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_MIS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_MIS;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_MODID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_MODID;
|
||||
|
||||
/** \brief Maximum Received Packet Size Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_MRPSCTRL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_MRPSCTRL;
|
||||
|
||||
/** \brief Protocol Interrupt Request Source Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_PIRQSC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_PIRQSC;
|
||||
|
||||
/** \brief Protocol Interrupt Request Source Mask Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_PIRQSM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_PIRQSM;
|
||||
|
||||
/** \brief Protocol Interrupt Request Source Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_PIRQSS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_PIRQSS;
|
||||
|
||||
/** \brief Raw Interrupt Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_RIS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_RIS;
|
||||
|
||||
/** \brief Received Packet Size Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_RPSSTAT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_RPSSTAT;
|
||||
|
||||
/** \brief RUN Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_RUNCTRL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_RUNCTRL;
|
||||
|
||||
/** \brief Reception Data Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_RXD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_RXD;
|
||||
|
||||
/** \brief Timing Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_TIMCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_TIMCFG;
|
||||
|
||||
/** \brief Transmit Packet Size Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_TPSCTRL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_TPSCTRL;
|
||||
|
||||
/** \brief Transmission Data Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_I2C_TXD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_I2C_TXD;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_I2c_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief I2C object */
|
||||
typedef volatile struct _Ifx_I2C
|
||||
{
|
||||
Ifx_I2C_CLC1 CLC1; /**< \brief 0, Clock Control 1 Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_I2C_ID ID; /**< \brief 8, Module Identification Register */
|
||||
unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
|
||||
Ifx_I2C_RUNCTRL RUNCTRL; /**< \brief 10, RUN Control Register */
|
||||
Ifx_I2C_ENDDCTRL ENDDCTRL; /**< \brief 14, End Data Control Register */
|
||||
Ifx_I2C_FDIVCFG FDIVCFG; /**< \brief 18, Fractional Divider Configuration Register */
|
||||
Ifx_I2C_FDIVHIGHCFG FDIVHIGHCFG; /**< \brief 1C, Fractional Divider High-speed Mode Configuration Register */
|
||||
Ifx_I2C_ADDRCFG ADDRCFG; /**< \brief 20, Address Configuration Register */
|
||||
Ifx_I2C_BUSSTAT BUSSTAT; /**< \brief 24, Bus Status Register */
|
||||
Ifx_I2C_FIFOCFG FIFOCFG; /**< \brief 28, FIFO Configuration Register */
|
||||
Ifx_I2C_MRPSCTRL MRPSCTRL; /**< \brief 2C, Maximum Received Packet Size Control Register */
|
||||
Ifx_I2C_RPSSTAT RPSSTAT; /**< \brief 30, Received Packet Size Status Register */
|
||||
Ifx_I2C_TPSCTRL TPSCTRL; /**< \brief 34, Transmit Packet Size Control Register */
|
||||
Ifx_I2C_FFSSTAT FFSSTAT; /**< \brief 38, Filled FIFO Stages Status Register */
|
||||
unsigned char reserved_3C[4]; /**< \brief 3C, \internal Reserved */
|
||||
Ifx_I2C_TIMCFG TIMCFG; /**< \brief 40, Timing Configuration Register */
|
||||
unsigned char reserved_44[28]; /**< \brief 44, \internal Reserved */
|
||||
Ifx_I2C_ERRIRQSM ERRIRQSM; /**< \brief 60, Error Interrupt Request Source Mask Register */
|
||||
Ifx_I2C_ERRIRQSS ERRIRQSS; /**< \brief 64, Error Interrupt Request Source Status Register */
|
||||
Ifx_I2C_ERRIRQSC ERRIRQSC; /**< \brief 68, Error Interrupt Request Source Clear Register */
|
||||
unsigned char reserved_6C[4]; /**< \brief 6C, \internal Reserved */
|
||||
Ifx_I2C_PIRQSM PIRQSM; /**< \brief 70, Protocol Interrupt Request Source Mask Register */
|
||||
Ifx_I2C_PIRQSS PIRQSS; /**< \brief 74, Protocol Interrupt Request Source Status Register */
|
||||
Ifx_I2C_PIRQSC PIRQSC; /**< \brief 78, Protocol Interrupt Request Source Clear Register */
|
||||
unsigned char reserved_7C[4]; /**< \brief 7C, \internal Reserved */
|
||||
Ifx_I2C_RIS RIS; /**< \brief 80, Raw Interrupt Status Register */
|
||||
Ifx_I2C_IMSC IMSC; /**< \brief 84, Interrupt Mask Control Register */
|
||||
Ifx_I2C_MIS MIS; /**< \brief 88, Masked Interrupt Status Register */
|
||||
Ifx_I2C_ICR ICR; /**< \brief 8C, Interrupt Clear Register */
|
||||
Ifx_I2C_ISR ISR; /**< \brief 90, Interrupt Set Register */
|
||||
unsigned char reserved_94[32620]; /**< \brief 94, \internal Reserved */
|
||||
Ifx_I2C_TXD TXD; /**< \brief 8000, Transmission Data Register */
|
||||
unsigned char reserved_8004[16380]; /**< \brief 8004, \internal Reserved */
|
||||
Ifx_I2C_RXD RXD; /**< \brief C000, Reception Data Register */
|
||||
unsigned char reserved_C004[16380]; /**< \brief C004, \internal Reserved */
|
||||
Ifx_I2C_CLC CLC; /**< \brief 10000, Clock Control Register */
|
||||
Ifx_I2C_MODID MODID; /**< \brief 10004, Module Identification Register */
|
||||
Ifx_I2C_GPCTL GPCTL; /**< \brief 10008, General Purpose Control Register */
|
||||
Ifx_I2C_ACCEN0 ACCEN0; /**< \brief 1000C, Access Enable Register 0 */
|
||||
Ifx_I2C_ACCEN1 ACCEN1; /**< \brief 10010, Access Enable Register 1 */
|
||||
Ifx_I2C_KRST0 KRST0; /**< \brief 10014, Kernel Reset Register 0 */
|
||||
Ifx_I2C_KRST1 KRST1; /**< \brief 10018, Kernel Reset Register 1 */
|
||||
Ifx_I2C_KRSTCLR KRSTCLR; /**< \brief 1001C, Kernel Reset Status Clear Register */
|
||||
unsigned char reserved_10020[224]; /**< \brief 10020, \internal Reserved */
|
||||
} Ifx_I2C;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXI2C_REGDEF_H */
|
||||
@@ -1,990 +0,0 @@
|
||||
/**
|
||||
* \file IfxInt_bf.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Int_BitfieldsMask Bitfields mask and offset
|
||||
* \ingroup IfxLld_Int
|
||||
*
|
||||
*/
|
||||
#ifndef IFXINT_BF_H
|
||||
#define IFXINT_BF_H 1
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Int_BitfieldsMask
|
||||
* \{ */
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN0 */
|
||||
#define IFX_INT_ACCEN00_EN0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN0 */
|
||||
#define IFX_INT_ACCEN00_EN0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN0 */
|
||||
#define IFX_INT_ACCEN00_EN0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN10 */
|
||||
#define IFX_INT_ACCEN00_EN10_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN10 */
|
||||
#define IFX_INT_ACCEN00_EN10_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN10 */
|
||||
#define IFX_INT_ACCEN00_EN10_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN11 */
|
||||
#define IFX_INT_ACCEN00_EN11_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN11 */
|
||||
#define IFX_INT_ACCEN00_EN11_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN11 */
|
||||
#define IFX_INT_ACCEN00_EN11_OFF (11u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN12 */
|
||||
#define IFX_INT_ACCEN00_EN12_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN12 */
|
||||
#define IFX_INT_ACCEN00_EN12_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN12 */
|
||||
#define IFX_INT_ACCEN00_EN12_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN13 */
|
||||
#define IFX_INT_ACCEN00_EN13_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN13 */
|
||||
#define IFX_INT_ACCEN00_EN13_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN13 */
|
||||
#define IFX_INT_ACCEN00_EN13_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN14 */
|
||||
#define IFX_INT_ACCEN00_EN14_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN14 */
|
||||
#define IFX_INT_ACCEN00_EN14_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN14 */
|
||||
#define IFX_INT_ACCEN00_EN14_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN15 */
|
||||
#define IFX_INT_ACCEN00_EN15_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN15 */
|
||||
#define IFX_INT_ACCEN00_EN15_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN15 */
|
||||
#define IFX_INT_ACCEN00_EN15_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN16 */
|
||||
#define IFX_INT_ACCEN00_EN16_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN16 */
|
||||
#define IFX_INT_ACCEN00_EN16_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN16 */
|
||||
#define IFX_INT_ACCEN00_EN16_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN17 */
|
||||
#define IFX_INT_ACCEN00_EN17_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN17 */
|
||||
#define IFX_INT_ACCEN00_EN17_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN17 */
|
||||
#define IFX_INT_ACCEN00_EN17_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN18 */
|
||||
#define IFX_INT_ACCEN00_EN18_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN18 */
|
||||
#define IFX_INT_ACCEN00_EN18_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN18 */
|
||||
#define IFX_INT_ACCEN00_EN18_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN19 */
|
||||
#define IFX_INT_ACCEN00_EN19_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN19 */
|
||||
#define IFX_INT_ACCEN00_EN19_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN19 */
|
||||
#define IFX_INT_ACCEN00_EN19_OFF (19u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN1 */
|
||||
#define IFX_INT_ACCEN00_EN1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN1 */
|
||||
#define IFX_INT_ACCEN00_EN1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN1 */
|
||||
#define IFX_INT_ACCEN00_EN1_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN20 */
|
||||
#define IFX_INT_ACCEN00_EN20_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN20 */
|
||||
#define IFX_INT_ACCEN00_EN20_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN20 */
|
||||
#define IFX_INT_ACCEN00_EN20_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN21 */
|
||||
#define IFX_INT_ACCEN00_EN21_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN21 */
|
||||
#define IFX_INT_ACCEN00_EN21_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN21 */
|
||||
#define IFX_INT_ACCEN00_EN21_OFF (21u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN22 */
|
||||
#define IFX_INT_ACCEN00_EN22_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN22 */
|
||||
#define IFX_INT_ACCEN00_EN22_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN22 */
|
||||
#define IFX_INT_ACCEN00_EN22_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN23 */
|
||||
#define IFX_INT_ACCEN00_EN23_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN23 */
|
||||
#define IFX_INT_ACCEN00_EN23_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN23 */
|
||||
#define IFX_INT_ACCEN00_EN23_OFF (23u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN24 */
|
||||
#define IFX_INT_ACCEN00_EN24_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN24 */
|
||||
#define IFX_INT_ACCEN00_EN24_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN24 */
|
||||
#define IFX_INT_ACCEN00_EN24_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN25 */
|
||||
#define IFX_INT_ACCEN00_EN25_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN25 */
|
||||
#define IFX_INT_ACCEN00_EN25_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN25 */
|
||||
#define IFX_INT_ACCEN00_EN25_OFF (25u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN26 */
|
||||
#define IFX_INT_ACCEN00_EN26_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN26 */
|
||||
#define IFX_INT_ACCEN00_EN26_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN26 */
|
||||
#define IFX_INT_ACCEN00_EN26_OFF (26u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN27 */
|
||||
#define IFX_INT_ACCEN00_EN27_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN27 */
|
||||
#define IFX_INT_ACCEN00_EN27_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN27 */
|
||||
#define IFX_INT_ACCEN00_EN27_OFF (27u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN28 */
|
||||
#define IFX_INT_ACCEN00_EN28_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN28 */
|
||||
#define IFX_INT_ACCEN00_EN28_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN28 */
|
||||
#define IFX_INT_ACCEN00_EN28_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN29 */
|
||||
#define IFX_INT_ACCEN00_EN29_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN29 */
|
||||
#define IFX_INT_ACCEN00_EN29_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN29 */
|
||||
#define IFX_INT_ACCEN00_EN29_OFF (29u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN2 */
|
||||
#define IFX_INT_ACCEN00_EN2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN2 */
|
||||
#define IFX_INT_ACCEN00_EN2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN2 */
|
||||
#define IFX_INT_ACCEN00_EN2_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN30 */
|
||||
#define IFX_INT_ACCEN00_EN30_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN30 */
|
||||
#define IFX_INT_ACCEN00_EN30_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN30 */
|
||||
#define IFX_INT_ACCEN00_EN30_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN31 */
|
||||
#define IFX_INT_ACCEN00_EN31_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN31 */
|
||||
#define IFX_INT_ACCEN00_EN31_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN31 */
|
||||
#define IFX_INT_ACCEN00_EN31_OFF (31u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN3 */
|
||||
#define IFX_INT_ACCEN00_EN3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN3 */
|
||||
#define IFX_INT_ACCEN00_EN3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN3 */
|
||||
#define IFX_INT_ACCEN00_EN3_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN4 */
|
||||
#define IFX_INT_ACCEN00_EN4_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN4 */
|
||||
#define IFX_INT_ACCEN00_EN4_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN4 */
|
||||
#define IFX_INT_ACCEN00_EN4_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN5 */
|
||||
#define IFX_INT_ACCEN00_EN5_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN5 */
|
||||
#define IFX_INT_ACCEN00_EN5_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN5 */
|
||||
#define IFX_INT_ACCEN00_EN5_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN6 */
|
||||
#define IFX_INT_ACCEN00_EN6_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN6 */
|
||||
#define IFX_INT_ACCEN00_EN6_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN6 */
|
||||
#define IFX_INT_ACCEN00_EN6_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN7 */
|
||||
#define IFX_INT_ACCEN00_EN7_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN7 */
|
||||
#define IFX_INT_ACCEN00_EN7_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN7 */
|
||||
#define IFX_INT_ACCEN00_EN7_OFF (7u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN8 */
|
||||
#define IFX_INT_ACCEN00_EN8_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN8 */
|
||||
#define IFX_INT_ACCEN00_EN8_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN8 */
|
||||
#define IFX_INT_ACCEN00_EN8_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN00_Bits.EN9 */
|
||||
#define IFX_INT_ACCEN00_EN9_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN00_Bits.EN9 */
|
||||
#define IFX_INT_ACCEN00_EN9_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN00_Bits.EN9 */
|
||||
#define IFX_INT_ACCEN00_EN9_OFF (9u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN0 */
|
||||
#define IFX_INT_ACCEN10_EN0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN0 */
|
||||
#define IFX_INT_ACCEN10_EN0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN0 */
|
||||
#define IFX_INT_ACCEN10_EN0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN10 */
|
||||
#define IFX_INT_ACCEN10_EN10_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN10 */
|
||||
#define IFX_INT_ACCEN10_EN10_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN10 */
|
||||
#define IFX_INT_ACCEN10_EN10_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN11 */
|
||||
#define IFX_INT_ACCEN10_EN11_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN11 */
|
||||
#define IFX_INT_ACCEN10_EN11_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN11 */
|
||||
#define IFX_INT_ACCEN10_EN11_OFF (11u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN12 */
|
||||
#define IFX_INT_ACCEN10_EN12_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN12 */
|
||||
#define IFX_INT_ACCEN10_EN12_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN12 */
|
||||
#define IFX_INT_ACCEN10_EN12_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN13 */
|
||||
#define IFX_INT_ACCEN10_EN13_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN13 */
|
||||
#define IFX_INT_ACCEN10_EN13_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN13 */
|
||||
#define IFX_INT_ACCEN10_EN13_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN14 */
|
||||
#define IFX_INT_ACCEN10_EN14_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN14 */
|
||||
#define IFX_INT_ACCEN10_EN14_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN14 */
|
||||
#define IFX_INT_ACCEN10_EN14_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN15 */
|
||||
#define IFX_INT_ACCEN10_EN15_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN15 */
|
||||
#define IFX_INT_ACCEN10_EN15_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN15 */
|
||||
#define IFX_INT_ACCEN10_EN15_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN16 */
|
||||
#define IFX_INT_ACCEN10_EN16_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN16 */
|
||||
#define IFX_INT_ACCEN10_EN16_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN16 */
|
||||
#define IFX_INT_ACCEN10_EN16_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN17 */
|
||||
#define IFX_INT_ACCEN10_EN17_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN17 */
|
||||
#define IFX_INT_ACCEN10_EN17_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN17 */
|
||||
#define IFX_INT_ACCEN10_EN17_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN18 */
|
||||
#define IFX_INT_ACCEN10_EN18_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN18 */
|
||||
#define IFX_INT_ACCEN10_EN18_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN18 */
|
||||
#define IFX_INT_ACCEN10_EN18_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN19 */
|
||||
#define IFX_INT_ACCEN10_EN19_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN19 */
|
||||
#define IFX_INT_ACCEN10_EN19_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN19 */
|
||||
#define IFX_INT_ACCEN10_EN19_OFF (19u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN1 */
|
||||
#define IFX_INT_ACCEN10_EN1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN1 */
|
||||
#define IFX_INT_ACCEN10_EN1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN1 */
|
||||
#define IFX_INT_ACCEN10_EN1_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN20 */
|
||||
#define IFX_INT_ACCEN10_EN20_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN20 */
|
||||
#define IFX_INT_ACCEN10_EN20_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN20 */
|
||||
#define IFX_INT_ACCEN10_EN20_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN21 */
|
||||
#define IFX_INT_ACCEN10_EN21_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN21 */
|
||||
#define IFX_INT_ACCEN10_EN21_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN21 */
|
||||
#define IFX_INT_ACCEN10_EN21_OFF (21u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN22 */
|
||||
#define IFX_INT_ACCEN10_EN22_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN22 */
|
||||
#define IFX_INT_ACCEN10_EN22_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN22 */
|
||||
#define IFX_INT_ACCEN10_EN22_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN23 */
|
||||
#define IFX_INT_ACCEN10_EN23_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN23 */
|
||||
#define IFX_INT_ACCEN10_EN23_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN23 */
|
||||
#define IFX_INT_ACCEN10_EN23_OFF (23u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN24 */
|
||||
#define IFX_INT_ACCEN10_EN24_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN24 */
|
||||
#define IFX_INT_ACCEN10_EN24_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN24 */
|
||||
#define IFX_INT_ACCEN10_EN24_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN25 */
|
||||
#define IFX_INT_ACCEN10_EN25_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN25 */
|
||||
#define IFX_INT_ACCEN10_EN25_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN25 */
|
||||
#define IFX_INT_ACCEN10_EN25_OFF (25u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN26 */
|
||||
#define IFX_INT_ACCEN10_EN26_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN26 */
|
||||
#define IFX_INT_ACCEN10_EN26_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN26 */
|
||||
#define IFX_INT_ACCEN10_EN26_OFF (26u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN27 */
|
||||
#define IFX_INT_ACCEN10_EN27_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN27 */
|
||||
#define IFX_INT_ACCEN10_EN27_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN27 */
|
||||
#define IFX_INT_ACCEN10_EN27_OFF (27u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN28 */
|
||||
#define IFX_INT_ACCEN10_EN28_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN28 */
|
||||
#define IFX_INT_ACCEN10_EN28_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN28 */
|
||||
#define IFX_INT_ACCEN10_EN28_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN29 */
|
||||
#define IFX_INT_ACCEN10_EN29_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN29 */
|
||||
#define IFX_INT_ACCEN10_EN29_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN29 */
|
||||
#define IFX_INT_ACCEN10_EN29_OFF (29u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN2 */
|
||||
#define IFX_INT_ACCEN10_EN2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN2 */
|
||||
#define IFX_INT_ACCEN10_EN2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN2 */
|
||||
#define IFX_INT_ACCEN10_EN2_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN30 */
|
||||
#define IFX_INT_ACCEN10_EN30_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN30 */
|
||||
#define IFX_INT_ACCEN10_EN30_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN30 */
|
||||
#define IFX_INT_ACCEN10_EN30_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN31 */
|
||||
#define IFX_INT_ACCEN10_EN31_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN31 */
|
||||
#define IFX_INT_ACCEN10_EN31_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN31 */
|
||||
#define IFX_INT_ACCEN10_EN31_OFF (31u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN3 */
|
||||
#define IFX_INT_ACCEN10_EN3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN3 */
|
||||
#define IFX_INT_ACCEN10_EN3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN3 */
|
||||
#define IFX_INT_ACCEN10_EN3_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN4 */
|
||||
#define IFX_INT_ACCEN10_EN4_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN4 */
|
||||
#define IFX_INT_ACCEN10_EN4_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN4 */
|
||||
#define IFX_INT_ACCEN10_EN4_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN5 */
|
||||
#define IFX_INT_ACCEN10_EN5_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN5 */
|
||||
#define IFX_INT_ACCEN10_EN5_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN5 */
|
||||
#define IFX_INT_ACCEN10_EN5_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN6 */
|
||||
#define IFX_INT_ACCEN10_EN6_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN6 */
|
||||
#define IFX_INT_ACCEN10_EN6_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN6 */
|
||||
#define IFX_INT_ACCEN10_EN6_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN7 */
|
||||
#define IFX_INT_ACCEN10_EN7_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN7 */
|
||||
#define IFX_INT_ACCEN10_EN7_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN7 */
|
||||
#define IFX_INT_ACCEN10_EN7_OFF (7u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN8 */
|
||||
#define IFX_INT_ACCEN10_EN8_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN8 */
|
||||
#define IFX_INT_ACCEN10_EN8_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN8 */
|
||||
#define IFX_INT_ACCEN10_EN8_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ACCEN10_Bits.EN9 */
|
||||
#define IFX_INT_ACCEN10_EN9_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ACCEN10_Bits.EN9 */
|
||||
#define IFX_INT_ACCEN10_EN9_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ACCEN10_Bits.EN9 */
|
||||
#define IFX_INT_ACCEN10_EN9_OFF (9u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ICU_ECR_Bits.ECC */
|
||||
#define IFX_INT_ICU_ECR_ECC_LEN (6u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ICU_ECR_Bits.ECC */
|
||||
#define IFX_INT_ICU_ECR_ECC_MSK (0x3fu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ICU_ECR_Bits.ECC */
|
||||
#define IFX_INT_ICU_ECR_ECC_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ICU_ECR_Bits.EOV */
|
||||
#define IFX_INT_ICU_ECR_EOV_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ICU_ECR_Bits.EOV */
|
||||
#define IFX_INT_ICU_ECR_EOV_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ICU_ECR_Bits.EOV */
|
||||
#define IFX_INT_ICU_ECR_EOV_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ICU_ECR_Bits.ID */
|
||||
#define IFX_INT_ICU_ECR_ID_LEN (10u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ICU_ECR_Bits.ID */
|
||||
#define IFX_INT_ICU_ECR_ID_MSK (0x3ffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ICU_ECR_Bits.ID */
|
||||
#define IFX_INT_ICU_ECR_ID_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ICU_ECR_Bits.PN */
|
||||
#define IFX_INT_ICU_ECR_PN_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ICU_ECR_Bits.PN */
|
||||
#define IFX_INT_ICU_ECR_PN_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ICU_ECR_Bits.PN */
|
||||
#define IFX_INT_ICU_ECR_PN_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ICU_ECR_Bits.STAT */
|
||||
#define IFX_INT_ICU_ECR_STAT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ICU_ECR_Bits.STAT */
|
||||
#define IFX_INT_ICU_ECR_STAT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ICU_ECR_Bits.STAT */
|
||||
#define IFX_INT_ICU_ECR_STAT_OFF (31u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ICU_LASR_Bits.ECC */
|
||||
#define IFX_INT_ICU_LASR_ECC_LEN (6u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ICU_LASR_Bits.ECC */
|
||||
#define IFX_INT_ICU_LASR_ECC_MSK (0x3fu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ICU_LASR_Bits.ECC */
|
||||
#define IFX_INT_ICU_LASR_ECC_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ICU_LASR_Bits.ID */
|
||||
#define IFX_INT_ICU_LASR_ID_LEN (10u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ICU_LASR_Bits.ID */
|
||||
#define IFX_INT_ICU_LASR_ID_MSK (0x3ffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ICU_LASR_Bits.ID */
|
||||
#define IFX_INT_ICU_LASR_ID_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ICU_LASR_Bits.PN */
|
||||
#define IFX_INT_ICU_LASR_PN_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ICU_LASR_Bits.PN */
|
||||
#define IFX_INT_ICU_LASR_PN_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ICU_LASR_Bits.PN */
|
||||
#define IFX_INT_ICU_LASR_PN_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ICU_LWSR_Bits.ECC */
|
||||
#define IFX_INT_ICU_LWSR_ECC_LEN (6u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ICU_LWSR_Bits.ECC */
|
||||
#define IFX_INT_ICU_LWSR_ECC_MSK (0x3fu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ICU_LWSR_Bits.ECC */
|
||||
#define IFX_INT_ICU_LWSR_ECC_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ICU_LWSR_Bits.ID */
|
||||
#define IFX_INT_ICU_LWSR_ID_LEN (10u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ICU_LWSR_Bits.ID */
|
||||
#define IFX_INT_ICU_LWSR_ID_MSK (0x3ffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ICU_LWSR_Bits.ID */
|
||||
#define IFX_INT_ICU_LWSR_ID_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ICU_LWSR_Bits.PN */
|
||||
#define IFX_INT_ICU_LWSR_PN_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ICU_LWSR_Bits.PN */
|
||||
#define IFX_INT_ICU_LWSR_PN_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ICU_LWSR_Bits.PN */
|
||||
#define IFX_INT_ICU_LWSR_PN_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ICU_LWSR_Bits.STAT */
|
||||
#define IFX_INT_ICU_LWSR_STAT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ICU_LWSR_Bits.STAT */
|
||||
#define IFX_INT_ICU_LWSR_STAT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ICU_LWSR_Bits.STAT */
|
||||
#define IFX_INT_ICU_LWSR_STAT_OFF (31u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ID_Bits.MODNUMBER */
|
||||
#define IFX_INT_ID_MODNUMBER_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ID_Bits.MODNUMBER */
|
||||
#define IFX_INT_ID_MODNUMBER_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ID_Bits.MODNUMBER */
|
||||
#define IFX_INT_ID_MODNUMBER_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ID_Bits.MODREV */
|
||||
#define IFX_INT_ID_MODREV_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ID_Bits.MODREV */
|
||||
#define IFX_INT_ID_MODREV_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ID_Bits.MODREV */
|
||||
#define IFX_INT_ID_MODREV_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_ID_Bits.MODTYPE */
|
||||
#define IFX_INT_ID_MODTYPE_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_ID_Bits.MODTYPE */
|
||||
#define IFX_INT_ID_MODTYPE_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_ID_Bits.MODTYPE */
|
||||
#define IFX_INT_ID_MODTYPE_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OIT_Bits.OE0 */
|
||||
#define IFX_INT_OIT_OE0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OIT_Bits.OE0 */
|
||||
#define IFX_INT_OIT_OE0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OIT_Bits.OE0 */
|
||||
#define IFX_INT_OIT_OE0_OFF (7u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OIT_Bits.OE1 */
|
||||
#define IFX_INT_OIT_OE1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OIT_Bits.OE1 */
|
||||
#define IFX_INT_OIT_OE1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OIT_Bits.OE1 */
|
||||
#define IFX_INT_OIT_OE1_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OIT_Bits.TOS0 */
|
||||
#define IFX_INT_OIT_TOS0_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OIT_Bits.TOS0 */
|
||||
#define IFX_INT_OIT_TOS0_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OIT_Bits.TOS0 */
|
||||
#define IFX_INT_OIT_TOS0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OIT_Bits.TOS1 */
|
||||
#define IFX_INT_OIT_TOS1_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OIT_Bits.TOS1 */
|
||||
#define IFX_INT_OIT_TOS1_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OIT_Bits.TOS1 */
|
||||
#define IFX_INT_OIT_TOS1_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OIXMS_Bits.MIRQ */
|
||||
#define IFX_INT_OIXMS_MIRQ_LEN (10u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OIXMS_Bits.MIRQ */
|
||||
#define IFX_INT_OIXMS_MIRQ_MSK (0x3ffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OIXMS_Bits.MIRQ */
|
||||
#define IFX_INT_OIXMS_MIRQ_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OIXS0_Bits.IRQ0 */
|
||||
#define IFX_INT_OIXS0_IRQ0_LEN (10u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OIXS0_Bits.IRQ0 */
|
||||
#define IFX_INT_OIXS0_IRQ0_MSK (0x3ffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OIXS0_Bits.IRQ0 */
|
||||
#define IFX_INT_OIXS0_IRQ0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OIXS0_Bits.IRQ1 */
|
||||
#define IFX_INT_OIXS0_IRQ1_LEN (10u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OIXS0_Bits.IRQ1 */
|
||||
#define IFX_INT_OIXS0_IRQ1_MSK (0x3ffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OIXS0_Bits.IRQ1 */
|
||||
#define IFX_INT_OIXS0_IRQ1_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OIXS1_Bits.IRQ2 */
|
||||
#define IFX_INT_OIXS1_IRQ2_LEN (10u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OIXS1_Bits.IRQ2 */
|
||||
#define IFX_INT_OIXS1_IRQ2_MSK (0x3ffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OIXS1_Bits.IRQ2 */
|
||||
#define IFX_INT_OIXS1_IRQ2_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OIXS1_Bits.IRQ3 */
|
||||
#define IFX_INT_OIXS1_IRQ3_LEN (10u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OIXS1_Bits.IRQ3 */
|
||||
#define IFX_INT_OIXS1_IRQ3_MSK (0x3ffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OIXS1_Bits.IRQ3 */
|
||||
#define IFX_INT_OIXS1_IRQ3_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OIXTS_Bits.OBS */
|
||||
#define IFX_INT_OIXTS_OBS_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OIXTS_Bits.OBS */
|
||||
#define IFX_INT_OIXTS_OBS_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OIXTS_Bits.OBS */
|
||||
#define IFX_INT_OIXTS_OBS_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OIXTS_Bits.TGS */
|
||||
#define IFX_INT_OIXTS_TGS_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OIXTS_Bits.TGS */
|
||||
#define IFX_INT_OIXTS_TGS_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OIXTS_Bits.TGS */
|
||||
#define IFX_INT_OIXTS_TGS_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OMISN_Bits.OTGB0 */
|
||||
#define IFX_INT_OMISN_OTGB0_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OMISN_Bits.OTGB0 */
|
||||
#define IFX_INT_OMISN_OTGB0_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OMISN_Bits.OTGB0 */
|
||||
#define IFX_INT_OMISN_OTGB0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OMISN_Bits.OTGB1 */
|
||||
#define IFX_INT_OMISN_OTGB1_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OMISN_Bits.OTGB1 */
|
||||
#define IFX_INT_OMISN_OTGB1_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OMISN_Bits.OTGB1 */
|
||||
#define IFX_INT_OMISN_OTGB1_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OMISP_Bits.OTGB0 */
|
||||
#define IFX_INT_OMISP_OTGB0_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OMISP_Bits.OTGB0 */
|
||||
#define IFX_INT_OMISP_OTGB0_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OMISP_Bits.OTGB0 */
|
||||
#define IFX_INT_OMISP_OTGB0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OMISP_Bits.OTGB1 */
|
||||
#define IFX_INT_OMISP_OTGB1_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OMISP_Bits.OTGB1 */
|
||||
#define IFX_INT_OMISP_OTGB1_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OMISP_Bits.OTGB1 */
|
||||
#define IFX_INT_OMISP_OTGB1_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OOBS_Bits.OTGB0 */
|
||||
#define IFX_INT_OOBS_OTGB0_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OOBS_Bits.OTGB0 */
|
||||
#define IFX_INT_OOBS_OTGB0_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OOBS_Bits.OTGB0 */
|
||||
#define IFX_INT_OOBS_OTGB0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OOBS_Bits.OTGB1 */
|
||||
#define IFX_INT_OOBS_OTGB1_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OOBS_Bits.OTGB1 */
|
||||
#define IFX_INT_OOBS_OTGB1_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OOBS_Bits.OTGB1 */
|
||||
#define IFX_INT_OOBS_OTGB1_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OSSIC_Bits.TGB */
|
||||
#define IFX_INT_OSSIC_TGB_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OSSIC_Bits.TGB */
|
||||
#define IFX_INT_OSSIC_TGB_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OSSIC_Bits.TGB */
|
||||
#define IFX_INT_OSSIC_TGB_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_INT_OSSIC_Bits.TGS */
|
||||
#define IFX_INT_OSSIC_TGS_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_OSSIC_Bits.TGS */
|
||||
#define IFX_INT_OSSIC_TGS_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_OSSIC_Bits.TGS */
|
||||
#define IFX_INT_OSSIC_TGS_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_SRB0_Bits.TRIG0 */
|
||||
#define IFX_INT_SRB0_TRIG0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_SRB0_Bits.TRIG0 */
|
||||
#define IFX_INT_SRB0_TRIG0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_SRB0_Bits.TRIG0 */
|
||||
#define IFX_INT_SRB0_TRIG0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_SRB0_Bits.TRIG1 */
|
||||
#define IFX_INT_SRB0_TRIG1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_SRB0_Bits.TRIG1 */
|
||||
#define IFX_INT_SRB0_TRIG1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_SRB0_Bits.TRIG1 */
|
||||
#define IFX_INT_SRB0_TRIG1_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_INT_SRB0_Bits.TRIG2 */
|
||||
#define IFX_INT_SRB0_TRIG2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_SRB0_Bits.TRIG2 */
|
||||
#define IFX_INT_SRB0_TRIG2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_SRB0_Bits.TRIG2 */
|
||||
#define IFX_INT_SRB0_TRIG2_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_INT_SRB0_Bits.TRIG3 */
|
||||
#define IFX_INT_SRB0_TRIG3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_SRB0_Bits.TRIG3 */
|
||||
#define IFX_INT_SRB0_TRIG3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_SRB0_Bits.TRIG3 */
|
||||
#define IFX_INT_SRB0_TRIG3_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_INT_SRB1_Bits.TRIG0 */
|
||||
#define IFX_INT_SRB1_TRIG0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_SRB1_Bits.TRIG0 */
|
||||
#define IFX_INT_SRB1_TRIG0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_SRB1_Bits.TRIG0 */
|
||||
#define IFX_INT_SRB1_TRIG0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_INT_SRB1_Bits.TRIG1 */
|
||||
#define IFX_INT_SRB1_TRIG1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_SRB1_Bits.TRIG1 */
|
||||
#define IFX_INT_SRB1_TRIG1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_SRB1_Bits.TRIG1 */
|
||||
#define IFX_INT_SRB1_TRIG1_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_INT_SRB1_Bits.TRIG2 */
|
||||
#define IFX_INT_SRB1_TRIG2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_SRB1_Bits.TRIG2 */
|
||||
#define IFX_INT_SRB1_TRIG2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_SRB1_Bits.TRIG2 */
|
||||
#define IFX_INT_SRB1_TRIG2_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_INT_SRB1_Bits.TRIG3 */
|
||||
#define IFX_INT_SRB1_TRIG3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_INT_SRB1_Bits.TRIG3 */
|
||||
#define IFX_INT_SRB1_TRIG3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_INT_SRB1_Bits.TRIG3 */
|
||||
#define IFX_INT_SRB1_TRIG3_OFF (3u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXINT_BF_H */
|
||||
@@ -1,171 +0,0 @@
|
||||
/**
|
||||
* \file IfxInt_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Int_Cfg Int address
|
||||
* \ingroup IfxLld_Int
|
||||
*
|
||||
* \defgroup IfxLld_Int_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Int_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Int_Cfg_Int 2-INT
|
||||
* \ingroup IfxLld_Int_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXINT_REG_H
|
||||
#define IFXINT_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxInt_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Int_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief Interrupt router object */
|
||||
#define MODULE_INT /*lint --e(923)*/ (*(Ifx_INT*)0xF0037000u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Int_Cfg_Int
|
||||
* \{ */
|
||||
|
||||
/** \brief F4, Access Enable Register 0 */
|
||||
#define INT_ACCEN00 /*lint --e(923)*/ (*(volatile Ifx_INT_ACCEN00*)0xF00370F4u)
|
||||
|
||||
/** \brief F0, Kernel 0 Access Enable Register 1 */
|
||||
#define INT_ACCEN01 /*lint --e(923)*/ (*(volatile Ifx_INT_ACCEN01*)0xF00370F0u)
|
||||
|
||||
/** \brief FC, Kernel 1 Access Enable Register 0 */
|
||||
#define INT_ACCEN10 /*lint --e(923)*/ (*(volatile Ifx_INT_ACCEN10*)0xF00370FCu)
|
||||
|
||||
/** \brief F8, Kernel 1 Access Enable Register 1 */
|
||||
#define INT_ACCEN11 /*lint --e(923)*/ (*(volatile Ifx_INT_ACCEN11*)0xF00370F8u)
|
||||
|
||||
/** \brief 108, Error Capture Register */
|
||||
#define INT_CH0_ECR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_ECR*)0xF0037108u)
|
||||
|
||||
/** Alias (User Manual Name) for INT_CH0_ECR.
|
||||
* To use register names with standard convension, please use INT_CH0_ECR.
|
||||
*/
|
||||
#define INT_ECR0 (INT_CH0_ECR)
|
||||
|
||||
/** \brief 104, Last Acknowledged Service Request Register */
|
||||
#define INT_CH0_LASR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_LASR*)0xF0037104u)
|
||||
|
||||
/** Alias (User Manual Name) for INT_CH0_LASR.
|
||||
* To use register names with standard convension, please use INT_CH0_LASR.
|
||||
*/
|
||||
#define INT_LASR0 (INT_CH0_LASR)
|
||||
|
||||
/** \brief 100, Latest Winning Service Request Register */
|
||||
#define INT_CH0_LWSR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_LWSR*)0xF0037100u)
|
||||
|
||||
/** Alias (User Manual Name) for INT_CH0_LWSR.
|
||||
* To use register names with standard convension, please use INT_CH0_LWSR.
|
||||
*/
|
||||
#define INT_LWSR0 (INT_CH0_LWSR)
|
||||
|
||||
/** \brief 118, Error Capture Register */
|
||||
#define INT_CH1_ECR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_ECR*)0xF0037118u)
|
||||
|
||||
/** Alias (User Manual Name) for INT_CH1_ECR.
|
||||
* To use register names with standard convension, please use INT_CH1_ECR.
|
||||
*/
|
||||
#define INT_ECR1 (INT_CH1_ECR)
|
||||
|
||||
/** \brief 114, Last Acknowledged Service Request Register */
|
||||
#define INT_CH1_LASR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_LASR*)0xF0037114u)
|
||||
|
||||
/** Alias (User Manual Name) for INT_CH1_LASR.
|
||||
* To use register names with standard convension, please use INT_CH1_LASR.
|
||||
*/
|
||||
#define INT_LASR1 (INT_CH1_LASR)
|
||||
|
||||
/** \brief 110, Latest Winning Service Request Register */
|
||||
#define INT_CH1_LWSR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_LWSR*)0xF0037110u)
|
||||
|
||||
/** Alias (User Manual Name) for INT_CH1_LWSR.
|
||||
* To use register names with standard convension, please use INT_CH1_LWSR.
|
||||
*/
|
||||
#define INT_LWSR1 (INT_CH1_LWSR)
|
||||
|
||||
/** \brief 138, Error Capture Register */
|
||||
#define INT_CH3_ECR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_ECR*)0xF0037138u)
|
||||
|
||||
/** Alias (User Manual Name) for INT_CH3_ECR.
|
||||
* To use register names with standard convension, please use INT_CH3_ECR.
|
||||
*/
|
||||
#define INT_ECR3 (INT_CH3_ECR)
|
||||
|
||||
/** \brief 134, Last Acknowledged Service Request Register */
|
||||
#define INT_CH3_LASR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_LASR*)0xF0037134u)
|
||||
|
||||
/** Alias (User Manual Name) for INT_CH3_LASR.
|
||||
* To use register names with standard convension, please use INT_CH3_LASR.
|
||||
*/
|
||||
#define INT_LASR3 (INT_CH3_LASR)
|
||||
|
||||
/** \brief 130, Latest Winning Service Request Register */
|
||||
#define INT_CH3_LWSR /*lint --e(923)*/ (*(volatile Ifx_INT_ICU_LWSR*)0xF0037130u)
|
||||
|
||||
/** Alias (User Manual Name) for INT_CH3_LWSR.
|
||||
* To use register names with standard convension, please use INT_CH3_LWSR.
|
||||
*/
|
||||
#define INT_LWSR3 (INT_CH3_LWSR)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define INT_ID /*lint --e(923)*/ (*(volatile Ifx_INT_ID*)0xF0037008u)
|
||||
|
||||
/** \brief A0, OTGM IRQ Trace */
|
||||
#define INT_OIT /*lint --e(923)*/ (*(volatile Ifx_INT_OIT*)0xF00370A0u)
|
||||
|
||||
/** \brief 8C, OTGM IRQ MUX Missed IRQ Select */
|
||||
#define INT_OIXMS /*lint --e(923)*/ (*(volatile Ifx_INT_OIXMS*)0xF003708Cu)
|
||||
|
||||
/** \brief 90, OTGM IRQ MUX Select 0 */
|
||||
#define INT_OIXS0 /*lint --e(923)*/ (*(volatile Ifx_INT_OIXS0*)0xF0037090u)
|
||||
|
||||
/** \brief 94, OTGM IRQ MUX Select 1 */
|
||||
#define INT_OIXS1 /*lint --e(923)*/ (*(volatile Ifx_INT_OIXS1*)0xF0037094u)
|
||||
|
||||
/** \brief 88, OTGM IRQ MUX Trigger Set Select */
|
||||
#define INT_OIXTS /*lint --e(923)*/ (*(volatile Ifx_INT_OIXTS*)0xF0037088u)
|
||||
|
||||
/** \brief A8, OTGM MCDS I/F Sensitivity Negedge */
|
||||
#define INT_OMISN /*lint --e(923)*/ (*(volatile Ifx_INT_OMISN*)0xF00370A8u)
|
||||
|
||||
/** \brief A4, OTGM MCDS I/F Sensitivity Posedge */
|
||||
#define INT_OMISP /*lint --e(923)*/ (*(volatile Ifx_INT_OMISP*)0xF00370A4u)
|
||||
|
||||
/** \brief 80, OTGM OTGB0/1 Status */
|
||||
#define INT_OOBS /*lint --e(923)*/ (*(volatile Ifx_INT_OOBS*)0xF0037080u)
|
||||
|
||||
/** \brief 84, OTGM SSI Control */
|
||||
#define INT_OSSIC /*lint --e(923)*/ (*(volatile Ifx_INT_OSSIC*)0xF0037084u)
|
||||
|
||||
/** \brief 10, Service Request Broadcast Register 0 */
|
||||
#define INT_SRB0 /*lint --e(923)*/ (*(volatile Ifx_INT_SRB0*)0xF0037010u)
|
||||
|
||||
/** \brief 14, Service Request Broadcast Register 1 */
|
||||
#define INT_SRB1 /*lint --e(923)*/ (*(volatile Ifx_INT_SRB1*)0xF0037014u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXINT_REG_H */
|
||||
@@ -1,482 +0,0 @@
|
||||
/**
|
||||
* \file IfxInt_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Int Int
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Int_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Int
|
||||
*
|
||||
* \defgroup IfxLld_Int_union Union
|
||||
* \ingroup IfxLld_Int
|
||||
*
|
||||
* \defgroup IfxLld_Int_struct Struct
|
||||
* \ingroup IfxLld_Int
|
||||
*
|
||||
*/
|
||||
#ifndef IFXINT_REGDEF_H
|
||||
#define IFXINT_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Int_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_INT_ACCEN00_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_INT_ACCEN00_Bits;
|
||||
|
||||
/** \brief Kernel 0 Access Enable Register 1 */
|
||||
typedef struct _Ifx_INT_ACCEN01_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_INT_ACCEN01_Bits;
|
||||
|
||||
/** \brief Kernel 1 Access Enable Register 0 */
|
||||
typedef struct _Ifx_INT_ACCEN10_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_INT_ACCEN10_Bits;
|
||||
|
||||
/** \brief Kernel 1 Access Enable Register 1 */
|
||||
typedef struct _Ifx_INT_ACCEN11_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_INT_ACCEN11_Bits;
|
||||
|
||||
/** \brief Error Capture Register */
|
||||
typedef struct _Ifx_INT_ICU_ECR_Bits
|
||||
{
|
||||
unsigned int PN:8; /**< \brief [7:0] Service Request Priority Number (rwh) */
|
||||
unsigned int reserved_8:2; /**< \brief \internal Reserved */
|
||||
unsigned int ECC:6; /**< \brief [15:10] Service Request ECC (rwh) */
|
||||
unsigned int ID:10; /**< \brief [25:16] Service Request Node Index Number (rwh) */
|
||||
unsigned int reserved_26:4; /**< \brief \internal Reserved */
|
||||
unsigned int EOV:1; /**< \brief [30:30] Error Overflow Bit (rwh) */
|
||||
unsigned int STAT:1; /**< \brief [31:31] Error Status Bit (rwh) */
|
||||
} Ifx_INT_ICU_ECR_Bits;
|
||||
|
||||
/** \brief Last Acknowledged Service Request Register */
|
||||
typedef struct _Ifx_INT_ICU_LASR_Bits
|
||||
{
|
||||
unsigned int PN:8; /**< \brief [7:0] Last Acknowledged Service Request Priority Number (r) */
|
||||
unsigned int reserved_8:2; /**< \brief \internal Reserved */
|
||||
unsigned int ECC:6; /**< \brief [15:10] Last Acknowledged Interrupt ECC (r) */
|
||||
unsigned int ID:10; /**< \brief [25:16] Last Acknowledged Interrupt SRN Index Number (r) */
|
||||
unsigned int reserved_26:6; /**< \brief \internal Reserved */
|
||||
} Ifx_INT_ICU_LASR_Bits;
|
||||
|
||||
/** \brief Latest Winning Service Request Register */
|
||||
typedef struct _Ifx_INT_ICU_LWSR_Bits
|
||||
{
|
||||
unsigned int PN:8; /**< \brief [7:0] Latest Winner Priority Number (r) */
|
||||
unsigned int reserved_8:2; /**< \brief \internal Reserved */
|
||||
unsigned int ECC:6; /**< \brief [15:10] Latest Winner ECC (r) */
|
||||
unsigned int ID:10; /**< \brief [25:16] Latest Winner Index Number (r) */
|
||||
unsigned int reserved_26:5; /**< \brief \internal Reserved */
|
||||
unsigned int STAT:1; /**< \brief [31:31] LWSR Register Status (r) */
|
||||
} Ifx_INT_ICU_LWSR_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_INT_ID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_INT_ID_Bits;
|
||||
|
||||
/** \brief OTGM IRQ Trace */
|
||||
typedef struct _Ifx_INT_OIT_Bits
|
||||
{
|
||||
unsigned int TOS0:2; /**< \brief [1:0] Type of Service for Observation on OTGB0 (rw) */
|
||||
unsigned int reserved_2:5; /**< \brief \internal Reserved */
|
||||
unsigned int OE0:1; /**< \brief [7:7] Output Enable for OTGB0 (rw) */
|
||||
unsigned int TOS1:2; /**< \brief [9:8] Type of Service for Observation on OTGB1 (rw) */
|
||||
unsigned int reserved_10:5; /**< \brief \internal Reserved */
|
||||
unsigned int OE1:1; /**< \brief [15:15] Output Enable for OTGB1 (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_INT_OIT_Bits;
|
||||
|
||||
/** \brief OTGM IRQ MUX Missed IRQ Select */
|
||||
typedef struct _Ifx_INT_OIXMS_Bits
|
||||
{
|
||||
unsigned int MIRQ:10; /**< \brief [9:0] SRN Index for Missed Interrupt Trigger (rw) */
|
||||
unsigned int reserved_10:22; /**< \brief \internal Reserved */
|
||||
} Ifx_INT_OIXMS_Bits;
|
||||
|
||||
/** \brief OTGM IRQ MUX Select 0 */
|
||||
typedef struct _Ifx_INT_OIXS0_Bits
|
||||
{
|
||||
unsigned int IRQ0:10; /**< \brief [9:0] SRN Index for Interrupt Trigger 0 (rw) */
|
||||
unsigned int reserved_10:6; /**< \brief \internal Reserved */
|
||||
unsigned int IRQ1:10; /**< \brief [25:16] SRN Index for Interrupt Trigger 1 (rw) */
|
||||
unsigned int reserved_26:6; /**< \brief \internal Reserved */
|
||||
} Ifx_INT_OIXS0_Bits;
|
||||
|
||||
/** \brief OTGM IRQ MUX Select 1 */
|
||||
typedef struct _Ifx_INT_OIXS1_Bits
|
||||
{
|
||||
unsigned int IRQ2:10; /**< \brief [9:0] SRN Index for Interrupt Trigger 2 (rw) */
|
||||
unsigned int reserved_10:6; /**< \brief \internal Reserved */
|
||||
unsigned int IRQ3:10; /**< \brief [25:16] SRN Index for Interrupt Trigger 3 (rw) */
|
||||
unsigned int reserved_26:6; /**< \brief \internal Reserved */
|
||||
} Ifx_INT_OIXS1_Bits;
|
||||
|
||||
/** \brief OTGM IRQ MUX Trigger Set Select */
|
||||
typedef struct _Ifx_INT_OIXTS_Bits
|
||||
{
|
||||
unsigned int TGS:2; /**< \brief [1:0] Trigger Set Select for OTGB0/1 Overlay (rw) */
|
||||
unsigned int reserved_2:6; /**< \brief \internal Reserved */
|
||||
unsigned int OBS:2; /**< \brief [9:8] Overlay Byte Select (rw) */
|
||||
unsigned int reserved_10:22; /**< \brief \internal Reserved */
|
||||
} Ifx_INT_OIXTS_Bits;
|
||||
|
||||
/** \brief OTGM MCDS I/F Sensitivity Negedge */
|
||||
typedef struct _Ifx_INT_OMISN_Bits
|
||||
{
|
||||
unsigned int OTGB0:16; /**< \brief [15:0] Bitwise Negedge Sensitivity for OTGB0 (rw) */
|
||||
unsigned int OTGB1:16; /**< \brief [31:16] Bitwise Negedge Sensitivity for OTGB1 (rw) */
|
||||
} Ifx_INT_OMISN_Bits;
|
||||
|
||||
/** \brief OTGM MCDS I/F Sensitivity Posedge */
|
||||
typedef struct _Ifx_INT_OMISP_Bits
|
||||
{
|
||||
unsigned int OTGB0:16; /**< \brief [15:0] Bitwise Posedge Sensitivity for OTGB0 (rw) */
|
||||
unsigned int OTGB1:16; /**< \brief [31:16] Bitwise Posedge Sensitivity for OTGB1 (rw) */
|
||||
} Ifx_INT_OMISP_Bits;
|
||||
|
||||
/** \brief OTGM OTGB0/1 Status */
|
||||
typedef struct _Ifx_INT_OOBS_Bits
|
||||
{
|
||||
unsigned int OTGB0:16; /**< \brief [15:0] Status of OTGB0 (rh) */
|
||||
unsigned int OTGB1:16; /**< \brief [31:16] Status of OTGB1 (rh) */
|
||||
} Ifx_INT_OOBS_Bits;
|
||||
|
||||
/** \brief OTGM SSI Control */
|
||||
typedef struct _Ifx_INT_OSSIC_Bits
|
||||
{
|
||||
unsigned int TGS:2; /**< \brief [1:0] Trigger Set for OTGB0/1 (rw) */
|
||||
unsigned int TGB:1; /**< \brief [2:2] OTGB0/1 Bus Select (rw) */
|
||||
unsigned int reserved_3:29; /**< \brief \internal Reserved */
|
||||
} Ifx_INT_OSSIC_Bits;
|
||||
|
||||
/** \brief Service Request Broadcast Register 0 */
|
||||
typedef struct _Ifx_INT_SRB0_Bits
|
||||
{
|
||||
unsigned int TRIG0:1; /**< \brief [0:0] General Purpose Service Request Trigger 0 (w) */
|
||||
unsigned int TRIG1:1; /**< \brief [1:1] General Purpose Service Request Trigger 1 (w) */
|
||||
unsigned int TRIG2:1; /**< \brief [2:2] General Purpose Service Request Trigger 2 (w) */
|
||||
unsigned int TRIG3:1; /**< \brief [3:3] General Purpose Service Request Trigger 3 (w) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_INT_SRB0_Bits;
|
||||
|
||||
/** \brief Service Request Broadcast Register 1 */
|
||||
typedef struct _Ifx_INT_SRB1_Bits
|
||||
{
|
||||
unsigned int TRIG0:1; /**< \brief [0:0] General Purpose Service Request Trigger 0 (w) */
|
||||
unsigned int TRIG1:1; /**< \brief [1:1] General Purpose Service Request Trigger 1 (w) */
|
||||
unsigned int TRIG2:1; /**< \brief [2:2] General Purpose Service Request Trigger 2 (w) */
|
||||
unsigned int TRIG3:1; /**< \brief [3:3] General Purpose Service Request Trigger 3 (w) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_INT_SRB1_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Int_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_ACCEN00_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_ACCEN00;
|
||||
|
||||
/** \brief Kernel 0 Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_ACCEN01_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_ACCEN01;
|
||||
|
||||
/** \brief Kernel 1 Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_ACCEN10_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_ACCEN10;
|
||||
|
||||
/** \brief Kernel 1 Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_ACCEN11_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_ACCEN11;
|
||||
|
||||
/** \brief Error Capture Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_ICU_ECR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_ICU_ECR;
|
||||
|
||||
/** \brief Last Acknowledged Service Request Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_ICU_LASR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_ICU_LASR;
|
||||
|
||||
/** \brief Latest Winning Service Request Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_ICU_LWSR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_ICU_LWSR;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_ID;
|
||||
|
||||
/** \brief OTGM IRQ Trace */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_OIT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_OIT;
|
||||
|
||||
/** \brief OTGM IRQ MUX Missed IRQ Select */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_OIXMS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_OIXMS;
|
||||
|
||||
/** \brief OTGM IRQ MUX Select 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_OIXS0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_OIXS0;
|
||||
|
||||
/** \brief OTGM IRQ MUX Select 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_OIXS1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_OIXS1;
|
||||
|
||||
/** \brief OTGM IRQ MUX Trigger Set Select */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_OIXTS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_OIXTS;
|
||||
|
||||
/** \brief OTGM MCDS I/F Sensitivity Negedge */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_OMISN_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_OMISN;
|
||||
|
||||
/** \brief OTGM MCDS I/F Sensitivity Posedge */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_OMISP_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_OMISP;
|
||||
|
||||
/** \brief OTGM OTGB0/1 Status */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_OOBS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_OOBS;
|
||||
|
||||
/** \brief OTGM SSI Control */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_OSSIC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_OSSIC;
|
||||
|
||||
/** \brief Service Request Broadcast Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_SRB0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_SRB0;
|
||||
|
||||
/** \brief Service Request Broadcast Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_INT_SRB1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_INT_SRB1;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Int_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L1
|
||||
* \{ */
|
||||
|
||||
/** \brief Interrupt router channel */
|
||||
typedef volatile struct _Ifx_INT_ICU
|
||||
{
|
||||
Ifx_INT_ICU_LWSR LWSR; /**< \brief 0, Latest Winning Service Request Register */
|
||||
Ifx_INT_ICU_LASR LASR; /**< \brief 4, Last Acknowledged Service Request Register */
|
||||
Ifx_INT_ICU_ECR ECR; /**< \brief 8, Error Capture Register */
|
||||
unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
|
||||
} Ifx_INT_ICU;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Int_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief Interrupt router object */
|
||||
typedef volatile struct _Ifx_INT
|
||||
{
|
||||
unsigned char reserved_0[8]; /**< \brief 0, \internal Reserved */
|
||||
Ifx_INT_ID ID; /**< \brief 8, Module Identification Register */
|
||||
unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
|
||||
Ifx_INT_SRB0 SRB0; /**< \brief 10, Service Request Broadcast Register 0 */
|
||||
Ifx_INT_SRB1 SRB1; /**< \brief 14, Service Request Broadcast Register 1 */
|
||||
unsigned char reserved_18[104]; /**< \brief 18, \internal Reserved */
|
||||
Ifx_INT_OOBS OOBS; /**< \brief 80, OTGM OTGB0/1 Status */
|
||||
Ifx_INT_OSSIC OSSIC; /**< \brief 84, OTGM SSI Control */
|
||||
Ifx_INT_OIXTS OIXTS; /**< \brief 88, OTGM IRQ MUX Trigger Set Select */
|
||||
Ifx_INT_OIXMS OIXMS; /**< \brief 8C, OTGM IRQ MUX Missed IRQ Select */
|
||||
Ifx_INT_OIXS0 OIXS0; /**< \brief 90, OTGM IRQ MUX Select 0 */
|
||||
Ifx_INT_OIXS1 OIXS1; /**< \brief 94, OTGM IRQ MUX Select 1 */
|
||||
unsigned char reserved_98[8]; /**< \brief 98, \internal Reserved */
|
||||
Ifx_INT_OIT OIT; /**< \brief A0, OTGM IRQ Trace */
|
||||
Ifx_INT_OMISP OMISP; /**< \brief A4, OTGM MCDS I/F Sensitivity Posedge */
|
||||
Ifx_INT_OMISN OMISN; /**< \brief A8, OTGM MCDS I/F Sensitivity Negedge */
|
||||
unsigned char reserved_AC[68]; /**< \brief AC, \internal Reserved */
|
||||
Ifx_INT_ACCEN01 ACCEN01; /**< \brief F0, Kernel 0 Access Enable Register 1 */
|
||||
Ifx_INT_ACCEN00 ACCEN00; /**< \brief F4, Access Enable Register 0 */
|
||||
Ifx_INT_ACCEN11 ACCEN11; /**< \brief F8, Kernel 1 Access Enable Register 1 */
|
||||
Ifx_INT_ACCEN10 ACCEN10; /**< \brief FC, Kernel 1 Access Enable Register 0 */
|
||||
Ifx_INT_ICU CH[4]; /**< \brief 100, Interrupt router channel */
|
||||
unsigned char reserved_140[3776]; /**< \brief 140, \internal Reserved */
|
||||
} Ifx_INT;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXINT_REGDEF_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,331 +0,0 @@
|
||||
/**
|
||||
* \file IfxIom_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Iom_Cfg Iom address
|
||||
* \ingroup IfxLld_Iom
|
||||
*
|
||||
* \defgroup IfxLld_Iom_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Iom_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Iom_Cfg_Iom 2-IOM
|
||||
* \ingroup IfxLld_Iom_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXIOM_REG_H
|
||||
#define IFXIOM_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxIom_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Iom_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief IOM object */
|
||||
#define MODULE_IOM /*lint --e(923)*/ (*(Ifx_IOM*)0xF0035000u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Iom_Cfg_Iom
|
||||
* \{ */
|
||||
|
||||
/** \brief 2C, IOM Access Enable Register 0 */
|
||||
#define IOM_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_IOM_ACCEN0*)0xF003502Cu)
|
||||
|
||||
/** \brief 28, IOM Access Enable Register 1 */
|
||||
#define IOM_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_IOM_ACCEN1*)0xF0035028u)
|
||||
|
||||
/** \brief 0, IOM Clock Control Register */
|
||||
#define IOM_CLC /*lint --e(923)*/ (*(volatile Ifx_IOM_CLC*)0xF0035000u)
|
||||
|
||||
/** \brief 30, IOM Event Combiner Module Counter Configuration Register */
|
||||
#define IOM_ECMCCFG /*lint --e(923)*/ (*(volatile Ifx_IOM_ECMCCFG*)0xF0035030u)
|
||||
|
||||
/** \brief 38, IOM Event Combiner Module Event Trigger History Register 0 */
|
||||
#define IOM_ECMETH0 /*lint --e(923)*/ (*(volatile Ifx_IOM_ECMETH0*)0xF0035038u)
|
||||
|
||||
/** \brief 3C, IOM Event Combiner Module Event Trigger History Register 1 */
|
||||
#define IOM_ECMETH1 /*lint --e(923)*/ (*(volatile Ifx_IOM_ECMETH1*)0xF003503Cu)
|
||||
|
||||
/** \brief 34, IOM Event Combiner Module Global Event Selection Register */
|
||||
#define IOM_ECMSELR /*lint --e(923)*/ (*(volatile Ifx_IOM_ECMSELR*)0xF0035034u)
|
||||
|
||||
/** \brief 80, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR0 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF0035080u)
|
||||
|
||||
/** \brief 84, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR1 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF0035084u)
|
||||
|
||||
/** \brief A8, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR10 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350A8u)
|
||||
|
||||
/** \brief AC, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR11 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350ACu)
|
||||
|
||||
/** \brief B0, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR12 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350B0u)
|
||||
|
||||
/** \brief B4, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR13 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350B4u)
|
||||
|
||||
/** \brief B8, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR14 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350B8u)
|
||||
|
||||
/** \brief BC, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR15 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350BCu)
|
||||
|
||||
/** \brief 88, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR2 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF0035088u)
|
||||
|
||||
/** \brief 8C, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR3 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF003508Cu)
|
||||
|
||||
/** \brief 90, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR4 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF0035090u)
|
||||
|
||||
/** \brief 94, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR5 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF0035094u)
|
||||
|
||||
/** \brief 98, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR6 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF0035098u)
|
||||
|
||||
/** \brief 9C, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR7 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF003509Cu)
|
||||
|
||||
/** \brief A0, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR8 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350A0u)
|
||||
|
||||
/** \brief A4, IOM Filter and Prescaler Cell Control Register */
|
||||
#define IOM_FPCCTR9 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCCTR*)0xF00350A4u)
|
||||
|
||||
/** \brief 78, IOM Filter and Prescaler Cells Rising & Falling Edge Status
|
||||
* Register */
|
||||
#define IOM_FPCESR /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCESR*)0xF0035078u)
|
||||
|
||||
/** \brief C0, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM0 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350C0u)
|
||||
|
||||
/** \brief C4, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM1 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350C4u)
|
||||
|
||||
/** \brief E8, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM10 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350E8u)
|
||||
|
||||
/** \brief EC, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM11 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350ECu)
|
||||
|
||||
/** \brief F0, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM12 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350F0u)
|
||||
|
||||
/** \brief F4, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM13 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350F4u)
|
||||
|
||||
/** \brief F8, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM14 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350F8u)
|
||||
|
||||
/** \brief FC, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM15 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350FCu)
|
||||
|
||||
/** \brief C8, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM2 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350C8u)
|
||||
|
||||
/** \brief CC, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM3 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350CCu)
|
||||
|
||||
/** \brief D0, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM4 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350D0u)
|
||||
|
||||
/** \brief D4, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM5 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350D4u)
|
||||
|
||||
/** \brief D8, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM6 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350D8u)
|
||||
|
||||
/** \brief DC, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM7 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350DCu)
|
||||
|
||||
/** \brief E0, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM8 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350E0u)
|
||||
|
||||
/** \brief E4, IOM Filter and Prescaler Cell Timer Register k */
|
||||
#define IOM_FPCTIM9 /*lint --e(923)*/ (*(volatile Ifx_IOM_FPCTIM*)0xF00350E4u)
|
||||
|
||||
/** \brief 40, IOM GTM Input EXOR Combiner Selection Register */
|
||||
#define IOM_GTMEXR /*lint --e(923)*/ (*(volatile Ifx_IOM_GTMEXR*)0xF0035040u)
|
||||
|
||||
/** \brief 8, IOM Identification Register */
|
||||
#define IOM_ID /*lint --e(923)*/ (*(volatile Ifx_IOM_ID*)0xF0035008u)
|
||||
|
||||
/** \brief 24, IOM Kernel Reset Register 0 */
|
||||
#define IOM_KRST0 /*lint --e(923)*/ (*(volatile Ifx_IOM_KRST0*)0xF0035024u)
|
||||
|
||||
/** \brief 20, IOM Kernel Reset Register 1 */
|
||||
#define IOM_KRST1 /*lint --e(923)*/ (*(volatile Ifx_IOM_KRST1*)0xF0035020u)
|
||||
|
||||
/** \brief 1C, IOM Kernel Reset Status Clear Register */
|
||||
#define IOM_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_IOM_KRSTCLR*)0xF003501Cu)
|
||||
|
||||
/** \brief 180, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG0 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF0035180u)
|
||||
|
||||
/** \brief 184, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG1 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF0035184u)
|
||||
|
||||
/** \brief 1A8, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG10 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351A8u)
|
||||
|
||||
/** \brief 1AC, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG11 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351ACu)
|
||||
|
||||
/** \brief 1B0, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG12 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351B0u)
|
||||
|
||||
/** \brief 1B4, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG13 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351B4u)
|
||||
|
||||
/** \brief 1B8, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG14 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351B8u)
|
||||
|
||||
/** \brief 1BC, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG15 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351BCu)
|
||||
|
||||
/** \brief 188, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG2 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF0035188u)
|
||||
|
||||
/** \brief 18C, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG3 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF003518Cu)
|
||||
|
||||
/** \brief 190, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG4 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF0035190u)
|
||||
|
||||
/** \brief 194, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG5 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF0035194u)
|
||||
|
||||
/** \brief 198, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG6 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF0035198u)
|
||||
|
||||
/** \brief 19C, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG7 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF003519Cu)
|
||||
|
||||
/** \brief 1A0, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG8 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351A0u)
|
||||
|
||||
/** \brief 1A4, IOM Logic Analyzer Module Configuration Register */
|
||||
#define IOM_LAMCFG9 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMCFG*)0xF00351A4u)
|
||||
|
||||
/** \brief 100, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC0 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035100u)
|
||||
|
||||
/** \brief 104, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC1 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035104u)
|
||||
|
||||
/** \brief 128, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC10 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035128u)
|
||||
|
||||
/** \brief 12C, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC11 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF003512Cu)
|
||||
|
||||
/** \brief 130, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC12 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035130u)
|
||||
|
||||
/** \brief 134, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC13 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035134u)
|
||||
|
||||
/** \brief 138, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC14 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035138u)
|
||||
|
||||
/** \brief 13C, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC15 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF003513Cu)
|
||||
|
||||
/** \brief 108, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC2 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035108u)
|
||||
|
||||
/** \brief 10C, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC3 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF003510Cu)
|
||||
|
||||
/** \brief 110, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC4 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035110u)
|
||||
|
||||
/** \brief 114, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC5 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035114u)
|
||||
|
||||
/** \brief 118, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC6 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035118u)
|
||||
|
||||
/** \brief 11C, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC7 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF003511Cu)
|
||||
|
||||
/** \brief 120, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC8 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035120u)
|
||||
|
||||
/** \brief 124, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
#define IOM_LAMEWC9 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWC*)0xF0035124u)
|
||||
|
||||
/** \brief 1C0, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS0 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351C0u)
|
||||
|
||||
/** \brief 1C4, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS1 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351C4u)
|
||||
|
||||
/** \brief 1E8, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS10 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351E8u)
|
||||
|
||||
/** \brief 1EC, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS11 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351ECu)
|
||||
|
||||
/** \brief 1F0, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS12 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351F0u)
|
||||
|
||||
/** \brief 1F4, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS13 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351F4u)
|
||||
|
||||
/** \brief 1F8, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS14 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351F8u)
|
||||
|
||||
/** \brief 1FC, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS15 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351FCu)
|
||||
|
||||
/** \brief 1C8, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS2 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351C8u)
|
||||
|
||||
/** \brief 1CC, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS3 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351CCu)
|
||||
|
||||
/** \brief 1D0, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS4 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351D0u)
|
||||
|
||||
/** \brief 1D4, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS5 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351D4u)
|
||||
|
||||
/** \brief 1D8, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS6 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351D8u)
|
||||
|
||||
/** \brief 1DC, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS7 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351DCu)
|
||||
|
||||
/** \brief 1E0, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS8 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351E0u)
|
||||
|
||||
/** \brief 1E4, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
#define IOM_LAMEWS9 /*lint --e(923)*/ (*(volatile Ifx_IOM_LAMEWS*)0xF00351E4u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXIOM_REG_H */
|
||||
@@ -1,533 +0,0 @@
|
||||
/**
|
||||
* \file IfxIom_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Iom Iom
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Iom_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Iom
|
||||
*
|
||||
* \defgroup IfxLld_Iom_union Union
|
||||
* \ingroup IfxLld_Iom
|
||||
*
|
||||
* \defgroup IfxLld_Iom_struct Struct
|
||||
* \ingroup IfxLld_Iom
|
||||
*
|
||||
*/
|
||||
#ifndef IFXIOM_REGDEF_H
|
||||
#define IFXIOM_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Iom_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief IOM Access Enable Register 0 */
|
||||
typedef struct _Ifx_IOM_ACCEN0_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_IOM_ACCEN0_Bits;
|
||||
|
||||
/** \brief IOM Access Enable Register 1 */
|
||||
typedef struct _Ifx_IOM_ACCEN1_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_IOM_ACCEN1_Bits;
|
||||
|
||||
/** \brief IOM Clock Control Register */
|
||||
typedef struct _Ifx_IOM_CLC_Bits
|
||||
{
|
||||
unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
|
||||
unsigned int reserved_2:1; /**< \brief \internal Reserved */
|
||||
unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
|
||||
unsigned int reserved_4:4; /**< \brief \internal Reserved */
|
||||
unsigned int RMC:8; /**< \brief [15:8] 8-bit Clock Divider Value in RUN Mode (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_IOM_CLC_Bits;
|
||||
|
||||
/** \brief IOM Event Combiner Module Counter Configuration Register */
|
||||
typedef struct _Ifx_IOM_ECMCCFG_Bits
|
||||
{
|
||||
unsigned int SELC0:4; /**< \brief [3:0] Event Channel Select (rw) */
|
||||
unsigned int THRC0:4; /**< \brief [7:4] Channel Event Counter Threshold (rw) */
|
||||
unsigned int SELC1:4; /**< \brief [11:8] Event Channel Select (rw) */
|
||||
unsigned int THCR1:4; /**< \brief [15:12] Channel Event Counter Threshold (rw) */
|
||||
unsigned int SELC2:4; /**< \brief [19:16] Event Channel Select (rw) */
|
||||
unsigned int THCR2:4; /**< \brief [23:20] Channel Event Counter Threshold (rw) */
|
||||
unsigned int SELC3:4; /**< \brief [27:24] Event Channel Select (rw) */
|
||||
unsigned int THCR3:4; /**< \brief [31:28] Channel Event Counter Threshold (rw) */
|
||||
} Ifx_IOM_ECMCCFG_Bits;
|
||||
|
||||
/** \brief IOM Event Combiner Module Event Trigger History Register 0 */
|
||||
typedef struct _Ifx_IOM_ECMETH0_Bits
|
||||
{
|
||||
unsigned int ETA0:1; /**< \brief [0:0] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA1:1; /**< \brief [1:1] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA2:1; /**< \brief [2:2] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA3:1; /**< \brief [3:3] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA4:1; /**< \brief [4:4] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA5:1; /**< \brief [5:5] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA6:1; /**< \brief [6:6] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA7:1; /**< \brief [7:7] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA8:1; /**< \brief [8:8] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA9:1; /**< \brief [9:9] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA10:1; /**< \brief [10:10] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA11:1; /**< \brief [11:11] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA12:1; /**< \brief [12:12] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA13:1; /**< \brief [13:13] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA14:1; /**< \brief [14:14] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETA15:1; /**< \brief [15:15] LAM 0-15 Event Trigger Activity (last) (rwh) */
|
||||
unsigned int ETB0:1; /**< \brief [16:16] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB1:1; /**< \brief [17:17] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB2:1; /**< \brief [18:18] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB3:1; /**< \brief [19:19] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB4:1; /**< \brief [20:20] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB5:1; /**< \brief [21:21] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB6:1; /**< \brief [22:22] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB7:1; /**< \brief [23:23] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB8:1; /**< \brief [24:24] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB9:1; /**< \brief [25:25] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB10:1; /**< \brief [26:26] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB11:1; /**< \brief [27:27] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB12:1; /**< \brief [28:28] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB13:1; /**< \brief [29:29] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB14:1; /**< \brief [30:30] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
unsigned int ETB15:1; /**< \brief [31:31] LAM 0-15 Event Trigger Activity (previous ETA0-15) (rwh) */
|
||||
} Ifx_IOM_ECMETH0_Bits;
|
||||
|
||||
/** \brief IOM Event Combiner Module Event Trigger History Register 1 */
|
||||
typedef struct _Ifx_IOM_ECMETH1_Bits
|
||||
{
|
||||
unsigned int ETC0:1; /**< \brief [0:0] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC1:1; /**< \brief [1:1] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC2:1; /**< \brief [2:2] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC3:1; /**< \brief [3:3] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC4:1; /**< \brief [4:4] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC5:1; /**< \brief [5:5] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC6:1; /**< \brief [6:6] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC7:1; /**< \brief [7:7] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC8:1; /**< \brief [8:8] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC9:1; /**< \brief [9:9] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC10:1; /**< \brief [10:10] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC11:1; /**< \brief [11:11] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC12:1; /**< \brief [12:12] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC13:1; /**< \brief [13:13] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC14:1; /**< \brief [14:14] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETC15:1; /**< \brief [15:15] LAM 0-15 Event Trigger Activity (previous ETB0-15) (rwh) */
|
||||
unsigned int ETD0:1; /**< \brief [16:16] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD1:1; /**< \brief [17:17] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD2:1; /**< \brief [18:18] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD3:1; /**< \brief [19:19] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD4:1; /**< \brief [20:20] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD5:1; /**< \brief [21:21] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD6:1; /**< \brief [22:22] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD7:1; /**< \brief [23:23] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD8:1; /**< \brief [24:24] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD9:1; /**< \brief [25:25] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD10:1; /**< \brief [26:26] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD11:1; /**< \brief [27:27] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD12:1; /**< \brief [28:28] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD13:1; /**< \brief [29:29] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD14:1; /**< \brief [30:30] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
unsigned int ETD15:1; /**< \brief [31:31] LAM 0-15 Event Trigger Activity (previous ETC0-15) (rwh) */
|
||||
} Ifx_IOM_ECMETH1_Bits;
|
||||
|
||||
/** \brief IOM Event Combiner Module Global Event Selection Register */
|
||||
typedef struct _Ifx_IOM_ECMSELR_Bits
|
||||
{
|
||||
unsigned int CES0:1; /**< \brief [0:0] Event Combiner Selection (rw) */
|
||||
unsigned int CES1:1; /**< \brief [1:1] Event Combiner Selection (rw) */
|
||||
unsigned int CES2:1; /**< \brief [2:2] Event Combiner Selection (rw) */
|
||||
unsigned int CES3:1; /**< \brief [3:3] Event Combiner Selection (rw) */
|
||||
unsigned int CES4:1; /**< \brief [4:4] Event Combiner Selection (rw) */
|
||||
unsigned int CES5:1; /**< \brief [5:5] Event Combiner Selection (rw) */
|
||||
unsigned int CES6:1; /**< \brief [6:6] Event Combiner Selection (rw) */
|
||||
unsigned int CES7:1; /**< \brief [7:7] Event Combiner Selection (rw) */
|
||||
unsigned int CES8:1; /**< \brief [8:8] Event Combiner Selection (rw) */
|
||||
unsigned int CES9:1; /**< \brief [9:9] Event Combiner Selection (rw) */
|
||||
unsigned int CES10:1; /**< \brief [10:10] Event Combiner Selection (rw) */
|
||||
unsigned int CES11:1; /**< \brief [11:11] Event Combiner Selection (rw) */
|
||||
unsigned int CES12:1; /**< \brief [12:12] Event Combiner Selection (rw) */
|
||||
unsigned int CES13:1; /**< \brief [13:13] Event Combiner Selection (rw) */
|
||||
unsigned int CES14:1; /**< \brief [14:14] Event Combiner Selection (rw) */
|
||||
unsigned int CES15:1; /**< \brief [15:15] Event Combiner Selection (rw) */
|
||||
unsigned int CTS0:1; /**< \brief [16:16] Accumulated (Counted) Event Combiner Selection (rw) */
|
||||
unsigned int CTS1:1; /**< \brief [17:17] Accumulated (Counted) Event Combiner Selection (rw) */
|
||||
unsigned int CTS2:1; /**< \brief [18:18] Accumulated (Counted) Event Combiner Selection (rw) */
|
||||
unsigned int CTS3:1; /**< \brief [19:19] Accumulated (Counted) Event Combiner Selection (rw) */
|
||||
unsigned int reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_IOM_ECMSELR_Bits;
|
||||
|
||||
/** \brief IOM Filter and Prescaler Cell Control Register */
|
||||
typedef struct _Ifx_IOM_FPCCTR_Bits
|
||||
{
|
||||
unsigned int CMP:16; /**< \brief [15:0] Threshold Value of Filter & Prescaler Cell k (rw) */
|
||||
unsigned int MOD:3; /**< \brief [18:16] Operation Mode Selection for Filter & Prescaler Cell k (rw) */
|
||||
unsigned int ISM:2; /**< \brief [20:19] Monitor Input Signal Selection for Filter & Prescaler Cell k (rw) */
|
||||
unsigned int reserved_21:1; /**< \brief \internal Reserved */
|
||||
unsigned int RTG:1; /**< \brief [22:22] Reset Timer behaviour for Filter & Prescaler Cell k on Glitch (rw) */
|
||||
unsigned int reserved_23:1; /**< \brief \internal Reserved */
|
||||
unsigned int ISR:3; /**< \brief [26:24] Reference Input Signal Selection for Filter & Prescaler Cell k (rw) */
|
||||
unsigned int reserved_27:5; /**< \brief \internal Reserved */
|
||||
} Ifx_IOM_FPCCTR_Bits;
|
||||
|
||||
/** \brief IOM Filter and Prescaler Cells Rising & Falling Edge Status Register */
|
||||
typedef struct _Ifx_IOM_FPCESR_Bits
|
||||
{
|
||||
unsigned int FEG0:1; /**< \brief [0:0] Falling Edge Glitch Flag for FPC0 (rwh) */
|
||||
unsigned int FEG1:1; /**< \brief [1:1] Falling Edge Glitch Flag for FPC1 (rwh) */
|
||||
unsigned int FEG2:1; /**< \brief [2:2] Falling Edge Glitch Flag for FPC2 (rwh) */
|
||||
unsigned int FEG3:1; /**< \brief [3:3] Falling Edge Glitch Flag for FPC3 (rwh) */
|
||||
unsigned int FEG4:1; /**< \brief [4:4] Falling Edge Glitch Flag for FPC4 (rwh) */
|
||||
unsigned int FEG5:1; /**< \brief [5:5] Falling Edge Glitch Flag for FPC5 (rwh) */
|
||||
unsigned int FEG6:1; /**< \brief [6:6] Falling Edge Glitch Flag for FPC6 (rwh) */
|
||||
unsigned int FEG7:1; /**< \brief [7:7] Falling Edge Glitch Flag for FPC7 (rwh) */
|
||||
unsigned int FEG8:1; /**< \brief [8:8] Falling Edge Glitch Flag for FPC8 (rwh) */
|
||||
unsigned int FEG9:1; /**< \brief [9:9] Falling Edge Glitch Flag for FPC9 (rwh) */
|
||||
unsigned int FEG10:1; /**< \brief [10:10] Falling Edge Glitch Flag for FPC10 (rwh) */
|
||||
unsigned int FEG11:1; /**< \brief [11:11] Falling Edge Glitch Flag for FPC11 (rwh) */
|
||||
unsigned int FEG12:1; /**< \brief [12:12] Falling Edge Glitch Flag for FPC12 (rwh) */
|
||||
unsigned int FEG13:1; /**< \brief [13:13] Falling Edge Glitch Flag for FPC13 (rwh) */
|
||||
unsigned int FEG14:1; /**< \brief [14:14] Falling Edge Glitch Flag for FPC14 (rwh) */
|
||||
unsigned int FEG15:1; /**< \brief [15:15] Falling Edge Glitch Flag for FPC15 (rwh) */
|
||||
unsigned int REG0:1; /**< \brief [16:16] Rising Edge Glitch Flag for FPC0 (rwh) */
|
||||
unsigned int REG1:1; /**< \brief [17:17] Rising Edge Glitch Flag for FPC1 (rwh) */
|
||||
unsigned int REG2:1; /**< \brief [18:18] Rising Edge Glitch Flag for FPC2 (rwh) */
|
||||
unsigned int REG3:1; /**< \brief [19:19] Rising Edge Glitch Flag for FPC3 (rwh) */
|
||||
unsigned int REG4:1; /**< \brief [20:20] Rising Edge Glitch Flag for FPC4 (rwh) */
|
||||
unsigned int REG5:1; /**< \brief [21:21] Rising Edge Glitch Flag for FPC5 (rwh) */
|
||||
unsigned int REG6:1; /**< \brief [22:22] Rising Edge Glitch Flag for FPC6 (rwh) */
|
||||
unsigned int REG7:1; /**< \brief [23:23] Rising Edge Glitch Flag for FPC7 (rwh) */
|
||||
unsigned int REG8:1; /**< \brief [24:24] Rising Edge Glitch Flag for FPC8 (rwh) */
|
||||
unsigned int REG9:1; /**< \brief [25:25] Rising Edge Glitch Flag for FPC9 (rwh) */
|
||||
unsigned int REG10:1; /**< \brief [26:26] Rising Edge Glitch Flag for FPC10 (rwh) */
|
||||
unsigned int REG11:1; /**< \brief [27:27] Rising Edge Glitch Flag for FPC11 (rwh) */
|
||||
unsigned int REG12:1; /**< \brief [28:28] Rising Edge Glitch Flag for FPC12 (rwh) */
|
||||
unsigned int REG13:1; /**< \brief [29:29] Rising Edge Glitch Flag for FPC13 (rwh) */
|
||||
unsigned int REG14:1; /**< \brief [30:30] Rising Edge Glitch Flag for FPC14 (rwh) */
|
||||
unsigned int REG15:1; /**< \brief [31:31] Rising Edge Glitch Flag for FPC15 (rwh) */
|
||||
} Ifx_IOM_FPCESR_Bits;
|
||||
|
||||
/** \brief IOM Filter and Prescaler Cell Timer Register k */
|
||||
typedef struct _Ifx_IOM_FPCTIM_Bits
|
||||
{
|
||||
unsigned int TIM:16; /**< \brief [15:0] Timer Value of Filter and Prescaler Cell k (rwh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_IOM_FPCTIM_Bits;
|
||||
|
||||
/** \brief IOM GTM Input EXOR Combiner Selection Register */
|
||||
typedef struct _Ifx_IOM_GTMEXR_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] GTM input 0 selection for EXOR combiner (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] GTM input 1 selection for EXOR combiner (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] GTM input 2 selection for EXOR combiner (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] GTM input 3 selection for EXOR combiner (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] GTM input 4 selection for EXOR combiner (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] GTM input 5 selection for EXOR combiner (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] GTM input 6 selection for EXOR combiner (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] GTM input 7 selection for EXOR combiner (rw) */
|
||||
unsigned int reserved_8:24; /**< \brief \internal Reserved */
|
||||
} Ifx_IOM_GTMEXR_Bits;
|
||||
|
||||
/** \brief IOM Identification Register */
|
||||
typedef struct _Ifx_IOM_ID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Number Value (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_IOM_ID_Bits;
|
||||
|
||||
/** \brief IOM Kernel Reset Register 0 */
|
||||
typedef struct _Ifx_IOM_KRST0_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_IOM_KRST0_Bits;
|
||||
|
||||
/** \brief IOM Kernel Reset Register 1 */
|
||||
typedef struct _Ifx_IOM_KRST1_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_IOM_KRST1_Bits;
|
||||
|
||||
/** \brief IOM Kernel Reset Status Clear Register */
|
||||
typedef struct _Ifx_IOM_KRSTCLR_Bits
|
||||
{
|
||||
unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_IOM_KRSTCLR_Bits;
|
||||
|
||||
/** \brief IOM Logic Analyzer Module Configuration Register */
|
||||
typedef struct _Ifx_IOM_LAMCFG_Bits
|
||||
{
|
||||
unsigned int IVR:1; /**< \brief [0:0] Invert Reference LAM block m (rw) */
|
||||
unsigned int IVM:1; /**< \brief [1:1] Invert Monitor LAM block m (rw) */
|
||||
unsigned int MOS:1; /**< \brief [2:2] Monitor Source Select LAM block m (rw) */
|
||||
unsigned int RMS:1; /**< \brief [3:3] Runmode Select LAM block m (rw) */
|
||||
unsigned int EWS:1; /**< \brief [4:4] Event Window Select LAM block m (rw) */
|
||||
unsigned int reserved_5:3; /**< \brief \internal Reserved */
|
||||
unsigned int EDS:4; /**< \brief [11:8] Event Window Active Edge Selection LAM block m (rw) */
|
||||
unsigned int IVW:1; /**< \brief [12:12] Invert Event Window LAM block m (rw) */
|
||||
unsigned int reserved_13:3; /**< \brief \internal Reserved */
|
||||
unsigned int MCS:4; /**< \brief [19:16] Monitor Input Signal Selection LAM block m (rw) */
|
||||
unsigned int RCS:4; /**< \brief [23:20] Reference Input Signal Selection LAM block m (rw) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_IOM_LAMCFG_Bits;
|
||||
|
||||
/** \brief IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
typedef struct _Ifx_IOM_LAMEWC_Bits
|
||||
{
|
||||
unsigned int CNT:24; /**< \brief [23:0] Event Window Count Value LAM block m (r) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_IOM_LAMEWC_Bits;
|
||||
|
||||
/** \brief IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
typedef struct _Ifx_IOM_LAMEWS_Bits
|
||||
{
|
||||
unsigned int THR:24; /**< \brief [23:0] Event Window Count Threshold (rw) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_IOM_LAMEWS_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Iom_union
|
||||
* \{ */
|
||||
|
||||
/** \brief IOM Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_ACCEN0;
|
||||
|
||||
/** \brief IOM Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_ACCEN1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_ACCEN1;
|
||||
|
||||
/** \brief IOM Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_CLC;
|
||||
|
||||
/** \brief IOM Event Combiner Module Counter Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_ECMCCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_ECMCCFG;
|
||||
|
||||
/** \brief IOM Event Combiner Module Event Trigger History Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_ECMETH0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_ECMETH0;
|
||||
|
||||
/** \brief IOM Event Combiner Module Event Trigger History Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_ECMETH1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_ECMETH1;
|
||||
|
||||
/** \brief IOM Event Combiner Module Global Event Selection Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_ECMSELR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_ECMSELR;
|
||||
|
||||
/** \brief IOM Filter and Prescaler Cell Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_FPCCTR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_FPCCTR;
|
||||
|
||||
/** \brief IOM Filter and Prescaler Cells Rising & Falling Edge Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_FPCESR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_FPCESR;
|
||||
|
||||
/** \brief IOM Filter and Prescaler Cell Timer Register k */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_FPCTIM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_FPCTIM;
|
||||
|
||||
/** \brief IOM GTM Input EXOR Combiner Selection Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_GTMEXR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_GTMEXR;
|
||||
|
||||
/** \brief IOM Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_ID;
|
||||
|
||||
/** \brief IOM Kernel Reset Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_KRST0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_KRST0;
|
||||
|
||||
/** \brief IOM Kernel Reset Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_KRST1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_KRST1;
|
||||
|
||||
/** \brief IOM Kernel Reset Status Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_KRSTCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_KRSTCLR;
|
||||
|
||||
/** \brief IOM Logic Analyzer Module Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_LAMCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_LAMCFG;
|
||||
|
||||
/** \brief IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_LAMEWC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_LAMEWC;
|
||||
|
||||
/** \brief IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_IOM_LAMEWS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_IOM_LAMEWS;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Iom_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief IOM object */
|
||||
typedef volatile struct _Ifx_IOM
|
||||
{
|
||||
Ifx_IOM_CLC CLC; /**< \brief 0, IOM Clock Control Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_IOM_ID ID; /**< \brief 8, IOM Identification Register */
|
||||
unsigned char reserved_C[16]; /**< \brief C, \internal Reserved */
|
||||
Ifx_IOM_KRSTCLR KRSTCLR; /**< \brief 1C, IOM Kernel Reset Status Clear Register */
|
||||
Ifx_IOM_KRST1 KRST1; /**< \brief 20, IOM Kernel Reset Register 1 */
|
||||
Ifx_IOM_KRST0 KRST0; /**< \brief 24, IOM Kernel Reset Register 0 */
|
||||
Ifx_IOM_ACCEN1 ACCEN1; /**< \brief 28, IOM Access Enable Register 1 */
|
||||
Ifx_IOM_ACCEN0 ACCEN0; /**< \brief 2C, IOM Access Enable Register 0 */
|
||||
Ifx_IOM_ECMCCFG ECMCCFG; /**< \brief 30, IOM Event Combiner Module Counter Configuration Register */
|
||||
Ifx_IOM_ECMSELR ECMSELR; /**< \brief 34, IOM Event Combiner Module Global Event Selection Register */
|
||||
Ifx_IOM_ECMETH0 ECMETH0; /**< \brief 38, IOM Event Combiner Module Event Trigger History Register 0 */
|
||||
Ifx_IOM_ECMETH1 ECMETH1; /**< \brief 3C, IOM Event Combiner Module Event Trigger History Register 1 */
|
||||
Ifx_IOM_GTMEXR GTMEXR; /**< \brief 40, IOM GTM Input EXOR Combiner Selection Register */
|
||||
unsigned char reserved_44[52]; /**< \brief 44, \internal Reserved */
|
||||
Ifx_IOM_FPCESR FPCESR; /**< \brief 78, IOM Filter and Prescaler Cells Rising & Falling Edge Status Register */
|
||||
unsigned char reserved_7C[4]; /**< \brief 7C, \internal Reserved */
|
||||
Ifx_IOM_FPCCTR FPCCTR[16]; /**< \brief 80, IOM Filter and Prescaler Cell Control Register */
|
||||
Ifx_IOM_FPCTIM FPCTIM[16]; /**< \brief C0, IOM Filter and Prescaler Cell Timer Register k */
|
||||
Ifx_IOM_LAMEWC LAMEWC[16]; /**< \brief 100, IOM Logic Analyzer Module Event Window Count Status Register */
|
||||
unsigned char reserved_140[64]; /**< \brief 140, \internal Reserved */
|
||||
Ifx_IOM_LAMCFG LAMCFG[16]; /**< \brief 180, IOM Logic Analyzer Module Configuration Register */
|
||||
Ifx_IOM_LAMEWS LAMEWS[16]; /**< \brief 1C0, IOM Logic Analyzer Module Event Window Configuration Register */
|
||||
} Ifx_IOM;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXIOM_REGDEF_H */
|
||||
@@ -1,477 +0,0 @@
|
||||
/**
|
||||
* \file IfxLmu_bf.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Lmu_BitfieldsMask Bitfields mask and offset
|
||||
* \ingroup IfxLld_Lmu
|
||||
*
|
||||
*/
|
||||
#ifndef IFXLMU_BF_H
|
||||
#define IFXLMU_BF_H 1
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Lmu_BitfieldsMask
|
||||
* \{ */
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN0 */
|
||||
#define IFX_LMU_ACCEN0_EN0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN0 */
|
||||
#define IFX_LMU_ACCEN0_EN0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN0 */
|
||||
#define IFX_LMU_ACCEN0_EN0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN10 */
|
||||
#define IFX_LMU_ACCEN0_EN10_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN10 */
|
||||
#define IFX_LMU_ACCEN0_EN10_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN10 */
|
||||
#define IFX_LMU_ACCEN0_EN10_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN11 */
|
||||
#define IFX_LMU_ACCEN0_EN11_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN11 */
|
||||
#define IFX_LMU_ACCEN0_EN11_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN11 */
|
||||
#define IFX_LMU_ACCEN0_EN11_OFF (11u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN12 */
|
||||
#define IFX_LMU_ACCEN0_EN12_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN12 */
|
||||
#define IFX_LMU_ACCEN0_EN12_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN12 */
|
||||
#define IFX_LMU_ACCEN0_EN12_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN13 */
|
||||
#define IFX_LMU_ACCEN0_EN13_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN13 */
|
||||
#define IFX_LMU_ACCEN0_EN13_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN13 */
|
||||
#define IFX_LMU_ACCEN0_EN13_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN14 */
|
||||
#define IFX_LMU_ACCEN0_EN14_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN14 */
|
||||
#define IFX_LMU_ACCEN0_EN14_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN14 */
|
||||
#define IFX_LMU_ACCEN0_EN14_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN15 */
|
||||
#define IFX_LMU_ACCEN0_EN15_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN15 */
|
||||
#define IFX_LMU_ACCEN0_EN15_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN15 */
|
||||
#define IFX_LMU_ACCEN0_EN15_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN16 */
|
||||
#define IFX_LMU_ACCEN0_EN16_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN16 */
|
||||
#define IFX_LMU_ACCEN0_EN16_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN16 */
|
||||
#define IFX_LMU_ACCEN0_EN16_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN17 */
|
||||
#define IFX_LMU_ACCEN0_EN17_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN17 */
|
||||
#define IFX_LMU_ACCEN0_EN17_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN17 */
|
||||
#define IFX_LMU_ACCEN0_EN17_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN18 */
|
||||
#define IFX_LMU_ACCEN0_EN18_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN18 */
|
||||
#define IFX_LMU_ACCEN0_EN18_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN18 */
|
||||
#define IFX_LMU_ACCEN0_EN18_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN19 */
|
||||
#define IFX_LMU_ACCEN0_EN19_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN19 */
|
||||
#define IFX_LMU_ACCEN0_EN19_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN19 */
|
||||
#define IFX_LMU_ACCEN0_EN19_OFF (19u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN1 */
|
||||
#define IFX_LMU_ACCEN0_EN1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN1 */
|
||||
#define IFX_LMU_ACCEN0_EN1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN1 */
|
||||
#define IFX_LMU_ACCEN0_EN1_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN20 */
|
||||
#define IFX_LMU_ACCEN0_EN20_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN20 */
|
||||
#define IFX_LMU_ACCEN0_EN20_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN20 */
|
||||
#define IFX_LMU_ACCEN0_EN20_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN21 */
|
||||
#define IFX_LMU_ACCEN0_EN21_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN21 */
|
||||
#define IFX_LMU_ACCEN0_EN21_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN21 */
|
||||
#define IFX_LMU_ACCEN0_EN21_OFF (21u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN22 */
|
||||
#define IFX_LMU_ACCEN0_EN22_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN22 */
|
||||
#define IFX_LMU_ACCEN0_EN22_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN22 */
|
||||
#define IFX_LMU_ACCEN0_EN22_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN23 */
|
||||
#define IFX_LMU_ACCEN0_EN23_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN23 */
|
||||
#define IFX_LMU_ACCEN0_EN23_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN23 */
|
||||
#define IFX_LMU_ACCEN0_EN23_OFF (23u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN24 */
|
||||
#define IFX_LMU_ACCEN0_EN24_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN24 */
|
||||
#define IFX_LMU_ACCEN0_EN24_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN24 */
|
||||
#define IFX_LMU_ACCEN0_EN24_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN25 */
|
||||
#define IFX_LMU_ACCEN0_EN25_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN25 */
|
||||
#define IFX_LMU_ACCEN0_EN25_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN25 */
|
||||
#define IFX_LMU_ACCEN0_EN25_OFF (25u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN26 */
|
||||
#define IFX_LMU_ACCEN0_EN26_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN26 */
|
||||
#define IFX_LMU_ACCEN0_EN26_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN26 */
|
||||
#define IFX_LMU_ACCEN0_EN26_OFF (26u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN27 */
|
||||
#define IFX_LMU_ACCEN0_EN27_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN27 */
|
||||
#define IFX_LMU_ACCEN0_EN27_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN27 */
|
||||
#define IFX_LMU_ACCEN0_EN27_OFF (27u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN28 */
|
||||
#define IFX_LMU_ACCEN0_EN28_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN28 */
|
||||
#define IFX_LMU_ACCEN0_EN28_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN28 */
|
||||
#define IFX_LMU_ACCEN0_EN28_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN29 */
|
||||
#define IFX_LMU_ACCEN0_EN29_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN29 */
|
||||
#define IFX_LMU_ACCEN0_EN29_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN29 */
|
||||
#define IFX_LMU_ACCEN0_EN29_OFF (29u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN2 */
|
||||
#define IFX_LMU_ACCEN0_EN2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN2 */
|
||||
#define IFX_LMU_ACCEN0_EN2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN2 */
|
||||
#define IFX_LMU_ACCEN0_EN2_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN30 */
|
||||
#define IFX_LMU_ACCEN0_EN30_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN30 */
|
||||
#define IFX_LMU_ACCEN0_EN30_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN30 */
|
||||
#define IFX_LMU_ACCEN0_EN30_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN31 */
|
||||
#define IFX_LMU_ACCEN0_EN31_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN31 */
|
||||
#define IFX_LMU_ACCEN0_EN31_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN31 */
|
||||
#define IFX_LMU_ACCEN0_EN31_OFF (31u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN3 */
|
||||
#define IFX_LMU_ACCEN0_EN3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN3 */
|
||||
#define IFX_LMU_ACCEN0_EN3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN3 */
|
||||
#define IFX_LMU_ACCEN0_EN3_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN4 */
|
||||
#define IFX_LMU_ACCEN0_EN4_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN4 */
|
||||
#define IFX_LMU_ACCEN0_EN4_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN4 */
|
||||
#define IFX_LMU_ACCEN0_EN4_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN5 */
|
||||
#define IFX_LMU_ACCEN0_EN5_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN5 */
|
||||
#define IFX_LMU_ACCEN0_EN5_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN5 */
|
||||
#define IFX_LMU_ACCEN0_EN5_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN6 */
|
||||
#define IFX_LMU_ACCEN0_EN6_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN6 */
|
||||
#define IFX_LMU_ACCEN0_EN6_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN6 */
|
||||
#define IFX_LMU_ACCEN0_EN6_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN7 */
|
||||
#define IFX_LMU_ACCEN0_EN7_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN7 */
|
||||
#define IFX_LMU_ACCEN0_EN7_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN7 */
|
||||
#define IFX_LMU_ACCEN0_EN7_OFF (7u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN8 */
|
||||
#define IFX_LMU_ACCEN0_EN8_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN8 */
|
||||
#define IFX_LMU_ACCEN0_EN8_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN8 */
|
||||
#define IFX_LMU_ACCEN0_EN8_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_ACCEN0_Bits.EN9 */
|
||||
#define IFX_LMU_ACCEN0_EN9_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_ACCEN0_Bits.EN9 */
|
||||
#define IFX_LMU_ACCEN0_EN9_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_ACCEN0_Bits.EN9 */
|
||||
#define IFX_LMU_ACCEN0_EN9_OFF (9u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_BUFCON_Bits.EN1 */
|
||||
#define IFX_LMU_BUFCON_EN1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_BUFCON_Bits.EN1 */
|
||||
#define IFX_LMU_BUFCON_EN1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_BUFCON_Bits.EN1 */
|
||||
#define IFX_LMU_BUFCON_EN1_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_BUFCON_Bits.EN2 */
|
||||
#define IFX_LMU_BUFCON_EN2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_BUFCON_Bits.EN2 */
|
||||
#define IFX_LMU_BUFCON_EN2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_BUFCON_Bits.EN2 */
|
||||
#define IFX_LMU_BUFCON_EN2_OFF (31u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_BUFCON_Bits.EPEN */
|
||||
#define IFX_LMU_BUFCON_EPEN_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_BUFCON_Bits.EPEN */
|
||||
#define IFX_LMU_BUFCON_EPEN_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_BUFCON_Bits.EPEN */
|
||||
#define IFX_LMU_BUFCON_EPEN_OFF (23u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_BUFCON_Bits.EREN */
|
||||
#define IFX_LMU_BUFCON_EREN_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_BUFCON_Bits.EREN */
|
||||
#define IFX_LMU_BUFCON_EREN_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_BUFCON_Bits.EREN */
|
||||
#define IFX_LMU_BUFCON_EREN_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_BUFCON_Bits.TAG1 */
|
||||
#define IFX_LMU_BUFCON_TAG1_LEN (6u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_BUFCON_Bits.TAG1 */
|
||||
#define IFX_LMU_BUFCON_TAG1_MSK (0x3fu)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_BUFCON_Bits.TAG1 */
|
||||
#define IFX_LMU_BUFCON_TAG1_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_BUFCON_Bits.TAG2 */
|
||||
#define IFX_LMU_BUFCON_TAG2_LEN (6u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_BUFCON_Bits.TAG2 */
|
||||
#define IFX_LMU_BUFCON_TAG2_MSK (0x3fu)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_BUFCON_Bits.TAG2 */
|
||||
#define IFX_LMU_BUFCON_TAG2_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_CLC_Bits.DISR */
|
||||
#define IFX_LMU_CLC_DISR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_CLC_Bits.DISR */
|
||||
#define IFX_LMU_CLC_DISR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_CLC_Bits.DISR */
|
||||
#define IFX_LMU_CLC_DISR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_CLC_Bits.DISS */
|
||||
#define IFX_LMU_CLC_DISS_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_CLC_Bits.DISS */
|
||||
#define IFX_LMU_CLC_DISS_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_CLC_Bits.DISS */
|
||||
#define IFX_LMU_CLC_DISS_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_MEMCON_Bits.ADDERR */
|
||||
#define IFX_LMU_MEMCON_ADDERR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_MEMCON_Bits.ADDERR */
|
||||
#define IFX_LMU_MEMCON_ADDERR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_MEMCON_Bits.ADDERR */
|
||||
#define IFX_LMU_MEMCON_ADDERR_OFF (7u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_MEMCON_Bits.DATAERR */
|
||||
#define IFX_LMU_MEMCON_DATAERR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_MEMCON_Bits.DATAERR */
|
||||
#define IFX_LMU_MEMCON_DATAERR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_MEMCON_Bits.DATAERR */
|
||||
#define IFX_LMU_MEMCON_DATAERR_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_MEMCON_Bits.ERERR */
|
||||
#define IFX_LMU_MEMCON_ERERR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_MEMCON_Bits.ERERR */
|
||||
#define IFX_LMU_MEMCON_ERERR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_MEMCON_Bits.ERERR */
|
||||
#define IFX_LMU_MEMCON_ERERR_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_MEMCON_Bits.EWERR */
|
||||
#define IFX_LMU_MEMCON_EWERR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_MEMCON_Bits.EWERR */
|
||||
#define IFX_LMU_MEMCON_EWERR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_MEMCON_Bits.EWERR */
|
||||
#define IFX_LMU_MEMCON_EWERR_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_MEMCON_Bits.FFTPFT */
|
||||
#define IFX_LMU_MEMCON_FFTPFT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_MEMCON_Bits.FFTPFT */
|
||||
#define IFX_LMU_MEMCON_FFTPFT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_MEMCON_Bits.FFTPFT */
|
||||
#define IFX_LMU_MEMCON_FFTPFT_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_MEMCON_Bits.OLDAEN */
|
||||
#define IFX_LMU_MEMCON_OLDAEN_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_MEMCON_Bits.OLDAEN */
|
||||
#define IFX_LMU_MEMCON_OLDAEN_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_MEMCON_Bits.OLDAEN */
|
||||
#define IFX_LMU_MEMCON_OLDAEN_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_MEMCON_Bits.POLDAEN */
|
||||
#define IFX_LMU_MEMCON_POLDAEN_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_MEMCON_Bits.POLDAEN */
|
||||
#define IFX_LMU_MEMCON_POLDAEN_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_MEMCON_Bits.POLDAEN */
|
||||
#define IFX_LMU_MEMCON_POLDAEN_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_MEMCON_Bits.WSTATES */
|
||||
#define IFX_LMU_MEMCON_WSTATES_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_MEMCON_Bits.WSTATES */
|
||||
#define IFX_LMU_MEMCON_WSTATES_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_MEMCON_Bits.WSTATES */
|
||||
#define IFX_LMU_MEMCON_WSTATES_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_LMU_MODID_Bits.ID_VALUE */
|
||||
#define IFX_LMU_MODID_ID_VALUE_LEN (32u)
|
||||
|
||||
/** \brief Mask for Ifx_LMU_MODID_Bits.ID_VALUE */
|
||||
#define IFX_LMU_MODID_ID_VALUE_MSK (0xffffffffu)
|
||||
|
||||
/** \brief Offset for Ifx_LMU_MODID_Bits.ID_VALUE */
|
||||
#define IFX_LMU_MODID_ID_VALUE_OFF (0u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXLMU_BF_H */
|
||||
@@ -1,75 +0,0 @@
|
||||
/**
|
||||
* \file IfxLmu_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Lmu_Cfg Lmu address
|
||||
* \ingroup IfxLld_Lmu
|
||||
*
|
||||
* \defgroup IfxLld_Lmu_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Lmu_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Lmu_Cfg_Lmu 2-LMU
|
||||
* \ingroup IfxLld_Lmu_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXLMU_REG_H
|
||||
#define IFXLMU_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxLmu_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Lmu_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief LMU object */
|
||||
#define MODULE_LMU /*lint --e(923)*/ (*(Ifx_LMU*)0xF8700800u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Lmu_Cfg_Lmu
|
||||
* \{ */
|
||||
|
||||
/** \brief 10, LMU Access Enable Register 0 */
|
||||
#define LMU_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_LMU_ACCEN0*)0xF8700810u)
|
||||
|
||||
/** \brief 14, LMU Access Enable Register 1 */
|
||||
#define LMU_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_LMU_ACCEN1*)0xF8700814u)
|
||||
|
||||
/** \brief 30, LMU Buffer Control Register */
|
||||
#define LMU_BUFCON0 /*lint --e(923)*/ (*(volatile Ifx_LMU_BUFCON*)0xF8700830u)
|
||||
|
||||
/** \brief 34, LMU Buffer Control Register */
|
||||
#define LMU_BUFCON1 /*lint --e(923)*/ (*(volatile Ifx_LMU_BUFCON*)0xF8700834u)
|
||||
|
||||
/** \brief 38, LMU Buffer Control Register */
|
||||
#define LMU_BUFCON2 /*lint --e(923)*/ (*(volatile Ifx_LMU_BUFCON*)0xF8700838u)
|
||||
|
||||
/** \brief 0, LMU Clock Control Register */
|
||||
#define LMU_CLC /*lint --e(923)*/ (*(volatile Ifx_LMU_CLC*)0xF8700800u)
|
||||
|
||||
/** \brief 20, LMU Memory Control Register */
|
||||
#define LMU_MEMCON /*lint --e(923)*/ (*(volatile Ifx_LMU_MEMCON*)0xF8700820u)
|
||||
|
||||
/** \brief 8, LMU Module ID Register */
|
||||
#define LMU_MODID /*lint --e(923)*/ (*(volatile Ifx_LMU_MODID*)0xF8700808u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXLMU_REG_H */
|
||||
@@ -1,214 +0,0 @@
|
||||
/**
|
||||
* \file IfxLmu_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Lmu Lmu
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Lmu_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Lmu
|
||||
*
|
||||
* \defgroup IfxLld_Lmu_union Union
|
||||
* \ingroup IfxLld_Lmu
|
||||
*
|
||||
* \defgroup IfxLld_Lmu_struct Struct
|
||||
* \ingroup IfxLld_Lmu
|
||||
*
|
||||
*/
|
||||
#ifndef IFXLMU_REGDEF_H
|
||||
#define IFXLMU_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Lmu_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief LMU Access Enable Register 0 */
|
||||
typedef struct _Ifx_LMU_ACCEN0_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
Ifx_Strict_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
Ifx_Strict_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
Ifx_Strict_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
Ifx_Strict_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
Ifx_Strict_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
Ifx_Strict_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
Ifx_Strict_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
Ifx_Strict_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
Ifx_Strict_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
Ifx_Strict_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
Ifx_Strict_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
Ifx_Strict_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
Ifx_Strict_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
Ifx_Strict_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
Ifx_Strict_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
Ifx_Strict_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
Ifx_Strict_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
Ifx_Strict_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
Ifx_Strict_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
Ifx_Strict_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
Ifx_Strict_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
Ifx_Strict_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
Ifx_Strict_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
Ifx_Strict_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
Ifx_Strict_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
Ifx_Strict_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
Ifx_Strict_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
Ifx_Strict_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
Ifx_Strict_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
Ifx_Strict_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
Ifx_Strict_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_LMU_ACCEN0_Bits;
|
||||
|
||||
/** \brief LMU Access Enable Register 1 */
|
||||
typedef struct _Ifx_LMU_ACCEN1_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_LMU_ACCEN1_Bits;
|
||||
|
||||
/** \brief LMU Buffer Control Register */
|
||||
typedef struct _Ifx_LMU_BUFCON_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit TAG1:6; /**< \brief [5:0] Master Tag ID 1 (rw) */
|
||||
Ifx_Strict_32Bit reserved_6:2; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit TAG2:6; /**< \brief [13:8] Master Tag ID 2 (rw) */
|
||||
Ifx_Strict_32Bit reserved_14:8; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit EREN:1; /**< \brief [22:22] EMEM Read Buffer Enable (rw) */
|
||||
Ifx_Strict_32Bit EPEN:1; /**< \brief [23:23] EMEM Prefetch Enable (rw) */
|
||||
Ifx_Strict_32Bit reserved_24:6; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit EN1:1; /**< \brief [30:30] TAG1 Field Enable (rw) */
|
||||
Ifx_Strict_32Bit EN2:1; /**< \brief [31:31] TAG2 Field Enable (rw) */
|
||||
} Ifx_LMU_BUFCON_Bits;
|
||||
|
||||
/** \brief LMU Clock Control Register */
|
||||
typedef struct _Ifx_LMU_CLC_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit DISR:1; /**< \brief [0:0] Module LMU Disable Request Bit (rw) */
|
||||
Ifx_Strict_32Bit DISS:1; /**< \brief [1:1] Module LMU Disable Status Bit (rh) */
|
||||
Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_LMU_CLC_Bits;
|
||||
|
||||
/** \brief LMU Memory Control Register */
|
||||
typedef struct _Ifx_LMU_MEMCON_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit OLDAEN:1; /**< \brief [0:0] Online Data Acquisition Enabled (rw) */
|
||||
Ifx_Strict_32Bit POLDAEN:1; /**< \brief [1:1] Protection Bit for OLDAEN (w) */
|
||||
Ifx_Strict_32Bit reserved_2:1; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit ERERR:1; /**< \brief [3:3] EMEM Read Error (rwh) */
|
||||
Ifx_Strict_32Bit reserved_4:1; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit EWERR:1; /**< \brief [5:5] EMEM Write Error (rwh) */
|
||||
Ifx_Strict_32Bit DATAERR:1; /**< \brief [6:6] SRI Data Phase ECC Error (rwh) */
|
||||
Ifx_Strict_32Bit ADDERR:1; /**< \brief [7:7] SRI Address Phase ECC Error (rwh) */
|
||||
Ifx_Strict_32Bit reserved_8:2; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit FFTPFT:1; /**< \brief [10:10] FFT Accelerator Prefetch Disable (rw) */
|
||||
Ifx_Strict_32Bit reserved_11:1; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit WSTATES:4; /**< \brief [15:12] EMEM Wait States (rw) */
|
||||
Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_LMU_MEMCON_Bits;
|
||||
|
||||
/** \brief LMU Module ID Register */
|
||||
typedef struct _Ifx_LMU_MODID_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit ID_VALUE:32; /**< \brief [31:0] Module Identification Value (r) */
|
||||
} Ifx_LMU_MODID_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Lmu_union
|
||||
* \{ */
|
||||
|
||||
/** \brief LMU Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_LMU_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_LMU_ACCEN0;
|
||||
|
||||
/** \brief LMU Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_LMU_ACCEN1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_LMU_ACCEN1;
|
||||
|
||||
/** \brief LMU Buffer Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_LMU_BUFCON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_LMU_BUFCON;
|
||||
|
||||
/** \brief LMU Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_LMU_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_LMU_CLC;
|
||||
|
||||
/** \brief LMU Memory Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_LMU_MEMCON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_LMU_MEMCON;
|
||||
|
||||
/** \brief LMU Module ID Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_LMU_MODID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_LMU_MODID;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Lmu_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief LMU object */
|
||||
typedef volatile struct _Ifx_LMU
|
||||
{
|
||||
Ifx_LMU_CLC CLC; /**< \brief 0, LMU Clock Control Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_LMU_MODID MODID; /**< \brief 8, LMU Module ID Register */
|
||||
unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
|
||||
Ifx_LMU_ACCEN0 ACCEN0; /**< \brief 10, LMU Access Enable Register 0 */
|
||||
Ifx_LMU_ACCEN1 ACCEN1; /**< \brief 14, LMU Access Enable Register 1 */
|
||||
unsigned char reserved_18[8]; /**< \brief 18, \internal Reserved */
|
||||
Ifx_LMU_MEMCON MEMCON; /**< \brief 20, LMU Memory Control Register */
|
||||
unsigned char reserved_24[12]; /**< \brief 24, \internal Reserved */
|
||||
Ifx_LMU_BUFCON BUFCON[3]; /**< \brief 30, LMU Buffer Control Register */
|
||||
unsigned char reserved_3C[196]; /**< \brief 3C, \internal Reserved */
|
||||
} Ifx_LMU;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXLMU_REGDEF_H */
|
||||
@@ -1,450 +0,0 @@
|
||||
/**
|
||||
* \file IfxMc_bf.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Mc_BitfieldsMask Bitfields mask and offset
|
||||
* \ingroup IfxLld_Mc
|
||||
*
|
||||
*/
|
||||
#ifndef IFXMC_BF_H
|
||||
#define IFXMC_BF_H 1
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Mc_BitfieldsMask
|
||||
* \{ */
|
||||
|
||||
/** \brief Length for Ifx_MC_CONFIG0_Bits.ACCSTYPE */
|
||||
#define IFX_MC_CONFIG0_ACCSTYPE_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_CONFIG0_Bits.ACCSTYPE */
|
||||
#define IFX_MC_CONFIG0_ACCSTYPE_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_MC_CONFIG0_Bits.ACCSTYPE */
|
||||
#define IFX_MC_CONFIG0_ACCSTYPE_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_MC_CONFIG0_Bits.NUMACCS */
|
||||
#define IFX_MC_CONFIG0_NUMACCS_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_CONFIG0_Bits.NUMACCS */
|
||||
#define IFX_MC_CONFIG0_NUMACCS_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_MC_CONFIG0_Bits.NUMACCS */
|
||||
#define IFX_MC_CONFIG0_NUMACCS_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_MC_CONFIG1_Bits.ACCSPAT */
|
||||
#define IFX_MC_CONFIG1_ACCSPAT_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_CONFIG1_Bits.ACCSPAT */
|
||||
#define IFX_MC_CONFIG1_ACCSPAT_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_MC_CONFIG1_Bits.ACCSPAT */
|
||||
#define IFX_MC_CONFIG1_ACCSPAT_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_MC_CONFIG1_Bits.AG_MOD */
|
||||
#define IFX_MC_CONFIG1_AG_MOD_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_CONFIG1_Bits.AG_MOD */
|
||||
#define IFX_MC_CONFIG1_AG_MOD_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_MC_CONFIG1_Bits.AG_MOD */
|
||||
#define IFX_MC_CONFIG1_AG_MOD_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_MC_CONFIG1_Bits.SELFASTB */
|
||||
#define IFX_MC_CONFIG1_SELFASTB_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_CONFIG1_Bits.SELFASTB */
|
||||
#define IFX_MC_CONFIG1_SELFASTB_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_MC_CONFIG1_Bits.SELFASTB */
|
||||
#define IFX_MC_CONFIG1_SELFASTB_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCD_Bits.AENE */
|
||||
#define IFX_MC_ECCD_AENE_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCD_Bits.AENE */
|
||||
#define IFX_MC_ECCD_AENE_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCD_Bits.AENE */
|
||||
#define IFX_MC_ECCD_AENE_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCD_Bits.AERR */
|
||||
#define IFX_MC_ECCD_AERR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCD_Bits.AERR */
|
||||
#define IFX_MC_ECCD_AERR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCD_Bits.AERR */
|
||||
#define IFX_MC_ECCD_AERR_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCD_Bits.CENE */
|
||||
#define IFX_MC_ECCD_CENE_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCD_Bits.CENE */
|
||||
#define IFX_MC_ECCD_CENE_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCD_Bits.CENE */
|
||||
#define IFX_MC_ECCD_CENE_OFF (11u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCD_Bits.CERR */
|
||||
#define IFX_MC_ECCD_CERR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCD_Bits.CERR */
|
||||
#define IFX_MC_ECCD_CERR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCD_Bits.CERR */
|
||||
#define IFX_MC_ECCD_CERR_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCD_Bits.ECE */
|
||||
#define IFX_MC_ECCD_ECE_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCD_Bits.ECE */
|
||||
#define IFX_MC_ECCD_ECE_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCD_Bits.ECE */
|
||||
#define IFX_MC_ECCD_ECE_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCD_Bits.EOV */
|
||||
#define IFX_MC_ECCD_EOV_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCD_Bits.EOV */
|
||||
#define IFX_MC_ECCD_EOV_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCD_Bits.EOV */
|
||||
#define IFX_MC_ECCD_EOV_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCD_Bits.RARVAL */
|
||||
#define IFX_MC_ECCD_RARVAL_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCD_Bits.RARVAL */
|
||||
#define IFX_MC_ECCD_RARVAL_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCD_Bits.RARVAL */
|
||||
#define IFX_MC_ECCD_RARVAL_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCD_Bits.SERR */
|
||||
#define IFX_MC_ECCD_SERR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCD_Bits.SERR */
|
||||
#define IFX_MC_ECCD_SERR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCD_Bits.SERR */
|
||||
#define IFX_MC_ECCD_SERR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCD_Bits.TRC */
|
||||
#define IFX_MC_ECCD_TRC_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCD_Bits.TRC */
|
||||
#define IFX_MC_ECCD_TRC_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCD_Bits.TRC */
|
||||
#define IFX_MC_ECCD_TRC_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCD_Bits.UENE */
|
||||
#define IFX_MC_ECCD_UENE_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCD_Bits.UENE */
|
||||
#define IFX_MC_ECCD_UENE_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCD_Bits.UENE */
|
||||
#define IFX_MC_ECCD_UENE_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCD_Bits.UERR */
|
||||
#define IFX_MC_ECCD_UERR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCD_Bits.UERR */
|
||||
#define IFX_MC_ECCD_UERR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCD_Bits.UERR */
|
||||
#define IFX_MC_ECCD_UERR_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCD_Bits.VAL */
|
||||
#define IFX_MC_ECCD_VAL_LEN (5u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCD_Bits.VAL */
|
||||
#define IFX_MC_ECCD_VAL_MSK (0x1fu)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCD_Bits.VAL */
|
||||
#define IFX_MC_ECCD_VAL_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCS_Bits.AENE */
|
||||
#define IFX_MC_ECCS_AENE_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCS_Bits.AENE */
|
||||
#define IFX_MC_ECCS_AENE_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCS_Bits.AENE */
|
||||
#define IFX_MC_ECCS_AENE_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCS_Bits.BFLE */
|
||||
#define IFX_MC_ECCS_BFLE_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCS_Bits.BFLE */
|
||||
#define IFX_MC_ECCS_BFLE_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCS_Bits.BFLE */
|
||||
#define IFX_MC_ECCS_BFLE_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCS_Bits.CENE */
|
||||
#define IFX_MC_ECCS_CENE_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCS_Bits.CENE */
|
||||
#define IFX_MC_ECCS_CENE_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCS_Bits.CENE */
|
||||
#define IFX_MC_ECCS_CENE_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCS_Bits.ECCMAP */
|
||||
#define IFX_MC_ECCS_ECCMAP_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCS_Bits.ECCMAP */
|
||||
#define IFX_MC_ECCS_ECCMAP_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCS_Bits.ECCMAP */
|
||||
#define IFX_MC_ECCS_ECCMAP_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCS_Bits.ECE */
|
||||
#define IFX_MC_ECCS_ECE_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCS_Bits.ECE */
|
||||
#define IFX_MC_ECCS_ECE_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCS_Bits.ECE */
|
||||
#define IFX_MC_ECCS_ECE_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCS_Bits.SFLE */
|
||||
#define IFX_MC_ECCS_SFLE_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCS_Bits.SFLE */
|
||||
#define IFX_MC_ECCS_SFLE_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCS_Bits.SFLE */
|
||||
#define IFX_MC_ECCS_SFLE_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCS_Bits.TC_WAY_SEL */
|
||||
#define IFX_MC_ECCS_TC_WAY_SEL_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCS_Bits.TC_WAY_SEL */
|
||||
#define IFX_MC_ECCS_TC_WAY_SEL_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCS_Bits.TC_WAY_SEL */
|
||||
#define IFX_MC_ECCS_TC_WAY_SEL_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCS_Bits.TRE */
|
||||
#define IFX_MC_ECCS_TRE_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCS_Bits.TRE */
|
||||
#define IFX_MC_ECCS_TRE_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCS_Bits.TRE */
|
||||
#define IFX_MC_ECCS_TRE_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ECCS_Bits.UENE */
|
||||
#define IFX_MC_ECCS_UENE_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ECCS_Bits.UENE */
|
||||
#define IFX_MC_ECCS_UENE_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ECCS_Bits.UENE */
|
||||
#define IFX_MC_ECCS_UENE_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ETRR_Bits.ADDR */
|
||||
#define IFX_MC_ETRR_ADDR_LEN (13u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ETRR_Bits.ADDR */
|
||||
#define IFX_MC_ETRR_ADDR_MSK (0x1fffu)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ETRR_Bits.ADDR */
|
||||
#define IFX_MC_ETRR_ADDR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_MC_ETRR_Bits.MBI */
|
||||
#define IFX_MC_ETRR_MBI_LEN (3u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_ETRR_Bits.MBI */
|
||||
#define IFX_MC_ETRR_MBI_MSK (0x7u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_ETRR_Bits.MBI */
|
||||
#define IFX_MC_ETRR_MBI_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_MC_MCONTROL_Bits.BITTOG */
|
||||
#define IFX_MC_MCONTROL_BITTOG_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_MCONTROL_Bits.BITTOG */
|
||||
#define IFX_MC_MCONTROL_BITTOG_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_MCONTROL_Bits.BITTOG */
|
||||
#define IFX_MC_MCONTROL_BITTOG_OFF (7u)
|
||||
|
||||
/** \brief Length for Ifx_MC_MCONTROL_Bits.DINIT */
|
||||
#define IFX_MC_MCONTROL_DINIT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_MCONTROL_Bits.DINIT */
|
||||
#define IFX_MC_MCONTROL_DINIT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_MCONTROL_Bits.DINIT */
|
||||
#define IFX_MC_MCONTROL_DINIT_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_MC_MCONTROL_Bits.DIR */
|
||||
#define IFX_MC_MCONTROL_DIR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_MCONTROL_Bits.DIR */
|
||||
#define IFX_MC_MCONTROL_DIR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_MCONTROL_Bits.DIR */
|
||||
#define IFX_MC_MCONTROL_DIR_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_MC_MCONTROL_Bits.ESTF */
|
||||
#define IFX_MC_MCONTROL_ESTF_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_MCONTROL_Bits.ESTF */
|
||||
#define IFX_MC_MCONTROL_ESTF_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_MCONTROL_Bits.ESTF */
|
||||
#define IFX_MC_MCONTROL_ESTF_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_MC_MCONTROL_Bits.FAILDMP */
|
||||
#define IFX_MC_MCONTROL_FAILDMP_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_MCONTROL_Bits.FAILDMP */
|
||||
#define IFX_MC_MCONTROL_FAILDMP_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_MCONTROL_Bits.FAILDMP */
|
||||
#define IFX_MC_MCONTROL_FAILDMP_OFF (9u)
|
||||
|
||||
/** \brief Length for Ifx_MC_MCONTROL_Bits.GP_BASE */
|
||||
#define IFX_MC_MCONTROL_GP_BASE_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_MCONTROL_Bits.GP_BASE */
|
||||
#define IFX_MC_MCONTROL_GP_BASE_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_MCONTROL_Bits.GP_BASE */
|
||||
#define IFX_MC_MCONTROL_GP_BASE_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_MC_MCONTROL_Bits.RCADR */
|
||||
#define IFX_MC_MCONTROL_RCADR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_MCONTROL_Bits.RCADR */
|
||||
#define IFX_MC_MCONTROL_RCADR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_MCONTROL_Bits.RCADR */
|
||||
#define IFX_MC_MCONTROL_RCADR_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_MC_MCONTROL_Bits.RESUME */
|
||||
#define IFX_MC_MCONTROL_RESUME_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_MCONTROL_Bits.RESUME */
|
||||
#define IFX_MC_MCONTROL_RESUME_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_MCONTROL_Bits.RESUME */
|
||||
#define IFX_MC_MCONTROL_RESUME_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_MC_MCONTROL_Bits.ROWTOG */
|
||||
#define IFX_MC_MCONTROL_ROWTOG_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_MCONTROL_Bits.ROWTOG */
|
||||
#define IFX_MC_MCONTROL_ROWTOG_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_MCONTROL_Bits.ROWTOG */
|
||||
#define IFX_MC_MCONTROL_ROWTOG_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_MC_MCONTROL_Bits.START */
|
||||
#define IFX_MC_MCONTROL_START_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_MCONTROL_Bits.START */
|
||||
#define IFX_MC_MCONTROL_START_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_MCONTROL_Bits.START */
|
||||
#define IFX_MC_MCONTROL_START_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_MC_MSTATUS_Bits.DONE */
|
||||
#define IFX_MC_MSTATUS_DONE_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_MSTATUS_Bits.DONE */
|
||||
#define IFX_MC_MSTATUS_DONE_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_MSTATUS_Bits.DONE */
|
||||
#define IFX_MC_MSTATUS_DONE_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_MC_MSTATUS_Bits.FAIL */
|
||||
#define IFX_MC_MSTATUS_FAIL_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_MSTATUS_Bits.FAIL */
|
||||
#define IFX_MC_MSTATUS_FAIL_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_MSTATUS_Bits.FAIL */
|
||||
#define IFX_MC_MSTATUS_FAIL_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_MC_MSTATUS_Bits.FDA */
|
||||
#define IFX_MC_MSTATUS_FDA_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_MSTATUS_Bits.FDA */
|
||||
#define IFX_MC_MSTATUS_FDA_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_MSTATUS_Bits.FDA */
|
||||
#define IFX_MC_MSTATUS_FDA_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_MC_MSTATUS_Bits.SFAIL */
|
||||
#define IFX_MC_MSTATUS_SFAIL_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_MSTATUS_Bits.SFAIL */
|
||||
#define IFX_MC_MSTATUS_SFAIL_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_MSTATUS_Bits.SFAIL */
|
||||
#define IFX_MC_MSTATUS_SFAIL_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_MC_RANGE_Bits.ADDR */
|
||||
#define IFX_MC_RANGE_ADDR_LEN (15u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_RANGE_Bits.ADDR */
|
||||
#define IFX_MC_RANGE_ADDR_MSK (0x7fffu)
|
||||
|
||||
/** \brief Offset for Ifx_MC_RANGE_Bits.ADDR */
|
||||
#define IFX_MC_RANGE_ADDR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_MC_RANGE_Bits.RAEN */
|
||||
#define IFX_MC_RANGE_RAEN_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_RANGE_Bits.RAEN */
|
||||
#define IFX_MC_RANGE_RAEN_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_MC_RANGE_Bits.RAEN */
|
||||
#define IFX_MC_RANGE_RAEN_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_MC_RDBFL_Bits.WDATA */
|
||||
#define IFX_MC_RDBFL_WDATA_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_RDBFL_Bits.WDATA */
|
||||
#define IFX_MC_RDBFL_WDATA_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_MC_RDBFL_Bits.WDATA */
|
||||
#define IFX_MC_RDBFL_WDATA_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_MC_REVID_Bits.REV_ID */
|
||||
#define IFX_MC_REVID_REV_ID_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_MC_REVID_Bits.REV_ID */
|
||||
#define IFX_MC_REVID_REV_ID_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_MC_REVID_Bits.REV_ID */
|
||||
#define IFX_MC_REVID_REV_ID_OFF (0u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXMC_BF_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,259 +0,0 @@
|
||||
/**
|
||||
* \file IfxMc_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Mc Mc
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Mc_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Mc
|
||||
*
|
||||
* \defgroup IfxLld_Mc_union Union
|
||||
* \ingroup IfxLld_Mc
|
||||
*
|
||||
* \defgroup IfxLld_Mc_struct Struct
|
||||
* \ingroup IfxLld_Mc
|
||||
*
|
||||
*/
|
||||
#ifndef IFXMC_REGDEF_H
|
||||
#define IFXMC_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Mc_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Configuration Register 0 */
|
||||
typedef struct _Ifx_MC_CONFIG0_Bits
|
||||
{
|
||||
Ifx_Strict_16Bit ACCSTYPE:8; /**< \brief [7:0] Access type (rw) */
|
||||
Ifx_Strict_16Bit reserved_8:4; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_16Bit NUMACCS:4; /**< \brief [15:12] Number of accesses per address (rw) */
|
||||
} Ifx_MC_CONFIG0_Bits;
|
||||
|
||||
/** \brief Configuration Register 1 */
|
||||
typedef struct _Ifx_MC_CONFIG1_Bits
|
||||
{
|
||||
Ifx_Strict_16Bit ACCSPAT:8; /**< \brief [7:0] Access pattern (rw) */
|
||||
Ifx_Strict_16Bit SELFASTB:4; /**< \brief [11:8] Select Fast Bit (rw) */
|
||||
Ifx_Strict_16Bit AG_MOD:4; /**< \brief [15:12] Address Generator Mode (rw) */
|
||||
} Ifx_MC_CONFIG1_Bits;
|
||||
|
||||
/** \brief Memory ECC Detection Register */
|
||||
typedef struct _Ifx_MC_ECCD_Bits
|
||||
{
|
||||
Ifx_Strict_16Bit SERR:1; /**< \brief [0:0] Error Detected (rwh) */
|
||||
Ifx_Strict_16Bit CERR:1; /**< \brief [1:1] Correctable Error Detected (rwh) */
|
||||
Ifx_Strict_16Bit UERR:1; /**< \brief [2:2] Uncorrectable Error Detected (rwh) */
|
||||
Ifx_Strict_16Bit AERR:1; /**< \brief [3:3] Address Error Detected (rwh) */
|
||||
Ifx_Strict_16Bit TRC:1; /**< \brief [4:4] Tracking Clear (w) */
|
||||
Ifx_Strict_16Bit VAL:5; /**< \brief [9:5] Valid Bits (rh) */
|
||||
Ifx_Strict_16Bit RARVAL:1; /**< \brief [10:10] RAR Valid (rwh) */
|
||||
Ifx_Strict_16Bit CENE:1; /**< \brief [11:11] Correctable Error Notification Enable (rw) */
|
||||
Ifx_Strict_16Bit UENE:1; /**< \brief [12:12] Uncorrectable Error Notification Enable (rw) */
|
||||
Ifx_Strict_16Bit AENE:1; /**< \brief [13:13] Address Error Notification Enable (rw) */
|
||||
Ifx_Strict_16Bit ECE:1; /**< \brief [14:14] Error Correction Enable (rw) */
|
||||
Ifx_Strict_16Bit EOV:1; /**< \brief [15:15] Error Overflow (rh) */
|
||||
} Ifx_MC_ECCD_Bits;
|
||||
|
||||
/** \brief ECC Safety Register */
|
||||
typedef struct _Ifx_MC_ECCS_Bits
|
||||
{
|
||||
Ifx_Strict_16Bit CENE:1; /**< \brief [0:0] Correctable Error Notification Enable (rw) */
|
||||
Ifx_Strict_16Bit UENE:1; /**< \brief [1:1] Uncorrectable Error Notification Enable (rw) */
|
||||
Ifx_Strict_16Bit AENE:1; /**< \brief [2:2] Address Error Notification Enable (rw) */
|
||||
Ifx_Strict_16Bit ECE:1; /**< \brief [3:3] Error Correction Enable (rw) */
|
||||
Ifx_Strict_16Bit TRE:1; /**< \brief [4:4] Tracking Enable (rw) */
|
||||
Ifx_Strict_16Bit BFLE:1; /**< \brief [5:5] Bit Flip Enable (rw) */
|
||||
Ifx_Strict_16Bit SFLE:2; /**< \brief [7:6] Signature Bit Flip Enables (rw) */
|
||||
Ifx_Strict_16Bit ECCMAP:2; /**< \brief [9:8] ECC Bit Mapping Mode (rw) */
|
||||
Ifx_Strict_16Bit TC_WAY_SEL:2; /**< \brief [11:10] TriCore Cache Way Select (rw) */
|
||||
Ifx_Strict_16Bit reserved_12:4; /**< \brief \internal Reserved */
|
||||
} Ifx_MC_ECCS_Bits;
|
||||
|
||||
/** \brief Error Tracking Register */
|
||||
typedef struct _Ifx_MC_ETRR_Bits
|
||||
{
|
||||
Ifx_Strict_16Bit ADDR:13; /**< \brief [12:0] Address of Error(i) (rh) */
|
||||
Ifx_Strict_16Bit MBI:3; /**< \brief [15:13] Memory Block Index of Error(i) (rh) */
|
||||
} Ifx_MC_ETRR_Bits;
|
||||
|
||||
/** \brief MBIST Control Register */
|
||||
typedef struct _Ifx_MC_MCONTROL_Bits
|
||||
{
|
||||
Ifx_Strict_16Bit START:1; /**< \brief [0:0] START (rw) */
|
||||
Ifx_Strict_16Bit RESUME:1; /**< \brief [1:1] Resume failed test (rwh) */
|
||||
Ifx_Strict_16Bit ESTF:1; /**< \brief [2:2] Enable Sticky Fail Bit (rw) */
|
||||
Ifx_Strict_16Bit DIR:1; /**< \brief [3:3] Direction Select (rw) */
|
||||
Ifx_Strict_16Bit DINIT:1; /**< \brief [4:4] Data Initialization Enable (rw) */
|
||||
Ifx_Strict_16Bit RCADR:1; /**< \brief [5:5] Fast Row / Fast Column Addressing Scheme Select (rw) */
|
||||
Ifx_Strict_16Bit ROWTOG:1; /**< \brief [6:6] Row toggling (rw) */
|
||||
Ifx_Strict_16Bit BITTOG:1; /**< \brief [7:7] Bit toggling (rw) */
|
||||
Ifx_Strict_16Bit GP_BASE:1; /**< \brief [8:8] Galpat Base (rw) */
|
||||
Ifx_Strict_16Bit FAILDMP:1; /**< \brief [9:9] Fail bitmap dump (rw) */
|
||||
Ifx_Strict_16Bit reserved_10:6; /**< \brief \internal Reserved */
|
||||
} Ifx_MC_MCONTROL_Bits;
|
||||
|
||||
/** \brief Status Register */
|
||||
typedef struct _Ifx_MC_MSTATUS_Bits
|
||||
{
|
||||
Ifx_Strict_16Bit DONE:1; /**< \brief [0:0] DONE (rh) */
|
||||
Ifx_Strict_16Bit FAIL:1; /**< \brief [1:1] FAIL (rh) */
|
||||
Ifx_Strict_16Bit FDA:1; /**< \brief [2:2] Fail Dump Available (rh) */
|
||||
Ifx_Strict_16Bit SFAIL:1; /**< \brief [3:3] Sticky Fail Bit (rh) */
|
||||
Ifx_Strict_16Bit reserved_4:12; /**< \brief \internal Reserved */
|
||||
} Ifx_MC_MSTATUS_Bits;
|
||||
|
||||
/** \brief Range Register, single address mode */
|
||||
typedef struct _Ifx_MC_RANGE_Bits
|
||||
{
|
||||
Ifx_Strict_16Bit ADDR:15; /**< \brief [14:0] Address (rw) */
|
||||
Ifx_Strict_16Bit RAEN:1; /**< \brief [15:15] Range Enable (rw) */
|
||||
} Ifx_MC_RANGE_Bits;
|
||||
|
||||
/** \brief Read Data and Bit Flip Register */
|
||||
typedef struct _Ifx_MC_RDBFL_Bits
|
||||
{
|
||||
Ifx_Strict_16Bit WDATA:16; /**< \brief [15:0] Word Data (rwh) */
|
||||
} Ifx_MC_RDBFL_Bits;
|
||||
|
||||
/** \brief Revision ID Register */
|
||||
typedef struct _Ifx_MC_REVID_Bits
|
||||
{
|
||||
Ifx_Strict_16Bit REV_ID:16; /**< \brief [15:0] Revision Identifier (r) */
|
||||
} Ifx_MC_REVID_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Mc_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Configuration Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned short U; /**< \brief Unsigned access */
|
||||
signed short I; /**< \brief Signed access */
|
||||
Ifx_MC_CONFIG0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MC_CONFIG0;
|
||||
|
||||
/** \brief Configuration Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned short U; /**< \brief Unsigned access */
|
||||
signed short I; /**< \brief Signed access */
|
||||
Ifx_MC_CONFIG1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MC_CONFIG1;
|
||||
|
||||
/** \brief Memory ECC Detection Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned short U; /**< \brief Unsigned access */
|
||||
signed short I; /**< \brief Signed access */
|
||||
Ifx_MC_ECCD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MC_ECCD;
|
||||
|
||||
/** \brief ECC Safety Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned short U; /**< \brief Unsigned access */
|
||||
signed short I; /**< \brief Signed access */
|
||||
Ifx_MC_ECCS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MC_ECCS;
|
||||
|
||||
/** \brief Error Tracking Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned short U; /**< \brief Unsigned access */
|
||||
signed short I; /**< \brief Signed access */
|
||||
Ifx_MC_ETRR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MC_ETRR;
|
||||
|
||||
/** \brief MBIST Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned short U; /**< \brief Unsigned access */
|
||||
signed short I; /**< \brief Signed access */
|
||||
Ifx_MC_MCONTROL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MC_MCONTROL;
|
||||
|
||||
/** \brief Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned short U; /**< \brief Unsigned access */
|
||||
signed short I; /**< \brief Signed access */
|
||||
Ifx_MC_MSTATUS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MC_MSTATUS;
|
||||
|
||||
/** \brief Range Register, single address mode */
|
||||
typedef union
|
||||
{
|
||||
unsigned short U; /**< \brief Unsigned access */
|
||||
signed short I; /**< \brief Signed access */
|
||||
Ifx_MC_RANGE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MC_RANGE;
|
||||
|
||||
/** \brief Read Data and Bit Flip Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned short U; /**< \brief Unsigned access */
|
||||
signed short I; /**< \brief Signed access */
|
||||
Ifx_MC_RDBFL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MC_RDBFL;
|
||||
|
||||
/** \brief Revision ID Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned short U; /**< \brief Unsigned access */
|
||||
signed short I; /**< \brief Signed access */
|
||||
Ifx_MC_REVID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MC_REVID;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Mc_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief MC object */
|
||||
typedef volatile struct _Ifx_MC
|
||||
{
|
||||
Ifx_MC_CONFIG0 CONFIG0; /**< \brief 0, Configuration Register 0 */
|
||||
Ifx_MC_CONFIG1 CONFIG1; /**< \brief 2, Configuration Register 1 */
|
||||
Ifx_MC_MCONTROL MCONTROL; /**< \brief 4, MBIST Control Register */
|
||||
Ifx_MC_MSTATUS MSTATUS; /**< \brief 6, Status Register */
|
||||
Ifx_MC_RANGE RANGE; /**< \brief 8, Range Register, single address mode */
|
||||
unsigned char reserved_A[2]; /**< \brief A, \internal Reserved */
|
||||
Ifx_MC_REVID REVID; /**< \brief C, Revision ID Register */
|
||||
Ifx_MC_ECCS ECCS; /**< \brief E, ECC Safety Register */
|
||||
Ifx_MC_ECCD ECCD; /**< \brief 10, Memory ECC Detection Register */
|
||||
Ifx_MC_ETRR ETRR[5]; /**< \brief 12, Error Tracking Register */
|
||||
unsigned char reserved_1C[132]; /**< \brief 1C, \internal Reserved */
|
||||
Ifx_MC_RDBFL RDBFL[40]; /**< \brief A0, Read Data and Bit Flip Register */
|
||||
unsigned char reserved_F0[16]; /**< \brief F0, \internal Reserved */
|
||||
} Ifx_MC;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXMC_REGDEF_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,266 +0,0 @@
|
||||
/**
|
||||
* \file IfxMsc_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Msc_Cfg Msc address
|
||||
* \ingroup IfxLld_Msc
|
||||
*
|
||||
* \defgroup IfxLld_Msc_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Msc_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Msc_Cfg_Msc0 2-MSC0
|
||||
* \ingroup IfxLld_Msc_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Msc_Cfg_Msc1 2-MSC1
|
||||
* \ingroup IfxLld_Msc_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXMSC_REG_H
|
||||
#define IFXMSC_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxMsc_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Msc_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief MSC object */
|
||||
#define MODULE_MSC0 /*lint --e(923)*/ (*(Ifx_MSC*)0xF0002600u)
|
||||
|
||||
/** \brief MSC object */
|
||||
#define MODULE_MSC1 /*lint --e(923)*/ (*(Ifx_MSC*)0xF0002700u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Msc_Cfg_Msc0
|
||||
* \{ */
|
||||
|
||||
/** \brief 80, Asynchronous Block Configuration Register */
|
||||
#define MSC0_ABC /*lint --e(923)*/ (*(volatile Ifx_MSC_ABC*)0xF0002680u)
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define MSC0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_MSC_ACCEN0*)0xF00026FCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define MSC0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_MSC_ACCEN1*)0xF00026F8u)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define MSC0_CLC /*lint --e(923)*/ (*(volatile Ifx_MSC_CLC*)0xF0002600u)
|
||||
|
||||
/** \brief 20, Downstream Command Register */
|
||||
#define MSC0_DC /*lint --e(923)*/ (*(volatile Ifx_MSC_DC*)0xF0002620u)
|
||||
|
||||
/** \brief 1C, Downstream Data Register */
|
||||
#define MSC0_DD /*lint --e(923)*/ (*(volatile Ifx_MSC_DD*)0xF000261Cu)
|
||||
|
||||
/** \brief 6C, Downstream Data Extension Register */
|
||||
#define MSC0_DDE /*lint --e(923)*/ (*(volatile Ifx_MSC_DDE*)0xF000266Cu)
|
||||
|
||||
/** \brief 70, Downstream Data Mirror Register */
|
||||
#define MSC0_DDM /*lint --e(923)*/ (*(volatile Ifx_MSC_DDM*)0xF0002670u)
|
||||
|
||||
/** \brief 14, Downstream Control Register */
|
||||
#define MSC0_DSC /*lint --e(923)*/ (*(volatile Ifx_MSC_DSC*)0xF0002614u)
|
||||
|
||||
/** \brief 58, Downstream Control Enhanced Register 1 */
|
||||
#define MSC0_DSCE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSCE*)0xF0002658u)
|
||||
|
||||
/** \brief 28, Downstream Select Data Source High Register */
|
||||
#define MSC0_DSDSH /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSH*)0xF0002628u)
|
||||
|
||||
/** \brief 64, Downstream Select Data Source High Register */
|
||||
#define MSC0_DSDSHE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSHE*)0xF0002664u)
|
||||
|
||||
/** \brief 24, Downstream Select Data Source Low Register */
|
||||
#define MSC0_DSDSL /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSL*)0xF0002624u)
|
||||
|
||||
/** \brief 60, Downstream Select Data Source Low Extension Register */
|
||||
#define MSC0_DSDSLE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSLE*)0xF0002660u)
|
||||
|
||||
/** \brief 18, Downstream Status Register */
|
||||
#define MSC0_DSS /*lint --e(923)*/ (*(volatile Ifx_MSC_DSS*)0xF0002618u)
|
||||
|
||||
/** \brief 74, Downstream Timing Extension Register */
|
||||
#define MSC0_DSTE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSTE*)0xF0002674u)
|
||||
|
||||
/** \brief 2C, Emergency Stop Register */
|
||||
#define MSC0_ESR /*lint --e(923)*/ (*(volatile Ifx_MSC_ESR*)0xF000262Cu)
|
||||
|
||||
/** \brief 68, Emergency Stop Extension Register */
|
||||
#define MSC0_ESRE /*lint --e(923)*/ (*(volatile Ifx_MSC_ESRE*)0xF0002668u)
|
||||
|
||||
/** \brief C, Fractional Divider Register */
|
||||
#define MSC0_FDR /*lint --e(923)*/ (*(volatile Ifx_MSC_FDR*)0xF000260Cu)
|
||||
|
||||
/** \brief 40, Interrupt Control Register */
|
||||
#define MSC0_ICR /*lint --e(923)*/ (*(volatile Ifx_MSC_ICR*)0xF0002640u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define MSC0_ID /*lint --e(923)*/ (*(volatile Ifx_MSC_ID*)0xF0002608u)
|
||||
|
||||
/** \brief 48, Interrupt Set Clear Register */
|
||||
#define MSC0_ISC /*lint --e(923)*/ (*(volatile Ifx_MSC_ISC*)0xF0002648u)
|
||||
|
||||
/** \brief 44, Interrupt Status Register */
|
||||
#define MSC0_ISR /*lint --e(923)*/ (*(volatile Ifx_MSC_ISR*)0xF0002644u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define MSC0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_MSC_KRST0*)0xF00026F4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define MSC0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_MSC_KRST1*)0xF00026F0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define MSC0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_MSC_KRSTCLR*)0xF00026ECu)
|
||||
|
||||
/** \brief 4C, Output Control Register */
|
||||
#define MSC0_OCR /*lint --e(923)*/ (*(volatile Ifx_MSC_OCR*)0xF000264Cu)
|
||||
|
||||
/** \brief E8, OCDS Control and Status */
|
||||
#define MSC0_OCS /*lint --e(923)*/ (*(volatile Ifx_MSC_OCS*)0xF00026E8u)
|
||||
|
||||
/** \brief 30, Upstream Data Register */
|
||||
#define MSC0_UD0 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF0002630u)
|
||||
|
||||
/** \brief 34, Upstream Data Register */
|
||||
#define MSC0_UD1 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF0002634u)
|
||||
|
||||
/** \brief 38, Upstream Data Register */
|
||||
#define MSC0_UD2 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF0002638u)
|
||||
|
||||
/** \brief 3C, Upstream Data Register */
|
||||
#define MSC0_UD3 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF000263Cu)
|
||||
|
||||
/** \brief 5C, Upstream Control Enhanced Register 1 */
|
||||
#define MSC0_USCE /*lint --e(923)*/ (*(volatile Ifx_MSC_USCE*)0xF000265Cu)
|
||||
|
||||
/** \brief 10, Upstream Status Register */
|
||||
#define MSC0_USR /*lint --e(923)*/ (*(volatile Ifx_MSC_USR*)0xF0002610u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Msc_Cfg_Msc1
|
||||
* \{ */
|
||||
|
||||
/** \brief 80, Asynchronous Block Configuration Register */
|
||||
#define MSC1_ABC /*lint --e(923)*/ (*(volatile Ifx_MSC_ABC*)0xF0002780u)
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define MSC1_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_MSC_ACCEN0*)0xF00027FCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define MSC1_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_MSC_ACCEN1*)0xF00027F8u)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define MSC1_CLC /*lint --e(923)*/ (*(volatile Ifx_MSC_CLC*)0xF0002700u)
|
||||
|
||||
/** \brief 20, Downstream Command Register */
|
||||
#define MSC1_DC /*lint --e(923)*/ (*(volatile Ifx_MSC_DC*)0xF0002720u)
|
||||
|
||||
/** \brief 1C, Downstream Data Register */
|
||||
#define MSC1_DD /*lint --e(923)*/ (*(volatile Ifx_MSC_DD*)0xF000271Cu)
|
||||
|
||||
/** \brief 6C, Downstream Data Extension Register */
|
||||
#define MSC1_DDE /*lint --e(923)*/ (*(volatile Ifx_MSC_DDE*)0xF000276Cu)
|
||||
|
||||
/** \brief 70, Downstream Data Mirror Register */
|
||||
#define MSC1_DDM /*lint --e(923)*/ (*(volatile Ifx_MSC_DDM*)0xF0002770u)
|
||||
|
||||
/** \brief 14, Downstream Control Register */
|
||||
#define MSC1_DSC /*lint --e(923)*/ (*(volatile Ifx_MSC_DSC*)0xF0002714u)
|
||||
|
||||
/** \brief 58, Downstream Control Enhanced Register 1 */
|
||||
#define MSC1_DSCE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSCE*)0xF0002758u)
|
||||
|
||||
/** \brief 28, Downstream Select Data Source High Register */
|
||||
#define MSC1_DSDSH /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSH*)0xF0002728u)
|
||||
|
||||
/** \brief 64, Downstream Select Data Source High Register */
|
||||
#define MSC1_DSDSHE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSHE*)0xF0002764u)
|
||||
|
||||
/** \brief 24, Downstream Select Data Source Low Register */
|
||||
#define MSC1_DSDSL /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSL*)0xF0002724u)
|
||||
|
||||
/** \brief 60, Downstream Select Data Source Low Extension Register */
|
||||
#define MSC1_DSDSLE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSDSLE*)0xF0002760u)
|
||||
|
||||
/** \brief 18, Downstream Status Register */
|
||||
#define MSC1_DSS /*lint --e(923)*/ (*(volatile Ifx_MSC_DSS*)0xF0002718u)
|
||||
|
||||
/** \brief 74, Downstream Timing Extension Register */
|
||||
#define MSC1_DSTE /*lint --e(923)*/ (*(volatile Ifx_MSC_DSTE*)0xF0002774u)
|
||||
|
||||
/** \brief 2C, Emergency Stop Register */
|
||||
#define MSC1_ESR /*lint --e(923)*/ (*(volatile Ifx_MSC_ESR*)0xF000272Cu)
|
||||
|
||||
/** \brief 68, Emergency Stop Extension Register */
|
||||
#define MSC1_ESRE /*lint --e(923)*/ (*(volatile Ifx_MSC_ESRE*)0xF0002768u)
|
||||
|
||||
/** \brief C, Fractional Divider Register */
|
||||
#define MSC1_FDR /*lint --e(923)*/ (*(volatile Ifx_MSC_FDR*)0xF000270Cu)
|
||||
|
||||
/** \brief 40, Interrupt Control Register */
|
||||
#define MSC1_ICR /*lint --e(923)*/ (*(volatile Ifx_MSC_ICR*)0xF0002740u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define MSC1_ID /*lint --e(923)*/ (*(volatile Ifx_MSC_ID*)0xF0002708u)
|
||||
|
||||
/** \brief 48, Interrupt Set Clear Register */
|
||||
#define MSC1_ISC /*lint --e(923)*/ (*(volatile Ifx_MSC_ISC*)0xF0002748u)
|
||||
|
||||
/** \brief 44, Interrupt Status Register */
|
||||
#define MSC1_ISR /*lint --e(923)*/ (*(volatile Ifx_MSC_ISR*)0xF0002744u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define MSC1_KRST0 /*lint --e(923)*/ (*(volatile Ifx_MSC_KRST0*)0xF00027F4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define MSC1_KRST1 /*lint --e(923)*/ (*(volatile Ifx_MSC_KRST1*)0xF00027F0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define MSC1_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_MSC_KRSTCLR*)0xF00027ECu)
|
||||
|
||||
/** \brief 4C, Output Control Register */
|
||||
#define MSC1_OCR /*lint --e(923)*/ (*(volatile Ifx_MSC_OCR*)0xF000274Cu)
|
||||
|
||||
/** \brief E8, OCDS Control and Status */
|
||||
#define MSC1_OCS /*lint --e(923)*/ (*(volatile Ifx_MSC_OCS*)0xF00027E8u)
|
||||
|
||||
/** \brief 30, Upstream Data Register */
|
||||
#define MSC1_UD0 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF0002730u)
|
||||
|
||||
/** \brief 34, Upstream Data Register */
|
||||
#define MSC1_UD1 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF0002734u)
|
||||
|
||||
/** \brief 38, Upstream Data Register */
|
||||
#define MSC1_UD2 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF0002738u)
|
||||
|
||||
/** \brief 3C, Upstream Data Register */
|
||||
#define MSC1_UD3 /*lint --e(923)*/ (*(volatile Ifx_MSC_UD*)0xF000273Cu)
|
||||
|
||||
/** \brief 5C, Upstream Control Enhanced Register 1 */
|
||||
#define MSC1_USCE /*lint --e(923)*/ (*(volatile Ifx_MSC_USCE*)0xF000275Cu)
|
||||
|
||||
/** \brief 10, Upstream Status Register */
|
||||
#define MSC1_USR /*lint --e(923)*/ (*(volatile Ifx_MSC_USR*)0xF0002710u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXMSC_REG_H */
|
||||
@@ -1,823 +0,0 @@
|
||||
/**
|
||||
* \file IfxMsc_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Msc Msc
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Msc_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Msc
|
||||
*
|
||||
* \defgroup IfxLld_Msc_union Union
|
||||
* \ingroup IfxLld_Msc
|
||||
*
|
||||
* \defgroup IfxLld_Msc_struct Struct
|
||||
* \ingroup IfxLld_Msc
|
||||
*
|
||||
*/
|
||||
#ifndef IFXMSC_REGDEF_H
|
||||
#define IFXMSC_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Msc_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Asynchronous Block Configuration Register */
|
||||
typedef struct _Ifx_MSC_ABC_Bits
|
||||
{
|
||||
unsigned int LOW:4; /**< \brief [3:0] Duration of the Low Phase of the Shift Clock (rw) */
|
||||
unsigned int HIGH:4; /**< \brief [7:4] Duration of the High Phase of the Shift Clock (rw) */
|
||||
unsigned int OIP:2; /**< \brief [9:8] Overflow Interrupt Node Pointer (rw) */
|
||||
unsigned int OASR:1; /**< \brief [10:10] Overflow Alternate Service Request (rw) */
|
||||
unsigned int reserved_11:1; /**< \brief \internal Reserved */
|
||||
unsigned int OVF:1; /**< \brief [12:12] Overflow Flag (r) */
|
||||
unsigned int OFM:2; /**< \brief [14:13] Overflow Flag Modify (w) */
|
||||
unsigned int OIE:1; /**< \brief [15:15] Overflow Interrupt Enable (rw) */
|
||||
unsigned int NDA:3; /**< \brief [18:16] N Divider ABRA (rw) */
|
||||
unsigned int UIP:2; /**< \brief [20:19] Underflow Interrupt Node Pointer (rw) */
|
||||
unsigned int UASR:1; /**< \brief [21:21] Underflow Alternate Service Request (rw) */
|
||||
unsigned int reserved_22:1; /**< \brief \internal Reserved */
|
||||
unsigned int UNF:1; /**< \brief [23:23] Underflow Flag (r) */
|
||||
unsigned int UFM:2; /**< \brief [25:24] Underflow Flag Modify (w) */
|
||||
unsigned int UIE:1; /**< \brief [26:26] Underflow Interrupt Enable (rw) */
|
||||
unsigned int CLKSEL:3; /**< \brief [29:27] Clock Select (rw) */
|
||||
unsigned int reserved_30:1; /**< \brief \internal Reserved */
|
||||
unsigned int ABB:1; /**< \brief [31:31] Asynchronous Block Bypass (rw) */
|
||||
} Ifx_MSC_ABC_Bits;
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_MSC_ACCEN0_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_MSC_ACCEN0_Bits;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef struct _Ifx_MSC_ACCEN1_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_ACCEN1_Bits;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef struct _Ifx_MSC_CLC_Bits
|
||||
{
|
||||
unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
|
||||
unsigned int reserved_2:1; /**< \brief \internal Reserved */
|
||||
unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_CLC_Bits;
|
||||
|
||||
/** \brief Downstream Command Register */
|
||||
typedef struct _Ifx_MSC_DC_Bits
|
||||
{
|
||||
unsigned int DCL:16; /**< \brief [15:0] Downstream Command for SRL Shift Register (rw) */
|
||||
unsigned int DCH:16; /**< \brief [31:16] Downstream Command for SRH Shift Register (rw) */
|
||||
} Ifx_MSC_DC_Bits;
|
||||
|
||||
/** \brief Downstream Data Register */
|
||||
typedef struct _Ifx_MSC_DD_Bits
|
||||
{
|
||||
unsigned int DDL:16; /**< \brief [15:0] Downstream Data for SRL Shift Register (rw) */
|
||||
unsigned int DDH:16; /**< \brief [31:16] Downstream Data for SRH Shift Register (rw) */
|
||||
} Ifx_MSC_DD_Bits;
|
||||
|
||||
/** \brief Downstream Data Extension Register */
|
||||
typedef struct _Ifx_MSC_DDE_Bits
|
||||
{
|
||||
unsigned int DDLE:16; /**< \brief [15:0] Downstream Data Extension for SRL Shift Register (rw) */
|
||||
unsigned int DDHE:16; /**< \brief [31:16] Downstream Data Extension for SRH Shift Register (rw) */
|
||||
} Ifx_MSC_DDE_Bits;
|
||||
|
||||
/** \brief Downstream Data Mirror Register */
|
||||
typedef struct _Ifx_MSC_DDM_Bits
|
||||
{
|
||||
unsigned int DDLM:16; /**< \brief [15:0] Downstream Data Mirror for SRL Shift Register (w) */
|
||||
unsigned int DDHM:16; /**< \brief [31:16] Downstream Data Mirror for SRH Shift Register (w) */
|
||||
} Ifx_MSC_DDM_Bits;
|
||||
|
||||
/** \brief Downstream Control Register */
|
||||
typedef struct _Ifx_MSC_DSC_Bits
|
||||
{
|
||||
unsigned int TM:1; /**< \brief [0:0] Transmission Mode (rw) */
|
||||
unsigned int CP:1; /**< \brief [1:1] Command Pending (rh) */
|
||||
unsigned int DP:1; /**< \brief [2:2] Data Pending (rh) */
|
||||
unsigned int NDBL:5; /**< \brief [7:3] Number of SRL Bits Shifted at Data Frames (rw) */
|
||||
unsigned int NDBH:5; /**< \brief [12:8] Number of SRH Bits Shifted at Data Frames (rw) */
|
||||
unsigned int ENSELL:1; /**< \brief [13:13] Enable SRL Active Phase Selection Bit (rw) */
|
||||
unsigned int ENSELH:1; /**< \brief [14:14] Enable SRH Active Phase Selection Bit (rw) */
|
||||
unsigned int DSDIS:1; /**< \brief [15:15] Downstream Disable (rh) */
|
||||
unsigned int NBC:6; /**< \brief [21:16] Number of Bits Shifted at Command Frames (rw) */
|
||||
unsigned int reserved_22:2; /**< \brief \internal Reserved */
|
||||
unsigned int PPD:5; /**< \brief [28:24] Passive Phase Length at Data Frames (rw) */
|
||||
unsigned int reserved_29:3; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_DSC_Bits;
|
||||
|
||||
/** \brief Downstream Control Enhanced Register 1 */
|
||||
typedef struct _Ifx_MSC_DSCE_Bits
|
||||
{
|
||||
unsigned int NDBHE:1; /**< \brief [0:0] Number of SRH Bits Shifted at Data Frames Extension (rw) */
|
||||
unsigned int NDBLE:1; /**< \brief [1:1] Number of SRH Bits Shifted at Data Frames Extension (rw) */
|
||||
unsigned int reserved_2:12; /**< \brief \internal Reserved */
|
||||
unsigned int EXEN:1; /**< \brief [14:14] Extension Enable (rw) */
|
||||
unsigned int CCF:1; /**< \brief [15:15] Command-Comand Flag (rh) */
|
||||
unsigned int INJENP0:1; /**< \brief [16:16] Injection Enable of the Pin 0 Signal (rw) */
|
||||
unsigned int INJPOSP0:6; /**< \brief [22:17] Injection Position of the Pin 0 Signal (rw) */
|
||||
unsigned int reserved_23:1; /**< \brief \internal Reserved */
|
||||
unsigned int INJENP1:1; /**< \brief [24:24] Injection Enable of the Pin 1 Signal (rw) */
|
||||
unsigned int INJPOSP1:6; /**< \brief [30:25] Injection Position of the Pin 1 Signal (rw) */
|
||||
unsigned int CDCM:1; /**< \brief [31:31] Command-Data-Comand in Data Repetition Mode (rw) */
|
||||
} Ifx_MSC_DSCE_Bits;
|
||||
|
||||
/** \brief Downstream Select Data Source High Register */
|
||||
typedef struct _Ifx_MSC_DSDSH_Bits
|
||||
{
|
||||
unsigned int SH0:2; /**< \brief [1:0] Select Source for SRH (rw) */
|
||||
unsigned int SH1:2; /**< \brief [3:2] Select Source for SRH (rw) */
|
||||
unsigned int SH2:2; /**< \brief [5:4] Select Source for SRH (rw) */
|
||||
unsigned int SH3:2; /**< \brief [7:6] Select Source for SRH (rw) */
|
||||
unsigned int SH4:2; /**< \brief [9:8] Select Source for SRH (rw) */
|
||||
unsigned int SH5:2; /**< \brief [11:10] Select Source for SRH (rw) */
|
||||
unsigned int SH6:2; /**< \brief [13:12] Select Source for SRH (rw) */
|
||||
unsigned int SH7:2; /**< \brief [15:14] Select Source for SRH (rw) */
|
||||
unsigned int SH8:2; /**< \brief [17:16] Select Source for SRH (rw) */
|
||||
unsigned int SH9:2; /**< \brief [19:18] Select Source for SRH (rw) */
|
||||
unsigned int SH10:2; /**< \brief [21:20] Select Source for SRH (rw) */
|
||||
unsigned int SH11:2; /**< \brief [23:22] Select Source for SRH (rw) */
|
||||
unsigned int SH12:2; /**< \brief [25:24] Select Source for SRH (rw) */
|
||||
unsigned int SH13:2; /**< \brief [27:26] Select Source for SRH (rw) */
|
||||
unsigned int SH14:2; /**< \brief [29:28] Select Source for SRH (rw) */
|
||||
unsigned int SH15:2; /**< \brief [31:30] Select Source for SRH (rw) */
|
||||
} Ifx_MSC_DSDSH_Bits;
|
||||
|
||||
/** \brief Downstream Select Data Source High Register */
|
||||
typedef struct _Ifx_MSC_DSDSHE_Bits
|
||||
{
|
||||
unsigned int SH16:2; /**< \brief [1:0] Select Source for SRH (rw) */
|
||||
unsigned int SH17:2; /**< \brief [3:2] Select Source for SRH (rw) */
|
||||
unsigned int SH18:2; /**< \brief [5:4] Select Source for SRH (rw) */
|
||||
unsigned int SH19:2; /**< \brief [7:6] Select Source for SRH (rw) */
|
||||
unsigned int SH20:2; /**< \brief [9:8] Select Source for SRH (rw) */
|
||||
unsigned int SH21:2; /**< \brief [11:10] Select Source for SRH (rw) */
|
||||
unsigned int SH22:2; /**< \brief [13:12] Select Source for SRH (rw) */
|
||||
unsigned int SH23:2; /**< \brief [15:14] Select Source for SRH (rw) */
|
||||
unsigned int SH24:2; /**< \brief [17:16] Select Source for SRH (rw) */
|
||||
unsigned int SH25:2; /**< \brief [19:18] Select Source for SRH (rw) */
|
||||
unsigned int SH26:2; /**< \brief [21:20] Select Source for SRH (rw) */
|
||||
unsigned int SH27:2; /**< \brief [23:22] Select Source for SRH (rw) */
|
||||
unsigned int SH28:2; /**< \brief [25:24] Select Source for SRH (rw) */
|
||||
unsigned int SH29:2; /**< \brief [27:26] Select Source for SRH (rw) */
|
||||
unsigned int SH30:2; /**< \brief [29:28] Select Source for SRH (rw) */
|
||||
unsigned int SH31:2; /**< \brief [31:30] Select Source for SRH (rw) */
|
||||
} Ifx_MSC_DSDSHE_Bits;
|
||||
|
||||
/** \brief Downstream Select Data Source Low Register */
|
||||
typedef struct _Ifx_MSC_DSDSL_Bits
|
||||
{
|
||||
unsigned int SL0:2; /**< \brief [1:0] Select Source for SRL (rw) */
|
||||
unsigned int SL1:2; /**< \brief [3:2] Select Source for SRL (rw) */
|
||||
unsigned int SL2:2; /**< \brief [5:4] Select Source for SRL (rw) */
|
||||
unsigned int SL3:2; /**< \brief [7:6] Select Source for SRL (rw) */
|
||||
unsigned int SL4:2; /**< \brief [9:8] Select Source for SRL (rw) */
|
||||
unsigned int SL5:2; /**< \brief [11:10] Select Source for SRL (rw) */
|
||||
unsigned int SL6:2; /**< \brief [13:12] Select Source for SRL (rw) */
|
||||
unsigned int SL7:2; /**< \brief [15:14] Select Source for SRL (rw) */
|
||||
unsigned int SL8:2; /**< \brief [17:16] Select Source for SRL (rw) */
|
||||
unsigned int SL9:2; /**< \brief [19:18] Select Source for SRL (rw) */
|
||||
unsigned int SL10:2; /**< \brief [21:20] Select Source for SRL (rw) */
|
||||
unsigned int SL11:2; /**< \brief [23:22] Select Source for SRL (rw) */
|
||||
unsigned int SL12:2; /**< \brief [25:24] Select Source for SRL (rw) */
|
||||
unsigned int SL13:2; /**< \brief [27:26] Select Source for SRL (rw) */
|
||||
unsigned int SL14:2; /**< \brief [29:28] Select Source for SRL (rw) */
|
||||
unsigned int SL15:2; /**< \brief [31:30] Select Source for SRL (rw) */
|
||||
} Ifx_MSC_DSDSL_Bits;
|
||||
|
||||
/** \brief Downstream Select Data Source Low Extension Register */
|
||||
typedef struct _Ifx_MSC_DSDSLE_Bits
|
||||
{
|
||||
unsigned int SL16:2; /**< \brief [1:0] Select Source for SRL (rw) */
|
||||
unsigned int SL17:2; /**< \brief [3:2] Select Source for SRL (rw) */
|
||||
unsigned int SL18:2; /**< \brief [5:4] Select Source for SRL (rw) */
|
||||
unsigned int SL19:2; /**< \brief [7:6] Select Source for SRL (rw) */
|
||||
unsigned int SL20:2; /**< \brief [9:8] Select Source for SRL (rw) */
|
||||
unsigned int SL21:2; /**< \brief [11:10] Select Source for SRL (rw) */
|
||||
unsigned int SL22:2; /**< \brief [13:12] Select Source for SRL (rw) */
|
||||
unsigned int SL23:2; /**< \brief [15:14] Select Source for SRL (rw) */
|
||||
unsigned int SL24:2; /**< \brief [17:16] Select Source for SRL (rw) */
|
||||
unsigned int SL25:2; /**< \brief [19:18] Select Source for SRL (rw) */
|
||||
unsigned int SL26:2; /**< \brief [21:20] Select Source for SRL (rw) */
|
||||
unsigned int SL27:2; /**< \brief [23:22] Select Source for SRL (rw) */
|
||||
unsigned int SL28:2; /**< \brief [25:24] Select Source for SRL (rw) */
|
||||
unsigned int SL29:2; /**< \brief [27:26] Select Source for SRL (rw) */
|
||||
unsigned int SL30:2; /**< \brief [29:28] Select Source for SRL (rw) */
|
||||
unsigned int SL31:2; /**< \brief [31:30] Select Source for SRL (rw) */
|
||||
} Ifx_MSC_DSDSLE_Bits;
|
||||
|
||||
/** \brief Downstream Status Register */
|
||||
typedef struct _Ifx_MSC_DSS_Bits
|
||||
{
|
||||
unsigned int PFC:4; /**< \brief [3:0] Passive Time Frame Counter (rh) */
|
||||
unsigned int reserved_4:4; /**< \brief \internal Reserved */
|
||||
unsigned int NPTF:4; /**< \brief [11:8] Number Of Passive Time Frames (rw) */
|
||||
unsigned int reserved_12:4; /**< \brief \internal Reserved */
|
||||
unsigned int DC:8; /**< \brief [23:16] Downstream Counter (rh) */
|
||||
unsigned int DFA:1; /**< \brief [24:24] Data Frame Active (rh) */
|
||||
unsigned int CFA:1; /**< \brief [25:25] Command Frame Active (rh) */
|
||||
unsigned int reserved_26:6; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_DSS_Bits;
|
||||
|
||||
/** \brief Downstream Timing Extension Register */
|
||||
typedef struct _Ifx_MSC_DSTE_Bits
|
||||
{
|
||||
unsigned int PPDE:2; /**< \brief [1:0] Passive Phase Length at Data Frames Extension (rw) */
|
||||
unsigned int PPCE:6; /**< \brief [7:2] Passive Phase Length at Control Frames Extension (rw) */
|
||||
unsigned int NDD:4; /**< \brief [11:8] N Divider Downstream (rw) */
|
||||
unsigned int reserved_12:20; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_DSTE_Bits;
|
||||
|
||||
/** \brief Emergency Stop Register */
|
||||
typedef struct _Ifx_MSC_ESR_Bits
|
||||
{
|
||||
unsigned int ENL0:1; /**< \brief [0:0] Emergency Stop Enable for Bit 0 in SRL (rw) */
|
||||
unsigned int ENL1:1; /**< \brief [1:1] Emergency Stop Enable for Bit 1 in SRL (rw) */
|
||||
unsigned int ENL2:1; /**< \brief [2:2] Emergency Stop Enable for Bit 2 in SRL (rw) */
|
||||
unsigned int ENL3:1; /**< \brief [3:3] Emergency Stop Enable for Bit 3 in SRL (rw) */
|
||||
unsigned int ENL4:1; /**< \brief [4:4] Emergency Stop Enable for Bit 4 in SRL (rw) */
|
||||
unsigned int ENL5:1; /**< \brief [5:5] Emergency Stop Enable for Bit 5 in SRL (rw) */
|
||||
unsigned int ENL6:1; /**< \brief [6:6] Emergency Stop Enable for Bit 6 in SRL (rw) */
|
||||
unsigned int ENL7:1; /**< \brief [7:7] Emergency Stop Enable for Bit 7 in SRL (rw) */
|
||||
unsigned int ENL8:1; /**< \brief [8:8] Emergency Stop Enable for Bit 8 in SRL (rw) */
|
||||
unsigned int ENL9:1; /**< \brief [9:9] Emergency Stop Enable for Bit 9 in SRL (rw) */
|
||||
unsigned int ENL10:1; /**< \brief [10:10] Emergency Stop Enable for Bit 10 in SRL (rw) */
|
||||
unsigned int ENL11:1; /**< \brief [11:11] Emergency Stop Enable for Bit 11 in SRL (rw) */
|
||||
unsigned int ENL12:1; /**< \brief [12:12] Emergency Stop Enable for Bit 12 in SRL (rw) */
|
||||
unsigned int ENL13:1; /**< \brief [13:13] Emergency Stop Enable for Bit 13 in SRL (rw) */
|
||||
unsigned int ENL14:1; /**< \brief [14:14] Emergency Stop Enable for Bit 14 in SRL (rw) */
|
||||
unsigned int ENL15:1; /**< \brief [15:15] Emergency Stop Enable for Bit 15 in SRL (rw) */
|
||||
unsigned int ENH0:1; /**< \brief [16:16] Emergency Stop Enable for Bit 0 in SRH (rw) */
|
||||
unsigned int ENH1:1; /**< \brief [17:17] Emergency Stop Enable for Bit 1 in SRH (rw) */
|
||||
unsigned int ENH2:1; /**< \brief [18:18] Emergency Stop Enable for Bit 2 in SRH (rw) */
|
||||
unsigned int ENH3:1; /**< \brief [19:19] Emergency Stop Enable for Bit 3 in SRH (rw) */
|
||||
unsigned int ENH4:1; /**< \brief [20:20] Emergency Stop Enable for Bit 4 in SRH (rw) */
|
||||
unsigned int ENH5:1; /**< \brief [21:21] Emergency Stop Enable for Bit 5 in SRH (rw) */
|
||||
unsigned int ENH6:1; /**< \brief [22:22] Emergency Stop Enable for Bit 6 in SRH (rw) */
|
||||
unsigned int ENH7:1; /**< \brief [23:23] Emergency Stop Enable for Bit 7 in SRH (rw) */
|
||||
unsigned int ENH8:1; /**< \brief [24:24] Emergency Stop Enable for Bit 8 in SRH (rw) */
|
||||
unsigned int ENH9:1; /**< \brief [25:25] Emergency Stop Enable for Bit 9 in SRH (rw) */
|
||||
unsigned int ENH10:1; /**< \brief [26:26] Emergency Stop Enable for Bit 10 in SRH (rw) */
|
||||
unsigned int ENH11:1; /**< \brief [27:27] Emergency Stop Enable for Bit 11 in SRH (rw) */
|
||||
unsigned int ENH12:1; /**< \brief [28:28] Emergency Stop Enable for Bit 12 in SRH (rw) */
|
||||
unsigned int ENH13:1; /**< \brief [29:29] Emergency Stop Enable for Bit 13 in SRH (rw) */
|
||||
unsigned int ENH14:1; /**< \brief [30:30] Emergency Stop Enable for Bit 14 in SRH (rw) */
|
||||
unsigned int ENH15:1; /**< \brief [31:31] Emergency Stop Enable for Bit 15 in SRH (rw) */
|
||||
} Ifx_MSC_ESR_Bits;
|
||||
|
||||
/** \brief Emergency Stop Extension Register */
|
||||
typedef struct _Ifx_MSC_ESRE_Bits
|
||||
{
|
||||
unsigned int ENL16:1; /**< \brief [0:0] Emergency Stop Enable for Bit 16 in SRL (rw) */
|
||||
unsigned int ENL17:1; /**< \brief [1:1] Emergency Stop Enable for Bit 17 in SRL (rw) */
|
||||
unsigned int ENL18:1; /**< \brief [2:2] Emergency Stop Enable for Bit 18 in SRL (rw) */
|
||||
unsigned int ENL19:1; /**< \brief [3:3] Emergency Stop Enable for Bit 19 in SRL (rw) */
|
||||
unsigned int ENL20:1; /**< \brief [4:4] Emergency Stop Enable for Bit 20 in SRL (rw) */
|
||||
unsigned int ENL21:1; /**< \brief [5:5] Emergency Stop Enable for Bit 21 in SRL (rw) */
|
||||
unsigned int ENL22:1; /**< \brief [6:6] Emergency Stop Enable for Bit 22 in SRL (rw) */
|
||||
unsigned int ENL23:1; /**< \brief [7:7] Emergency Stop Enable for Bit 23 in SRL (rw) */
|
||||
unsigned int ENL24:1; /**< \brief [8:8] Emergency Stop Enable for Bit 24 in SRL (rw) */
|
||||
unsigned int ENL25:1; /**< \brief [9:9] Emergency Stop Enable for Bit 25 in SRL (rw) */
|
||||
unsigned int ENL26:1; /**< \brief [10:10] Emergency Stop Enable for Bit 26 in SRL (rw) */
|
||||
unsigned int ENL27:1; /**< \brief [11:11] Emergency Stop Enable for Bit 27 in SRL (rw) */
|
||||
unsigned int ENL28:1; /**< \brief [12:12] Emergency Stop Enable for Bit 28 in SRL (rw) */
|
||||
unsigned int ENL29:1; /**< \brief [13:13] Emergency Stop Enable for Bit 29 in SRL (rw) */
|
||||
unsigned int ENL30:1; /**< \brief [14:14] Emergency Stop Enable for Bit 30 in SRL (rw) */
|
||||
unsigned int ENL31:1; /**< \brief [15:15] Emergency Stop Enable for Bit 31 in SRL (rw) */
|
||||
unsigned int ENH16:1; /**< \brief [16:16] Emergency Stop Enable for Bit 16 in SRH (rw) */
|
||||
unsigned int ENH17:1; /**< \brief [17:17] Emergency Stop Enable for Bit 17 in SRH (rw) */
|
||||
unsigned int ENH18:1; /**< \brief [18:18] Emergency Stop Enable for Bit 18 in SRH (rw) */
|
||||
unsigned int ENH19:1; /**< \brief [19:19] Emergency Stop Enable for Bit 19 in SRH (rw) */
|
||||
unsigned int ENH20:1; /**< \brief [20:20] Emergency Stop Enable for Bit 20 in SRH (rw) */
|
||||
unsigned int ENH21:1; /**< \brief [21:21] Emergency Stop Enable for Bit 21 in SRH (rw) */
|
||||
unsigned int ENH22:1; /**< \brief [22:22] Emergency Stop Enable for Bit 22 in SRH (rw) */
|
||||
unsigned int ENH23:1; /**< \brief [23:23] Emergency Stop Enable for Bit 23 in SRH (rw) */
|
||||
unsigned int ENH24:1; /**< \brief [24:24] Emergency Stop Enable for Bit 24 in SRH (rw) */
|
||||
unsigned int ENH25:1; /**< \brief [25:25] Emergency Stop Enable for Bit 25 in SRH (rw) */
|
||||
unsigned int ENH26:1; /**< \brief [26:26] Emergency Stop Enable for Bit 26 in SRH (rw) */
|
||||
unsigned int ENH27:1; /**< \brief [27:27] Emergency Stop Enable for Bit 27 in SRH (rw) */
|
||||
unsigned int ENH28:1; /**< \brief [28:28] Emergency Stop Enable for Bit 28 in SRH (rw) */
|
||||
unsigned int ENH29:1; /**< \brief [29:29] Emergency Stop Enable for Bit 29 in SRH (rw) */
|
||||
unsigned int ENH30:1; /**< \brief [30:30] Emergency Stop Enable for Bit 30 in SRH (rw) */
|
||||
unsigned int ENH31:1; /**< \brief [31:31] Emergency Stop Enable for Bit 31 in SRH (rw) */
|
||||
} Ifx_MSC_ESRE_Bits;
|
||||
|
||||
/** \brief Fractional Divider Register */
|
||||
typedef struct _Ifx_MSC_FDR_Bits
|
||||
{
|
||||
unsigned int STEP:10; /**< \brief [9:0] Step Value (rw) */
|
||||
unsigned int reserved_10:4; /**< \brief \internal Reserved */
|
||||
unsigned int DM:2; /**< \brief [15:14] Divider Mode (rw) */
|
||||
unsigned int RESULT:10; /**< \brief [25:16] Result Value (rh) */
|
||||
unsigned int reserved_26:4; /**< \brief \internal Reserved */
|
||||
unsigned int ENHW:1; /**< \brief [30:30] Enable Hardware Clock Control (rw) */
|
||||
unsigned int DISCLK:1; /**< \brief [31:31] Disable Clock (rwh) */
|
||||
} Ifx_MSC_FDR_Bits;
|
||||
|
||||
/** \brief Interrupt Control Register */
|
||||
typedef struct _Ifx_MSC_ICR_Bits
|
||||
{
|
||||
unsigned int EDIP:2; /**< \brief [1:0] Data Frame Interrupt Node Pointer (rw) */
|
||||
unsigned int EDIE:2; /**< \brief [3:2] Data Frame Interrupt Enable (rw) */
|
||||
unsigned int ECIP:2; /**< \brief [5:4] Command Frame Interrupt Node Pointer (rw) */
|
||||
unsigned int reserved_6:1; /**< \brief \internal Reserved */
|
||||
unsigned int ECIE:1; /**< \brief [7:7] Command Frame Interrupt Enable (rw) */
|
||||
unsigned int TFIP:2; /**< \brief [9:8] Time Frame Interrupt Pointer (rw) */
|
||||
unsigned int reserved_10:1; /**< \brief \internal Reserved */
|
||||
unsigned int TFIE:1; /**< \brief [11:11] Time Frame Interrupt Enable (rw) */
|
||||
unsigned int RDIP:2; /**< \brief [13:12] Receive Data Interrupt Pointer (rw) */
|
||||
unsigned int RDIE:2; /**< \brief [15:14] Receive Data Interrupt Enable (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_ICR_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_MSC_ID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_MSC_ID_Bits;
|
||||
|
||||
/** \brief Interrupt Set Clear Register */
|
||||
typedef struct _Ifx_MSC_ISC_Bits
|
||||
{
|
||||
unsigned int CDEDI:1; /**< \brief [0:0] Clear DEDI Flag (w) */
|
||||
unsigned int CDECI:1; /**< \brief [1:1] Clear DECI Flag (w) */
|
||||
unsigned int CDTFI:1; /**< \brief [2:2] Clear DTFI Flag (w) */
|
||||
unsigned int CURDI:1; /**< \brief [3:3] Clear URDI Flag (w) */
|
||||
unsigned int CDP:1; /**< \brief [4:4] Clear DP Flag (w) */
|
||||
unsigned int CCP:1; /**< \brief [5:5] Clear CP Flag (w) */
|
||||
unsigned int CDDIS:1; /**< \brief [6:6] Clear DSDIS Flag (w) */
|
||||
unsigned int reserved_7:9; /**< \brief \internal Reserved */
|
||||
unsigned int SDEDI:1; /**< \brief [16:16] Set DEDI Flag (w) */
|
||||
unsigned int SDECI:1; /**< \brief [17:17] Set DECI Flag (w) */
|
||||
unsigned int SDTFI:1; /**< \brief [18:18] Set DTFI Flag (w) */
|
||||
unsigned int SURDI:1; /**< \brief [19:19] Set URDI Flag (w) */
|
||||
unsigned int SDP:1; /**< \brief [20:20] Set DP Bit (w) */
|
||||
unsigned int SCP:1; /**< \brief [21:21] Set CP Flag (w) */
|
||||
unsigned int SDDIS:1; /**< \brief [22:22] Set DSDIS Flag (w) */
|
||||
unsigned int reserved_23:9; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_ISC_Bits;
|
||||
|
||||
/** \brief Interrupt Status Register */
|
||||
typedef struct _Ifx_MSC_ISR_Bits
|
||||
{
|
||||
unsigned int DEDI:1; /**< \brief [0:0] Data Frame Interrupt Flag (rh) */
|
||||
unsigned int DECI:1; /**< \brief [1:1] Command Frame Interrupt Flag (rh) */
|
||||
unsigned int DTFI:1; /**< \brief [2:2] Time Frame Interrupt Flag (rh) */
|
||||
unsigned int URDI:1; /**< \brief [3:3] Receive Data Interrupt Flag (rh) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_ISR_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef struct _Ifx_MSC_KRST0_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_KRST0_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef struct _Ifx_MSC_KRST1_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_KRST1_Bits;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef struct _Ifx_MSC_KRSTCLR_Bits
|
||||
{
|
||||
unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_KRSTCLR_Bits;
|
||||
|
||||
/** \brief Output Control Register */
|
||||
typedef struct _Ifx_MSC_OCR_Bits
|
||||
{
|
||||
unsigned int CLP:1; /**< \brief [0:0] FCLP Line Polarity (rw) */
|
||||
unsigned int SLP:1; /**< \brief [1:1] SOP Line Polarity (rw) */
|
||||
unsigned int CSLP:1; /**< \brief [2:2] Chip Selection Lines Polarity (rw) */
|
||||
unsigned int ILP:1; /**< \brief [3:3] SDI Line Polarity (rw) */
|
||||
unsigned int reserved_4:4; /**< \brief \internal Reserved */
|
||||
unsigned int CLKCTRL:1; /**< \brief [8:8] Clock Control (rw) */
|
||||
unsigned int CSL:2; /**< \brief [10:9] Chip Enable Selection for ENL (rw) */
|
||||
unsigned int CSH:2; /**< \brief [12:11] Chip Enable Selection for ENH (rw) */
|
||||
unsigned int CSC:2; /**< \brief [14:13] Chip Enable Selection for ENC (rw) */
|
||||
unsigned int reserved_15:1; /**< \brief \internal Reserved */
|
||||
unsigned int SDISEL:3; /**< \brief [18:16] Serial Data Input Selection (rw) */
|
||||
unsigned int reserved_19:13; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_OCR_Bits;
|
||||
|
||||
/** \brief OCDS Control and Status */
|
||||
typedef struct _Ifx_MSC_OCS_Bits
|
||||
{
|
||||
unsigned int reserved_0:24; /**< \brief \internal Reserved */
|
||||
unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
|
||||
unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
|
||||
unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
|
||||
unsigned int reserved_30:2; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_OCS_Bits;
|
||||
|
||||
/** \brief Upstream Data Register */
|
||||
typedef struct _Ifx_MSC_UD_Bits
|
||||
{
|
||||
unsigned int DATA:8; /**< \brief [7:0] Received Data (rh) */
|
||||
unsigned int reserved_8:8; /**< \brief \internal Reserved */
|
||||
unsigned int V:1; /**< \brief [16:16] Valid Bit (rh) */
|
||||
unsigned int P:1; /**< \brief [17:17] Parity Bit (rh) */
|
||||
unsigned int C:1; /**< \brief [18:18] Clear Bit (w) */
|
||||
unsigned int LABF:2; /**< \brief [20:19] Lower Address Bit Field (rh) */
|
||||
unsigned int IPF:1; /**< \brief [21:21] Internal Parity Flag (rh) */
|
||||
unsigned int PERR:1; /**< \brief [22:22] Parity Error (rh) */
|
||||
unsigned int reserved_23:9; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_UD_Bits;
|
||||
|
||||
/** \brief Upstream Control Enhanced Register 1 */
|
||||
typedef struct _Ifx_MSC_USCE_Bits
|
||||
{
|
||||
unsigned int USTOPRE:4; /**< \brief [3:0] Upstream Timeout Prescaler (rw) */
|
||||
unsigned int USTOVAL:4; /**< \brief [7:4] Upstream Timeout Value (rw) */
|
||||
unsigned int USTOEN:1; /**< \brief [8:8] Upstream Timeout Interrupt Enable (rw) */
|
||||
unsigned int USTF:1; /**< \brief [9:9] Upstream Timeout Flag (rh) */
|
||||
unsigned int USTC:1; /**< \brief [10:10] Upstream Timout Clear (w) */
|
||||
unsigned int USTS:1; /**< \brief [11:11] Upstream Timout Set (w) */
|
||||
unsigned int reserved_12:1; /**< \brief \internal Reserved */
|
||||
unsigned int UTASR:1; /**< \brief [13:13] Upstream Timout Alternate Service Request (rw) */
|
||||
unsigned int USTOIP:2; /**< \brief [15:14] Upstream Timout Interrupt Node Pointer (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_USCE_Bits;
|
||||
|
||||
/** \brief Upstream Status Register */
|
||||
typedef struct _Ifx_MSC_USR_Bits
|
||||
{
|
||||
unsigned int UFT:1; /**< \brief [0:0] Upstream Channel Frame Type (rw) */
|
||||
unsigned int URR:3; /**< \brief [3:1] Upstream Channel Receiving Rate (rw) */
|
||||
unsigned int PCTR:1; /**< \brief [4:4] Parity Control (rw) */
|
||||
unsigned int SRDC:1; /**< \brief [5:5] Service Request Delay Control (rw) */
|
||||
unsigned int reserved_6:10; /**< \brief \internal Reserved */
|
||||
unsigned int UC:5; /**< \brief [20:16] Upstream Counter (rh) */
|
||||
unsigned int reserved_21:11; /**< \brief \internal Reserved */
|
||||
} Ifx_MSC_USR_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Msc_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Asynchronous Block Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_ABC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_ABC;
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_ACCEN0;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_ACCEN1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_ACCEN1;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_CLC;
|
||||
|
||||
/** \brief Downstream Command Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_DC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_DC;
|
||||
|
||||
/** \brief Downstream Data Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_DD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_DD;
|
||||
|
||||
/** \brief Downstream Data Extension Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_DDE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_DDE;
|
||||
|
||||
/** \brief Downstream Data Mirror Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_DDM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_DDM;
|
||||
|
||||
/** \brief Downstream Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_DSC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_DSC;
|
||||
|
||||
/** \brief Downstream Control Enhanced Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_DSCE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_DSCE;
|
||||
|
||||
/** \brief Downstream Select Data Source High Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_DSDSH_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_DSDSH;
|
||||
|
||||
/** \brief Downstream Select Data Source High Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_DSDSHE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_DSDSHE;
|
||||
|
||||
/** \brief Downstream Select Data Source Low Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_DSDSL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_DSDSL;
|
||||
|
||||
/** \brief Downstream Select Data Source Low Extension Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_DSDSLE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_DSDSLE;
|
||||
|
||||
/** \brief Downstream Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_DSS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_DSS;
|
||||
|
||||
/** \brief Downstream Timing Extension Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_DSTE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_DSTE;
|
||||
|
||||
/** \brief Emergency Stop Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_ESR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_ESR;
|
||||
|
||||
/** \brief Emergency Stop Extension Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_ESRE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_ESRE;
|
||||
|
||||
/** \brief Fractional Divider Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_FDR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_FDR;
|
||||
|
||||
/** \brief Interrupt Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_ICR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_ICR;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_ID;
|
||||
|
||||
/** \brief Interrupt Set Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_ISC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_ISC;
|
||||
|
||||
/** \brief Interrupt Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_ISR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_ISR;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_KRST0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_KRST0;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_KRST1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_KRST1;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_KRSTCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_KRSTCLR;
|
||||
|
||||
/** \brief Output Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_OCR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_OCR;
|
||||
|
||||
/** \brief OCDS Control and Status */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_OCS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_OCS;
|
||||
|
||||
/** \brief Upstream Data Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_UD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_UD;
|
||||
|
||||
/** \brief Upstream Control Enhanced Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_USCE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_USCE;
|
||||
|
||||
/** \brief Upstream Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MSC_USR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MSC_USR;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Msc_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief MSC object */
|
||||
typedef volatile struct _Ifx_MSC
|
||||
{
|
||||
Ifx_MSC_CLC CLC; /**< \brief 0, Clock Control Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_MSC_ID ID; /**< \brief 8, Module Identification Register */
|
||||
Ifx_MSC_FDR FDR; /**< \brief C, Fractional Divider Register */
|
||||
Ifx_MSC_USR USR; /**< \brief 10, Upstream Status Register */
|
||||
Ifx_MSC_DSC DSC; /**< \brief 14, Downstream Control Register */
|
||||
Ifx_MSC_DSS DSS; /**< \brief 18, Downstream Status Register */
|
||||
Ifx_MSC_DD DD; /**< \brief 1C, Downstream Data Register */
|
||||
Ifx_MSC_DC DC; /**< \brief 20, Downstream Command Register */
|
||||
Ifx_MSC_DSDSL DSDSL; /**< \brief 24, Downstream Select Data Source Low Register */
|
||||
Ifx_MSC_DSDSH DSDSH; /**< \brief 28, Downstream Select Data Source High Register */
|
||||
Ifx_MSC_ESR ESR; /**< \brief 2C, Emergency Stop Register */
|
||||
Ifx_MSC_UD UD[4]; /**< \brief 30, Upstream Data Register */
|
||||
Ifx_MSC_ICR ICR; /**< \brief 40, Interrupt Control Register */
|
||||
Ifx_MSC_ISR ISR; /**< \brief 44, Interrupt Status Register */
|
||||
Ifx_MSC_ISC ISC; /**< \brief 48, Interrupt Set Clear Register */
|
||||
Ifx_MSC_OCR OCR; /**< \brief 4C, Output Control Register */
|
||||
unsigned char reserved_50[8]; /**< \brief 50, \internal Reserved */
|
||||
Ifx_MSC_DSCE DSCE; /**< \brief 58, Downstream Control Enhanced Register 1 */
|
||||
Ifx_MSC_USCE USCE; /**< \brief 5C, Upstream Control Enhanced Register 1 */
|
||||
Ifx_MSC_DSDSLE DSDSLE; /**< \brief 60, Downstream Select Data Source Low Extension Register */
|
||||
Ifx_MSC_DSDSHE DSDSHE; /**< \brief 64, Downstream Select Data Source High Register */
|
||||
Ifx_MSC_ESRE ESRE; /**< \brief 68, Emergency Stop Extension Register */
|
||||
Ifx_MSC_DDE DDE; /**< \brief 6C, Downstream Data Extension Register */
|
||||
Ifx_MSC_DDM DDM; /**< \brief 70, Downstream Data Mirror Register */
|
||||
Ifx_MSC_DSTE DSTE; /**< \brief 74, Downstream Timing Extension Register */
|
||||
unsigned char reserved_78[8]; /**< \brief 78, \internal Reserved */
|
||||
Ifx_MSC_ABC ABC; /**< \brief 80, Asynchronous Block Configuration Register */
|
||||
unsigned char reserved_84[100]; /**< \brief 84, \internal Reserved */
|
||||
Ifx_MSC_OCS OCS; /**< \brief E8, OCDS Control and Status */
|
||||
Ifx_MSC_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
|
||||
Ifx_MSC_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
|
||||
Ifx_MSC_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
|
||||
Ifx_MSC_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
|
||||
Ifx_MSC_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
|
||||
} Ifx_MSC;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXMSC_REGDEF_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,84 +0,0 @@
|
||||
/**
|
||||
* \file IfxMtu_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Mtu_Cfg Mtu address
|
||||
* \ingroup IfxLld_Mtu
|
||||
*
|
||||
* \defgroup IfxLld_Mtu_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Mtu_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Mtu_Cfg_Mtu 2-MTU
|
||||
* \ingroup IfxLld_Mtu_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXMTU_REG_H
|
||||
#define IFXMTU_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxMtu_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Mtu_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief MTU object */
|
||||
#define MODULE_MTU /*lint --e(923)*/ (*(Ifx_MTU*)0xF0060000u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Mtu_Cfg_Mtu
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define MTU_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_MTU_ACCEN0*)0xF00600FCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define MTU_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_MTU_ACCEN1*)0xF00600F8u)
|
||||
|
||||
/** \brief 0, Identification Register */
|
||||
#define MTU_CLC /*lint --e(923)*/ (*(volatile Ifx_MTU_CLC*)0xF0060000u)
|
||||
|
||||
/** \brief 8, Identification Register */
|
||||
#define MTU_ID /*lint --e(923)*/ (*(volatile Ifx_MTU_ID*)0xF0060008u)
|
||||
|
||||
/** \brief 1C, Memory Mapping Enable Register */
|
||||
#define MTU_MEMMAP /*lint --e(923)*/ (*(volatile Ifx_MTU_MEMMAP*)0xF006001Cu)
|
||||
|
||||
/** \brief 38, Memory Status Register 0 */
|
||||
#define MTU_MEMSTAT0 /*lint --e(923)*/ (*(volatile Ifx_MTU_MEMSTAT0*)0xF0060038u)
|
||||
|
||||
/** \brief 3C, Memory Status Register 1 */
|
||||
#define MTU_MEMSTAT1 /*lint --e(923)*/ (*(volatile Ifx_MTU_MEMSTAT1*)0xF006003Cu)
|
||||
|
||||
/** \brief 40, Memory Status Register 2 */
|
||||
#define MTU_MEMSTAT2 /*lint --e(923)*/ (*(volatile Ifx_MTU_MEMSTAT2*)0xF0060040u)
|
||||
|
||||
/** \brief 10, Memory MBISTEnable Register 0 */
|
||||
#define MTU_MEMTEST0 /*lint --e(923)*/ (*(volatile Ifx_MTU_MEMTEST0*)0xF0060010u)
|
||||
|
||||
/** \brief 14, Memory MBISTEnable Register 1 */
|
||||
#define MTU_MEMTEST1 /*lint --e(923)*/ (*(volatile Ifx_MTU_MEMTEST1*)0xF0060014u)
|
||||
|
||||
/** \brief 18, Memory MBISTEnable Register 2 */
|
||||
#define MTU_MEMTEST2 /*lint --e(923)*/ (*(volatile Ifx_MTU_MEMTEST2*)0xF0060018u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXMTU_REG_H */
|
||||
@@ -1,370 +0,0 @@
|
||||
/**
|
||||
* \file IfxMtu_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Mtu Mtu
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Mtu_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Mtu
|
||||
*
|
||||
* \defgroup IfxLld_Mtu_union Union
|
||||
* \ingroup IfxLld_Mtu
|
||||
*
|
||||
* \defgroup IfxLld_Mtu_struct Struct
|
||||
* \ingroup IfxLld_Mtu
|
||||
*
|
||||
*/
|
||||
#ifndef IFXMTU_REGDEF_H
|
||||
#define IFXMTU_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Mtu_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_MTU_ACCEN0_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_MTU_ACCEN0_Bits;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef struct _Ifx_MTU_ACCEN1_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_MTU_ACCEN1_Bits;
|
||||
|
||||
/** \brief Identification Register */
|
||||
typedef struct _Ifx_MTU_CLC_Bits
|
||||
{
|
||||
unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
|
||||
unsigned int Resvd:1; /**< \brief [2:2] Resvd (rw) */
|
||||
unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_MTU_CLC_Bits;
|
||||
|
||||
/** \brief Identification Register */
|
||||
typedef struct _Ifx_MTU_ID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_MTU_ID_Bits;
|
||||
|
||||
/** \brief Memory Mapping Enable Register */
|
||||
typedef struct _Ifx_MTU_MEMMAP_Bits
|
||||
{
|
||||
unsigned int reserved_0:1; /**< \brief \internal Reserved */
|
||||
unsigned int CPU2DxMAP:2; /**< \brief [2:1] Reserved in this product (r) */
|
||||
unsigned int reserved_3:1; /**< \brief \internal Reserved */
|
||||
unsigned int CPU2PxMAP:2; /**< \brief [5:4] Reserved in this product (r) */
|
||||
unsigned int reserved_6:1; /**< \brief \internal Reserved */
|
||||
unsigned int CPU1DCMAP:1; /**< \brief [7:7] CPU1 DCACHE Mapping (rwh) */
|
||||
unsigned int CPU1DTMAP:1; /**< \brief [8:8] CPU1 DTAG Mapping (rh) */
|
||||
unsigned int reserved_9:1; /**< \brief \internal Reserved */
|
||||
unsigned int CPU1PCMAP:1; /**< \brief [10:10] CPU1 PCACHE Mapping (rwh) */
|
||||
unsigned int CPU1PTMAP:1; /**< \brief [11:11] CPU1 PTAG Mapping (rh) */
|
||||
unsigned int reserved_12:3; /**< \brief \internal Reserved */
|
||||
unsigned int CPU0PCMAP:1; /**< \brief [15:15] CPU0 PCACHE Mapping (rwh) */
|
||||
unsigned int reserved_16:1; /**< \brief \internal Reserved */
|
||||
unsigned int CPU0PTMAP:1; /**< \brief [17:17] CPU0 PTAG Mapping (rh) */
|
||||
unsigned int CPU0DxMAP:2; /**< \brief [19:18] Reserved in this product (r) */
|
||||
unsigned int reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_MTU_MEMMAP_Bits;
|
||||
|
||||
/** \brief Memory Status Register 0 */
|
||||
typedef struct _Ifx_MTU_MEMSTAT0_Bits
|
||||
{
|
||||
unsigned int CPU2DSAIU:1; /**< \brief [0:0] Reserved in this product (r) */
|
||||
unsigned int reserved_1:1; /**< \brief \internal Reserved */
|
||||
unsigned int CPU2DTAIU:1; /**< \brief [2:2] Reserved in this product (r) */
|
||||
unsigned int CPU2PSAIU:1; /**< \brief [3:3] Reserved in this product (r) */
|
||||
unsigned int reserved_4:1; /**< \brief \internal Reserved */
|
||||
unsigned int CPU2PTAIU:1; /**< \brief [5:5] Reserved in this product (r) */
|
||||
unsigned int CPU1DSAIU:1; /**< \brief [6:6] CPU1 DCACHE Partial AutoInitialize Underway (rh) */
|
||||
unsigned int reserved_7:1; /**< \brief \internal Reserved */
|
||||
unsigned int CPU1DTAIU:1; /**< \brief [8:8] CPU1 DTAG MBIST AutoInitialize Underway (rh) */
|
||||
unsigned int CPU1PSAIU:1; /**< \brief [9:9] CPU1 PCACHE Partial AutoInitialize Underway (rh) */
|
||||
unsigned int reserved_10:1; /**< \brief \internal Reserved */
|
||||
unsigned int CPU1PTAIU:1; /**< \brief [11:11] CPU1 PTAG MBIST AutoInitialize Underway (rh) */
|
||||
unsigned int reserved_12:2; /**< \brief \internal Reserved */
|
||||
unsigned int CPU0DSAIU:1; /**< \brief [14:14] Reserved in this product (r) */
|
||||
unsigned int reserved_15:1; /**< \brief \internal Reserved */
|
||||
unsigned int CPU0PSAIU:1; /**< \brief [16:16] CPU0 PCACHE Partial AutoInitialize Underway (rh) */
|
||||
unsigned int CPU0PTAIU:1; /**< \brief [17:17] CPU0 PTAG MBIST AutoInitialize Underway (rh) */
|
||||
unsigned int reserved_18:1; /**< \brief \internal Reserved */
|
||||
unsigned int CPU0DxAIU:1; /**< \brief [19:19] Reserved in this product (r) */
|
||||
unsigned int CPU1DS2AIU:1; /**< \brief [20:20] Reserved in this product (r) */
|
||||
unsigned int CPU2DS2AIU:1; /**< \brief [21:21] Reserved in this product (r) */
|
||||
unsigned int reserved_22:1; /**< \brief \internal Reserved */
|
||||
unsigned int HSMCAIU:1; /**< \brief [23:23] Reserved in this product (r) */
|
||||
unsigned int HSMTAIU:1; /**< \brief [24:24] Reserved in this product (r) */
|
||||
unsigned int HSMRAIU:1; /**< \brief [25:25] Reserved in this product (r) */
|
||||
unsigned int FSI0AIU:1; /**< \brief [26:26] FSI0 MBIST AutoInitialize Underway (rh) */
|
||||
unsigned int CPU0DS2AIU:1; /**< \brief [27:27] Reserved in this product (r) */
|
||||
unsigned int reserved_28:4; /**< \brief \internal Reserved */
|
||||
} Ifx_MTU_MEMSTAT0_Bits;
|
||||
|
||||
/** \brief Memory Status Register 1 */
|
||||
typedef struct _Ifx_MTU_MEMSTAT1_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_MTU_MEMSTAT1_Bits;
|
||||
|
||||
/** \brief Memory Status Register 2 */
|
||||
typedef struct _Ifx_MTU_MEMSTAT2_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_MTU_MEMSTAT2_Bits;
|
||||
|
||||
/** \brief Memory MBISTEnable Register 0 */
|
||||
typedef struct _Ifx_MTU_MEMTEST0_Bits
|
||||
{
|
||||
unsigned int CPU2XEN:6; /**< \brief [5:0] Reserved in this product (r) */
|
||||
unsigned int CPU1DSEN:1; /**< \brief [6:6] CPU1 TC1.6P DSPR MBIST Controller Memory Enable (rwh) */
|
||||
unsigned int Res:1; /**< \brief [7:7] Reserved in this product (r) */
|
||||
unsigned int CPU1DTEN:1; /**< \brief [8:8] CPU1 TC1.6P DTAG MBIST Controller Memory Enable (rwh) */
|
||||
unsigned int CPU1PSEN:1; /**< \brief [9:9] CPU1 TC1.6P PSPR MBIST Controller Memory Enable (rwh) */
|
||||
unsigned int reserved_10:1; /**< \brief \internal Reserved */
|
||||
unsigned int CPU1PTEN:1; /**< \brief [11:11] CPU1 TC1.6P PTAG MBIST Controller Memory Enable (rwh) */
|
||||
unsigned int LMUEN:1; /**< \brief [12:12] Reserved in this product (r) */
|
||||
unsigned int MMCDSEN:1; /**< \brief [13:13] Reserved in this product (r) */
|
||||
unsigned int CPU0DSEN:1; /**< \brief [14:14] CPU0 DSPR MBIST Controller Memory Enable (rwh) */
|
||||
unsigned int reserved_15:1; /**< \brief \internal Reserved */
|
||||
unsigned int CPU0PSEN:1; /**< \brief [16:16] CPU0 PSPR MBIST Controller Memory Enable (rwh) */
|
||||
unsigned int CPU0PTEN:1; /**< \brief [17:17] CPU0 PTAG MBIST Controller Memory Enable (rwh) */
|
||||
unsigned int reserved_18:1; /**< \brief \internal Reserved */
|
||||
unsigned int CPU0DTEN:1; /**< \brief [19:19] Reserved in this product (r) */
|
||||
unsigned int CPUXDS2EN:2; /**< \brief [21:20] Reserved in this product (r) */
|
||||
unsigned int ETHEN:1; /**< \brief [22:22] ETHERMAC MBIST Controller Memory Enable (rwh) */
|
||||
unsigned int reserved_23:3; /**< \brief \internal Reserved */
|
||||
unsigned int FSI0EN:1; /**< \brief [26:26] FSI0 MBIST Controller Memory Enable (rwh) */
|
||||
unsigned int CPU0DS2EN:1; /**< \brief [27:27] Reserved in this product (r) */
|
||||
unsigned int GTMFEN:1; /**< \brief [28:28] GTM FIFO0 MBIST Controller Memory Enable (rwh) */
|
||||
unsigned int GTMM0EN:1; /**< \brief [29:29] GTM MCS0 MBIST Controller Memory Enable (rwh) */
|
||||
unsigned int GTMM1EN:1; /**< \brief [30:30] GTM RAM1 MBIST Controller Memory Enable (rwh) */
|
||||
unsigned int GTM1AEN:1; /**< \brief [31:31] GTM RAM1A MBIST Controller Memory Enable (rwh) */
|
||||
} Ifx_MTU_MEMTEST0_Bits;
|
||||
|
||||
/** \brief Memory MBISTEnable Register 1 */
|
||||
typedef struct _Ifx_MTU_MEMTEST1_Bits
|
||||
{
|
||||
unsigned int GTM1BEN:1; /**< \brief [0:0] GTM RAM1B Controller Memory Enable (rwh) */
|
||||
unsigned int GTM2EN:1; /**< \brief [1:1] GTM RAM2 Controller Memory Enable (rwh) */
|
||||
unsigned int PSI5EN:1; /**< \brief [2:2] PSI5 Controller Memory Enable (rwh) */
|
||||
unsigned int reserved_3:1; /**< \brief \internal Reserved */
|
||||
unsigned int MCAN0EN:1; /**< \brief [4:4] MultiCAN0 Controller Memory Enable (rwh) */
|
||||
unsigned int MCAN1EN:1; /**< \brief [5:5] Reserved in this product (r) */
|
||||
unsigned int ERAY0OEN:1; /**< \brief [6:6] ERAY0 OBF Controller Memory Enable (rwh) */
|
||||
unsigned int ERAY0TEN:1; /**< \brief [7:7] ERAY0 TBF Controller Memory Enable (rwh) */
|
||||
unsigned int ERAY0MEN:1; /**< \brief [8:8] ERAY0 MBF Controller Memory Enable (rwh) */
|
||||
unsigned int ERAY1XEN:3; /**< \brief [11:9] Reserved in this product (r) */
|
||||
unsigned int STBY1EN:1; /**< \brief [12:12] 8 Bit Standby RAM Controller Memory 1 Enable (rwh) */
|
||||
unsigned int MCDSEN:1; /**< \brief [13:13] MCDS Controller Memory Enable (ED only) (rwh) */
|
||||
unsigned int EMEML0EN:1; /**< \brief [14:14] EMEM Lower 0 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
|
||||
unsigned int EMEML1EN:1; /**< \brief [15:15] EMEM Lower 1 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
|
||||
unsigned int EMEML2EN:1; /**< \brief [16:16] EMEM Lower 2 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
|
||||
unsigned int EMEML3EN:1; /**< \brief [17:17] EMEM Lower 3 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
|
||||
unsigned int EMEML4EN:1; /**< \brief [18:18] EMEM Lower 4 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
|
||||
unsigned int EMEML5EN:1; /**< \brief [19:19] EMEM Lower 5 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
|
||||
unsigned int EMEML6EN:1; /**< \brief [20:20] EMEM Lower 6 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
|
||||
unsigned int EMEML7EN:1; /**< \brief [21:21] EMEM Lower 7 (TCM) MBIST Controller Memory Test Enable (ED only) (rwh) */
|
||||
unsigned int EMEMLXEN:8; /**< \brief [29:22] Reserved in this product (r) */
|
||||
unsigned int EMEMUXEN:2; /**< \brief [31:30] Reserved in this product (r) */
|
||||
} Ifx_MTU_MEMTEST1_Bits;
|
||||
|
||||
/** \brief Memory MBISTEnable Register 2 */
|
||||
typedef struct _Ifx_MTU_MEMTEST2_Bits
|
||||
{
|
||||
unsigned int EMEMUxEN:14; /**< \brief [13:0] Reserved in this product (r) */
|
||||
unsigned int CIF0EN:1; /**< \brief [14:14] CIF JPEG1_4 Memory Enable (ED only) (rwh) */
|
||||
unsigned int DAMEN:1; /**< \brief [15:15] Reserved in this product (r) */
|
||||
unsigned int CIF1EN:1; /**< \brief [16:16] CIF JPEG3 Memory Enable (ADAS Product only) (rwh) */
|
||||
unsigned int CIF2EN:1; /**< \brief [17:17] CIF Memory2 Enable (ADAS Product only) (rwh) */
|
||||
unsigned int STBY2EN:1; /**< \brief [18:18] 8-bit Standby Controller Memory2 Enable (rwh) */
|
||||
unsigned int DMAEN:1; /**< \brief [19:19] DMA MBIST Controller Memory Enable (rwh) */
|
||||
unsigned int XTM0EN:1; /**< \brief [20:20] EMEM XTM0 Controller Memory Enable (ED only) (rwh) */
|
||||
unsigned int XTM1EN:1; /**< \brief [21:21] EMEM XTM1 Controller Memory Enable (ED only) (rwh) */
|
||||
unsigned int FFT0EN:1; /**< \brief [22:22] FFT0 Memory Controller Memory Enable (ADAS Product only) (rwh) */
|
||||
unsigned int FFT1EN:1; /**< \brief [23:23] FFT1 Memory Controller Memory Enable (ADAS Product only) (rwh) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_MTU_MEMTEST2_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Mtu_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MTU_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MTU_ACCEN0;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MTU_ACCEN1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MTU_ACCEN1;
|
||||
|
||||
/** \brief Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MTU_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MTU_CLC;
|
||||
|
||||
/** \brief Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MTU_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MTU_ID;
|
||||
|
||||
/** \brief Memory Mapping Enable Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MTU_MEMMAP_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MTU_MEMMAP;
|
||||
|
||||
/** \brief Memory Status Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MTU_MEMSTAT0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MTU_MEMSTAT0;
|
||||
|
||||
/** \brief Memory Status Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MTU_MEMSTAT1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MTU_MEMSTAT1;
|
||||
|
||||
/** \brief Memory Status Register 2 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MTU_MEMSTAT2_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MTU_MEMSTAT2;
|
||||
|
||||
/** \brief Memory MBISTEnable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MTU_MEMTEST0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MTU_MEMTEST0;
|
||||
|
||||
/** \brief Memory MBISTEnable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MTU_MEMTEST1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MTU_MEMTEST1;
|
||||
|
||||
/** \brief Memory MBISTEnable Register 2 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_MTU_MEMTEST2_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_MTU_MEMTEST2;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Mtu_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief MTU object */
|
||||
typedef volatile struct _Ifx_MTU
|
||||
{
|
||||
Ifx_MTU_CLC CLC; /**< \brief 0, Identification Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_MTU_ID ID; /**< \brief 8, Identification Register */
|
||||
unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
|
||||
Ifx_MTU_MEMTEST0 MEMTEST0; /**< \brief 10, Memory MBISTEnable Register 0 */
|
||||
Ifx_MTU_MEMTEST1 MEMTEST1; /**< \brief 14, Memory MBISTEnable Register 1 */
|
||||
Ifx_MTU_MEMTEST2 MEMTEST2; /**< \brief 18, Memory MBISTEnable Register 2 */
|
||||
Ifx_MTU_MEMMAP MEMMAP; /**< \brief 1C, Memory Mapping Enable Register */
|
||||
unsigned char reserved_20[24]; /**< \brief 20, \internal Reserved */
|
||||
Ifx_MTU_MEMSTAT0 MEMSTAT0; /**< \brief 38, Memory Status Register 0 */
|
||||
Ifx_MTU_MEMSTAT1 MEMSTAT1; /**< \brief 3C, Memory Status Register 1 */
|
||||
Ifx_MTU_MEMSTAT2 MEMSTAT2; /**< \brief 40, Memory Status Register 2 */
|
||||
unsigned char reserved_44[180]; /**< \brief 44, \internal Reserved */
|
||||
Ifx_MTU_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
|
||||
Ifx_MTU_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
|
||||
unsigned char reserved_100[1]; /**< \brief 100, \internal Reserved */
|
||||
} Ifx_MTU;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXMTU_REGDEF_H */
|
||||
@@ -1,378 +0,0 @@
|
||||
/**
|
||||
* \file IfxOvc_bf.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Ovc_BitfieldsMask Bitfields mask and offset
|
||||
* \ingroup IfxLld_Ovc
|
||||
*
|
||||
*/
|
||||
#ifndef IFXOVC_BF_H
|
||||
#define IFXOVC_BF_H 1
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ovc_BitfieldsMask
|
||||
* \{ */
|
||||
|
||||
/** \brief Length for Ifx_OVC_BLK_OMASK_Bits.OMASK */
|
||||
#define IFX_OVC_BLK_OMASK_OMASK_LEN (12u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_BLK_OMASK_Bits.OMASK */
|
||||
#define IFX_OVC_BLK_OMASK_OMASK_MSK (0xfffu)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_BLK_OMASK_Bits.OMASK */
|
||||
#define IFX_OVC_BLK_OMASK_OMASK_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_BLK_OMASK_Bits.ONE */
|
||||
#define IFX_OVC_BLK_OMASK_ONE_LEN (11u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_BLK_OMASK_Bits.ONE */
|
||||
#define IFX_OVC_BLK_OMASK_ONE_MSK (0x7ffu)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_BLK_OMASK_Bits.ONE */
|
||||
#define IFX_OVC_BLK_OMASK_ONE_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_BLK_OTAR_Bits.TBASE */
|
||||
#define IFX_OVC_BLK_OTAR_TBASE_LEN (23u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_BLK_OTAR_Bits.TBASE */
|
||||
#define IFX_OVC_BLK_OTAR_TBASE_MSK (0x7fffffu)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_BLK_OTAR_Bits.TBASE */
|
||||
#define IFX_OVC_BLK_OTAR_TBASE_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_BLK_RABR_Bits.OBASE */
|
||||
#define IFX_OVC_BLK_RABR_OBASE_LEN (17u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_BLK_RABR_Bits.OBASE */
|
||||
#define IFX_OVC_BLK_RABR_OBASE_MSK (0x1ffffu)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_BLK_RABR_Bits.OBASE */
|
||||
#define IFX_OVC_BLK_RABR_OBASE_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_BLK_RABR_Bits.OMEM */
|
||||
#define IFX_OVC_BLK_RABR_OMEM_LEN (3u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_BLK_RABR_Bits.OMEM */
|
||||
#define IFX_OVC_BLK_RABR_OMEM_MSK (0x7u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_BLK_RABR_Bits.OMEM */
|
||||
#define IFX_OVC_BLK_RABR_OMEM_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_BLK_RABR_Bits.OVEN */
|
||||
#define IFX_OVC_BLK_RABR_OVEN_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_BLK_RABR_Bits.OVEN */
|
||||
#define IFX_OVC_BLK_RABR_OVEN_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_BLK_RABR_Bits.OVEN */
|
||||
#define IFX_OVC_BLK_RABR_OVEN_OFF (31u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN0 */
|
||||
#define IFX_OVC_OSEL_SHOVEN0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN0 */
|
||||
#define IFX_OVC_OSEL_SHOVEN0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN0 */
|
||||
#define IFX_OVC_OSEL_SHOVEN0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN10 */
|
||||
#define IFX_OVC_OSEL_SHOVEN10_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN10 */
|
||||
#define IFX_OVC_OSEL_SHOVEN10_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN10 */
|
||||
#define IFX_OVC_OSEL_SHOVEN10_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN11 */
|
||||
#define IFX_OVC_OSEL_SHOVEN11_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN11 */
|
||||
#define IFX_OVC_OSEL_SHOVEN11_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN11 */
|
||||
#define IFX_OVC_OSEL_SHOVEN11_OFF (11u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN12 */
|
||||
#define IFX_OVC_OSEL_SHOVEN12_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN12 */
|
||||
#define IFX_OVC_OSEL_SHOVEN12_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN12 */
|
||||
#define IFX_OVC_OSEL_SHOVEN12_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN13 */
|
||||
#define IFX_OVC_OSEL_SHOVEN13_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN13 */
|
||||
#define IFX_OVC_OSEL_SHOVEN13_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN13 */
|
||||
#define IFX_OVC_OSEL_SHOVEN13_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN14 */
|
||||
#define IFX_OVC_OSEL_SHOVEN14_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN14 */
|
||||
#define IFX_OVC_OSEL_SHOVEN14_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN14 */
|
||||
#define IFX_OVC_OSEL_SHOVEN14_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN15 */
|
||||
#define IFX_OVC_OSEL_SHOVEN15_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN15 */
|
||||
#define IFX_OVC_OSEL_SHOVEN15_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN15 */
|
||||
#define IFX_OVC_OSEL_SHOVEN15_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN16 */
|
||||
#define IFX_OVC_OSEL_SHOVEN16_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN16 */
|
||||
#define IFX_OVC_OSEL_SHOVEN16_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN16 */
|
||||
#define IFX_OVC_OSEL_SHOVEN16_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN17 */
|
||||
#define IFX_OVC_OSEL_SHOVEN17_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN17 */
|
||||
#define IFX_OVC_OSEL_SHOVEN17_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN17 */
|
||||
#define IFX_OVC_OSEL_SHOVEN17_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN18 */
|
||||
#define IFX_OVC_OSEL_SHOVEN18_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN18 */
|
||||
#define IFX_OVC_OSEL_SHOVEN18_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN18 */
|
||||
#define IFX_OVC_OSEL_SHOVEN18_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN19 */
|
||||
#define IFX_OVC_OSEL_SHOVEN19_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN19 */
|
||||
#define IFX_OVC_OSEL_SHOVEN19_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN19 */
|
||||
#define IFX_OVC_OSEL_SHOVEN19_OFF (19u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN1 */
|
||||
#define IFX_OVC_OSEL_SHOVEN1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN1 */
|
||||
#define IFX_OVC_OSEL_SHOVEN1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN1 */
|
||||
#define IFX_OVC_OSEL_SHOVEN1_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN20 */
|
||||
#define IFX_OVC_OSEL_SHOVEN20_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN20 */
|
||||
#define IFX_OVC_OSEL_SHOVEN20_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN20 */
|
||||
#define IFX_OVC_OSEL_SHOVEN20_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN21 */
|
||||
#define IFX_OVC_OSEL_SHOVEN21_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN21 */
|
||||
#define IFX_OVC_OSEL_SHOVEN21_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN21 */
|
||||
#define IFX_OVC_OSEL_SHOVEN21_OFF (21u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN22 */
|
||||
#define IFX_OVC_OSEL_SHOVEN22_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN22 */
|
||||
#define IFX_OVC_OSEL_SHOVEN22_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN22 */
|
||||
#define IFX_OVC_OSEL_SHOVEN22_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN23 */
|
||||
#define IFX_OVC_OSEL_SHOVEN23_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN23 */
|
||||
#define IFX_OVC_OSEL_SHOVEN23_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN23 */
|
||||
#define IFX_OVC_OSEL_SHOVEN23_OFF (23u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN24 */
|
||||
#define IFX_OVC_OSEL_SHOVEN24_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN24 */
|
||||
#define IFX_OVC_OSEL_SHOVEN24_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN24 */
|
||||
#define IFX_OVC_OSEL_SHOVEN24_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN25 */
|
||||
#define IFX_OVC_OSEL_SHOVEN25_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN25 */
|
||||
#define IFX_OVC_OSEL_SHOVEN25_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN25 */
|
||||
#define IFX_OVC_OSEL_SHOVEN25_OFF (25u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN26 */
|
||||
#define IFX_OVC_OSEL_SHOVEN26_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN26 */
|
||||
#define IFX_OVC_OSEL_SHOVEN26_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN26 */
|
||||
#define IFX_OVC_OSEL_SHOVEN26_OFF (26u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN27 */
|
||||
#define IFX_OVC_OSEL_SHOVEN27_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN27 */
|
||||
#define IFX_OVC_OSEL_SHOVEN27_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN27 */
|
||||
#define IFX_OVC_OSEL_SHOVEN27_OFF (27u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN28 */
|
||||
#define IFX_OVC_OSEL_SHOVEN28_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN28 */
|
||||
#define IFX_OVC_OSEL_SHOVEN28_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN28 */
|
||||
#define IFX_OVC_OSEL_SHOVEN28_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN29 */
|
||||
#define IFX_OVC_OSEL_SHOVEN29_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN29 */
|
||||
#define IFX_OVC_OSEL_SHOVEN29_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN29 */
|
||||
#define IFX_OVC_OSEL_SHOVEN29_OFF (29u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN2 */
|
||||
#define IFX_OVC_OSEL_SHOVEN2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN2 */
|
||||
#define IFX_OVC_OSEL_SHOVEN2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN2 */
|
||||
#define IFX_OVC_OSEL_SHOVEN2_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN30 */
|
||||
#define IFX_OVC_OSEL_SHOVEN30_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN30 */
|
||||
#define IFX_OVC_OSEL_SHOVEN30_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN30 */
|
||||
#define IFX_OVC_OSEL_SHOVEN30_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN31 */
|
||||
#define IFX_OVC_OSEL_SHOVEN31_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN31 */
|
||||
#define IFX_OVC_OSEL_SHOVEN31_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN31 */
|
||||
#define IFX_OVC_OSEL_SHOVEN31_OFF (31u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN3 */
|
||||
#define IFX_OVC_OSEL_SHOVEN3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN3 */
|
||||
#define IFX_OVC_OSEL_SHOVEN3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN3 */
|
||||
#define IFX_OVC_OSEL_SHOVEN3_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN4 */
|
||||
#define IFX_OVC_OSEL_SHOVEN4_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN4 */
|
||||
#define IFX_OVC_OSEL_SHOVEN4_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN4 */
|
||||
#define IFX_OVC_OSEL_SHOVEN4_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN5 */
|
||||
#define IFX_OVC_OSEL_SHOVEN5_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN5 */
|
||||
#define IFX_OVC_OSEL_SHOVEN5_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN5 */
|
||||
#define IFX_OVC_OSEL_SHOVEN5_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN6 */
|
||||
#define IFX_OVC_OSEL_SHOVEN6_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN6 */
|
||||
#define IFX_OVC_OSEL_SHOVEN6_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN6 */
|
||||
#define IFX_OVC_OSEL_SHOVEN6_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN7 */
|
||||
#define IFX_OVC_OSEL_SHOVEN7_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN7 */
|
||||
#define IFX_OVC_OSEL_SHOVEN7_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN7 */
|
||||
#define IFX_OVC_OSEL_SHOVEN7_OFF (7u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN8 */
|
||||
#define IFX_OVC_OSEL_SHOVEN8_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN8 */
|
||||
#define IFX_OVC_OSEL_SHOVEN8_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN8 */
|
||||
#define IFX_OVC_OSEL_SHOVEN8_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_OVC_OSEL_Bits.SHOVEN9 */
|
||||
#define IFX_OVC_OSEL_SHOVEN9_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_OVC_OSEL_Bits.SHOVEN9 */
|
||||
#define IFX_OVC_OSEL_SHOVEN9_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_OVC_OSEL_Bits.SHOVEN9 */
|
||||
#define IFX_OVC_OSEL_SHOVEN9_OFF (9u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXOVC_BF_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,185 +0,0 @@
|
||||
/**
|
||||
* \file IfxOvc_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Ovc Ovc
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Ovc_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Ovc
|
||||
*
|
||||
* \defgroup IfxLld_Ovc_union Union
|
||||
* \ingroup IfxLld_Ovc
|
||||
*
|
||||
* \defgroup IfxLld_Ovc_struct Struct
|
||||
* \ingroup IfxLld_Ovc
|
||||
*
|
||||
*/
|
||||
#ifndef IFXOVC_REGDEF_H
|
||||
#define IFXOVC_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ovc_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Overlay Mask Register */
|
||||
typedef struct _Ifx_OVC_BLK_OMASK_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit reserved_0:5; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit OMASK:12; /**< \brief [16:5] Overlay Address Mask (rw) */
|
||||
Ifx_Strict_32Bit ONE:11; /**< \brief [27:17] Fixed "1" Values (r) */
|
||||
Ifx_Strict_32Bit reserved_28:4; /**< \brief \internal Reserved */
|
||||
} Ifx_OVC_BLK_OMASK_Bits;
|
||||
|
||||
/** \brief Overlay Target Address Register */
|
||||
typedef struct _Ifx_OVC_BLK_OTAR_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit reserved_0:5; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit TBASE:23; /**< \brief [27:5] Target Base (rw) */
|
||||
Ifx_Strict_32Bit reserved_28:4; /**< \brief \internal Reserved */
|
||||
} Ifx_OVC_BLK_OTAR_Bits;
|
||||
|
||||
/** \brief Redirected Address Base Register */
|
||||
typedef struct _Ifx_OVC_BLK_RABR_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit reserved_0:5; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit OBASE:17; /**< \brief [21:5] Overlay Block Base Address (rw) */
|
||||
Ifx_Strict_32Bit reserved_22:2; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit OMEM:3; /**< \brief [26:24] Overlay Memory Select (rw) */
|
||||
Ifx_Strict_32Bit reserved_27:4; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit OVEN:1; /**< \brief [31:31] Overlay Enabled (rwh) */
|
||||
} Ifx_OVC_BLK_RABR_Bits;
|
||||
|
||||
/** \brief Overlay Range Select Register */
|
||||
typedef struct _Ifx_OVC_OSEL_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit SHOVEN0:1; /**< \brief [0:0] Shadow Overlay Enable 0 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN1:1; /**< \brief [1:1] Shadow Overlay Enable 1 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN2:1; /**< \brief [2:2] Shadow Overlay Enable 2 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN3:1; /**< \brief [3:3] Shadow Overlay Enable 3 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN4:1; /**< \brief [4:4] Shadow Overlay Enable 4 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN5:1; /**< \brief [5:5] Shadow Overlay Enable 5 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN6:1; /**< \brief [6:6] Shadow Overlay Enable 6 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN7:1; /**< \brief [7:7] Shadow Overlay Enable 7 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN8:1; /**< \brief [8:8] Shadow Overlay Enable 8 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN9:1; /**< \brief [9:9] Shadow Overlay Enable 9 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN10:1; /**< \brief [10:10] Shadow Overlay Enable 10 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN11:1; /**< \brief [11:11] Shadow Overlay Enable 11 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN12:1; /**< \brief [12:12] Shadow Overlay Enable 12 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN13:1; /**< \brief [13:13] Shadow Overlay Enable 13 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN14:1; /**< \brief [14:14] Shadow Overlay Enable 14 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN15:1; /**< \brief [15:15] Shadow Overlay Enable 15 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN16:1; /**< \brief [16:16] Shadow Overlay Enable 16 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN17:1; /**< \brief [17:17] Shadow Overlay Enable 17 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN18:1; /**< \brief [18:18] Shadow Overlay Enable 18 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN19:1; /**< \brief [19:19] Shadow Overlay Enable 19 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN20:1; /**< \brief [20:20] Shadow Overlay Enable 20 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN21:1; /**< \brief [21:21] Shadow Overlay Enable 21 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN22:1; /**< \brief [22:22] Shadow Overlay Enable 22 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN23:1; /**< \brief [23:23] Shadow Overlay Enable 23 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN24:1; /**< \brief [24:24] Shadow Overlay Enable 24 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN25:1; /**< \brief [25:25] Shadow Overlay Enable 25 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN26:1; /**< \brief [26:26] Shadow Overlay Enable 26 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN27:1; /**< \brief [27:27] Shadow Overlay Enable 27 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN28:1; /**< \brief [28:28] Shadow Overlay Enable 28 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN29:1; /**< \brief [29:29] Shadow Overlay Enable 29 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN30:1; /**< \brief [30:30] Shadow Overlay Enable 30 (rw) */
|
||||
Ifx_Strict_32Bit SHOVEN31:1; /**< \brief [31:31] Shadow Overlay Enable 31 (rw) */
|
||||
} Ifx_OVC_OSEL_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ovc_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Overlay Mask Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_OVC_BLK_OMASK_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_OVC_BLK_OMASK;
|
||||
|
||||
/** \brief Overlay Target Address Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_OVC_BLK_OTAR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_OVC_BLK_OTAR;
|
||||
|
||||
/** \brief Redirected Address Base Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_OVC_BLK_RABR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_OVC_BLK_RABR;
|
||||
|
||||
/** \brief Overlay Range Select Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_OVC_OSEL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_OVC_OSEL;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ovc_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L1
|
||||
* \{ */
|
||||
|
||||
/** \brief Overlay blocks objects */
|
||||
typedef volatile struct _Ifx_OVC_BLK
|
||||
{
|
||||
Ifx_OVC_BLK_RABR RABR; /**< \brief 0, Redirected Address Base Register */
|
||||
Ifx_OVC_BLK_OTAR OTAR; /**< \brief 4, Overlay Target Address Register */
|
||||
Ifx_OVC_BLK_OMASK OMASK; /**< \brief 8, Overlay Mask Register */
|
||||
} Ifx_OVC_BLK;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ovc_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief OVC object */
|
||||
typedef volatile struct _Ifx_OVC
|
||||
{
|
||||
Ifx_OVC_OSEL OSEL; /**< \brief 0, Overlay Range Select Register */
|
||||
unsigned char reserved_4[12]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_OVC_BLK BLK[32]; /**< \brief 10, Overlay blocks objects */
|
||||
unsigned char reserved_190[112]; /**< \brief 190, \internal Reserved */
|
||||
} Ifx_OVC;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXOVC_REGDEF_H */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user