mirror of
https://gitee.com/seekfree/TC264_Library.git
synced 2026-06-04 03:32:56 +00:00
V1.0.4
默认勾选上生成HEX的功能 对Cpu1_Main.c中的core1_main函数默认添加 开启总中断的函数。 修复CPU1无法响应中断的问题 删除汇编中的包含路径信息 修复总钻风小分辨只采集一次的问题 添加RDA5807 FM模块驱动代码 修改LSL文件，方便通过#pragma 来指定变量或者程序放在指定RAM，具体如何使用请参考库例程Specifies_Variable_Or_Code_Location_Demo
This commit is contained in:
SEEKFREE_Kang
@@ -170,88 +170,6 @@
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</tool>
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<tool id="com.tasking.ctc.as.abs.debug.1390239146" name="Assembler" superClass="com.tasking.ctc.as.abs.debug">
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<option id="com.tasking.ctc.as.includePaths.1708708624" name="Include paths" superClass="com.tasking.ctc.as.includePaths" valueType="includePath">
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Config}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Cfg_Illd}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Demo_Illd}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Main}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/CStart}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/Irq}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/Std}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/Trap}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Config}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Config/Common}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Cfg_Illd}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Demo_Illd}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Main}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/Doc}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/Doc/Source}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Build}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Impl}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Lib}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Lib/DataHandling}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Lib/InternalMux}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_PinMap}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Asclin}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Ccu6}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cif}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Dma}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Dsadc}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Dts}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Emem}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Eray}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Eth}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Fce}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Fft}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Flash}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Gpt12}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Gtm}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Hssl}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/I2c}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Iom}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Msc}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Mtu}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Multican}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Port}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Psi5}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Psi5s}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Qspi}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Scu}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Sent}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Smu}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Src}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Stm}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Vadc}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Platform}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Platform/Tricore}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Platform/Tricore/Compilers}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Sfr}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Sfr/TC26B}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Sfr/TC26B/_Reg}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/_Utilities}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/If}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/If/Ccu6If}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/StdIf}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Bsp}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Comm}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/General}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Math}""/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Time}""/>
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</option>
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<inputType id="com.tasking.ctc.asmInputType.1471959711" name="ASM" superClass="com.tasking.ctc.asmInputType"/>
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</tool>
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@@ -270,12 +270,19 @@ derivative tc26
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{
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select "(.data.data_cpu1|.data.data_cpu1*)";
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select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
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select ".bss.cpu1_dsram";
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select ".data.cpu1_dsram";
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select ".zdata.cpu1_dsram";
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}
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group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
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{
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select "(.data.data_cpu0|.data.data_cpu0*)";
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select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
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select ".bss.cpu0_dsram";
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select ".data.cpu0_dsram";
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select ".zdata.cpu0_dsram";
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}
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# if LCF_DEFAULT_HOST == LCF_CPU1
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@@ -413,6 +420,7 @@ derivative tc26
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group (ordered, run_addr=mem:pfls0)
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{
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select ".rodata*";
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}
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group (ordered, run_addr=mem:pfls0)
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{
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@@ -17,4 +17,35 @@ V1.0.2
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<09><><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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V1.0.3
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<09><>spi<70><69>uart<72><74>pit<69>в<EFBFBD><D0B2>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>volatile<6C><65><EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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<09><>spi<70><69>uart<72><74>pit<69>в<EFBFBD><D0B2>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>volatile<6C><65><EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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V1.0.4
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Ĭ<>Ϲ<EFBFBD>ѡ<EFBFBD><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HEX<45>Ĺ<EFBFBD><C4B9><EFBFBD>
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<09><>Cpu1_Main.c<>е<EFBFBD>core1_main<69><6E><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϵĺ<CFB5><C4BA><EFBFBD><EFBFBD><EFBFBD>
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<09><EFBFBD>CPU1<55><EFBFBD><DEB7><EFBFBD>Ӧ<EFBFBD>жϵ<D0B6><CFB5><EFBFBD><EFBFBD><EFBFBD>
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ɾ<><C9BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>еİ<D0B5><C4B0><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD>Ϣ
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<09><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD>ֱ<EFBFBD>ֻ<EFBFBD>ɼ<EFBFBD>һ<EFBFBD>ε<EFBFBD><CEB5><EFBFBD><EFBFBD><EFBFBD>
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<09><EFBFBD>LSL<53>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>#pragma <20><>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߳<EFBFBD><DFB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>RAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ο<EFBFBD><CEBF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Specifies_Variable_Or_Code_Location_Demo
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//ʹ<><CAB9>#pragma section all "cpu0_dsram" <20><> #pragma section all restore<72><65><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram
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//<2F><><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>仰<EFBFBD>м伴<D0BC>ɣ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#pragma section all "cpu0_dsram"
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uint8 test_arry[5]; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D>Ϊcpu1_dsram <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu1_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//<2F><><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>CPUִ<55>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>õı<C3B5><C4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu1_dsram<61><6D><EFBFBD><EFBFBD>
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#pragma section all restore
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//ʹ<><CAB9>#pragma section all "cpu0_psram" <20><> #pragma section all restore<72><65><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu0_psram
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//<2F><><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>仰<EFBFBD>м伴<D0BC>ɣ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#pragma section all "cpu0_psram"
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void delay_tset(void) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu0_psram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4>
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{
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int i;
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i = 999;
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while(i--);
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}
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_psram<61><6D>Ϊcpu1_psram <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu1_psram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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//<2F><><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>CPUִ<55>У<EFBFBD><D0A3><EFBFBD><F2BDABBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>£<EFBFBD><C2A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ǵ<EFBFBD>flash<73><68><EFBFBD>ز<EFBFBD>ִ<EFBFBD><D6B4>
|
||||
//ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAM<41><4D><EFBFBD>У<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD>еij<D0B5><C4B3><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cache<68><EFBFBD><F3A3ACBB><EFBFBD><EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD>ٶȽ<D9B6><C8BD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ǾͿ<C7BE><CDBF>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAMִ<4D>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٶ<EFBFBD>
|
||||
#pragma section all restore
|
||||
|
||||
|
||||
@@ -24,7 +24,7 @@
|
||||
|
||||
uint8 camera_type; //<2F><><EFBFBD><EFBFBD>ͷ<EFBFBD>ͺ<EFBFBD> 1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 2<><32><EFBFBD><EFBFBD>ͫ<EFBFBD><CDAB><EFBFBD><EFBFBD>δ֧<CEB4>֣<EFBFBD>3<EFBFBD><33>С<EFBFBD><D0A1><EFBFBD><EFBFBD>
|
||||
|
||||
|
||||
uint32 te;
|
||||
|
||||
App_Cpu0 g_AppCpu0; //Ƶ<><C6B5><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>
|
||||
void get_clk(void)
|
||||
@@ -40,4 +40,6 @@ void get_clk(void)
|
||||
g_AppCpu0.info.cpuFreq = IfxScuCcu_getCpuFrequency(IfxCpu_getCoreIndex());
|
||||
g_AppCpu0.info.sysFreq = IfxScuCcu_getSpbFrequency();
|
||||
g_AppCpu0.info.stmFreq = IfxStm_getFrequency(&MODULE_STM0);
|
||||
|
||||
te = IfxScuCcu_getSriFrequency();
|
||||
}
|
||||
|
||||
@@ -63,6 +63,7 @@
|
||||
#include "SEEKFREE_WIRELESS.h"
|
||||
#include "SEEKFREE_IPS200_PARALLEL8.h"
|
||||
#include "SEEKFREE_7725.h"
|
||||
#include "SEEKFREE_RDA5807.h"
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -50,7 +50,6 @@ void pit_init(CCU6N_enum ccu6n, CCU6_CHN_enum pit_ch, uint32 time);
|
||||
|
||||
|
||||
//------------------------------------<2D><><EFBFBD>´<EFBFBD><C2B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PIT<49>ж<EFBFBD>------------------------------------
|
||||
//-----------------<2D><><EFBFBD>ñ<EFBFBD><C3B1>꺯<EFBFBD><EABAAF>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD>pit_init<69><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Գ<EFBFBD>ʼ<EFBFBD><CABC>PIT<49><54><EFBFBD><EFBFBD>-------------------
|
||||
#define pit_interrupt_ms(ccu6n, pit_ch, time) pit_init(ccu6n, pit_ch, time*1000) //(<28><>λΪ <20><><EFBFBD><EFBFBD>)
|
||||
#define pit_interrupt_us(ccu6n, pit_ch, time) pit_init(ccu6n, pit_ch, time) //(<28><>λΪ <><CEA2>)
|
||||
|
||||
|
||||
@@ -314,6 +314,7 @@ void mt9v03x_init(void)
|
||||
|
||||
|
||||
uint8 mt9v03x_finish_flag = 0; //һ<><D2BB>ͼ<EFBFBD><CDBC><EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD>ɱ<EFBFBD>־λ
|
||||
uint8 mt9v03x_dma_int_num; //<2F><>ǰDMA<4D>жϴ<D0B6><CFB4><EFBFBD>
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief MT9V03X<33><58><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>ж<EFBFBD>
|
||||
// @param NULL
|
||||
@@ -324,15 +325,20 @@ uint8 mt9v03x_finish_flag = 0; //һ
|
||||
void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
|
||||
mt9v03x_dma_int_num = 0;
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
if(1 == link_list_num)
|
||||
{
|
||||
//û<>в<EFBFBD><D0B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӵ<EFBFBD><D3B4><EFBFBD>ģʽ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD>ĵ<EFBFBD>ַ
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, mt9v03x_image[0]);
|
||||
}
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
uint8 mt9v03x_dma_int_num; //<2F><>ǰDMA<4D>жϴ<D0B6><CFB4><EFBFBD>
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief MT9V03X<33><58><EFBFBD><EFBFBD>ͷDMA<4D><41><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
||||
// @param NULL
|
||||
|
||||
@@ -0,0 +1,220 @@
|
||||
/*********************************************************************************************************************
|
||||
* COPYRIGHT NOTICE
|
||||
* Copyright (c) 2020,<2C><><EFBFBD>ɿƼ<C9BF>
|
||||
* All rights reserved.
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>QQȺ<51><C8BA><EFBFBD><EFBFBD>Ⱥ<EFBFBD><C8BA>824575535
|
||||
*
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD>У<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҵ<EFBFBD><D2B5>;<EFBFBD><CDBE>
|
||||
* <20><>ӭ<EFBFBD><D3AD>λʹ<CEBB>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>뱣<EFBFBD><EBB1A3><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC>İ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*
|
||||
* @file MPU6050
|
||||
* @company <09>ɶ<EFBFBD><C9B6><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD><EFBFBD>˾
|
||||
* @author <09><><EFBFBD>ɿƼ<C9BF>(QQ3184284598)
|
||||
* @version <09>鿴doc<6F><63>version<6F>ļ<EFBFBD> <20>汾˵<E6B1BE><CBB5>
|
||||
* @Software tasking v6.3r1
|
||||
* @Target core TC264D
|
||||
* @Taobao https://seekfree.taobao.com/
|
||||
* @date 2020-3-23
|
||||
* @note
|
||||
<09><><EFBFBD>߶<EFBFBD><DFB6>壺
|
||||
------------------------------------
|
||||
<09><><EFBFBD><EFBFBD>IIC
|
||||
SCL <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SCL<43>궨<EFBFBD><EAB6A8>
|
||||
SDA <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SDA<44>궨<EFBFBD><EAB6A8>
|
||||
|
||||
Ӳ<><D3B2>IIC
|
||||
SCL <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
SDA <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
------------------------------------
|
||||
ע<><D7A2><EFBFBD><EFBFBD><EFBFBD>RDA5807<30><37>SCL<43><4C>SDA<44><41><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>1K<31><4B><EFBFBD><EFBFBD>Ȼ<EFBFBD><C8BB><EFBFBD><EFBFBD><EFBFBD>뵥Ƭ<EBB5A5><C6AC><EFBFBD><EFBFBD><EFBFBD>ӣ<EFBFBD><D3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
|
||||
********************************************************************************************************************/
|
||||
|
||||
|
||||
|
||||
#include "SEEKFREE_IIC.h"
|
||||
#include "zf_stm_systick.h"
|
||||
#include "SEEKFREE_RDA5807.h"
|
||||
|
||||
|
||||
#define ack 1 //<2F><>Ӧ<EFBFBD><D3A6>
|
||||
#define no_ack 0 //<2F><>Ӧ<EFBFBD><D3A6>
|
||||
|
||||
|
||||
#define FM_ADDRESS 0x20>>1
|
||||
|
||||
uint8 rda5807_config_reg[] = {
|
||||
0xc1, 0x03, // Register 0x2
|
||||
0x00, 0x00, // Register 0x3
|
||||
0x0a, 0x00, // Register 0x4
|
||||
0x88, 0x0f, // Register 0x5
|
||||
0x00, 0x00, // Register 0x6
|
||||
0x42, 0x02, // Register 0x7
|
||||
};
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807ģ<37><C4A3>IIC<49><43>ȡ<EFBFBD><C8A1><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @param dev_add <09>豸<EFBFBD><E8B1B8>ַ(<28><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>ַ)
|
||||
// @param data[] <09><><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD>ĵ<EFBFBD>ַָ<D6B7><D6B8>
|
||||
// @param num <09><>ȡ<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rad5807m_simiic_write(uint8 dev_add, uint8 data[], uint8 num)
|
||||
{
|
||||
uint8 i;
|
||||
simiic_start();
|
||||
send_ch( (dev_add<<1) | 0x00); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>дλ
|
||||
|
||||
for(i=0;i<num;i++)
|
||||
send_ch(data[i]); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
simiic_stop();
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief ģ<><C4A3>IIC<49><43>ȡ<EFBFBD><C8A1><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @param dev_add <09>豸<EFBFBD><E8B1B8>ַ(<28><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>ַ)
|
||||
// @param dat_add <09><><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD>ĵ<EFBFBD>ַָ<D6B7><D6B8>
|
||||
// @param num <09><>ȡ<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @return uint8 <09><><EFBFBD>ؼĴ<D8BC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807m_simiic_read(uint8 dev_add,uint8 *dat_add,uint8 num)
|
||||
{
|
||||
simiic_start();
|
||||
|
||||
send_ch( (dev_add<<1) | 0x01); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD>Ӷ<EFBFBD>λ
|
||||
while(--num)
|
||||
{
|
||||
*dat_add = read_ch(ack); //<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
|
||||
dat_add++;
|
||||
|
||||
}
|
||||
*dat_add = read_ch(no_ack); //<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
|
||||
|
||||
simiic_stop();
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief Ƶ<>ʼĴ<CABC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3>ڲ<EFBFBD>ʹ<EFBFBD>ã<EFBFBD><C3A3>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD>
|
||||
// @param channel Ƶ<>ʼĴ<CABC><C4B4><EFBFBD>ֵ
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_channel_config(uint16 reg_chn)
|
||||
{
|
||||
rda5807_config_reg[0] = 0xc0;
|
||||
rda5807_config_reg[1] = 0x01;
|
||||
rda5807_config_reg[2] = (uint8)(reg_chn >> 2);
|
||||
rda5807_config_reg[3] = (uint8)(((reg_chn & 0x3) << 6) | 0x18);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5> <09><><EFBFBD>ڲ<EFBFBD>ʹ<EFBFBD>ã<EFBFBD><C3A3>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD>
|
||||
// @param freq Ƶ<><C6B5>ֵ
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_set_channel(float freq)
|
||||
{
|
||||
uint16 reg_chn=0;
|
||||
reg_chn = (int)((freq - 76.0) * 10.0 + 0.5);
|
||||
rda5807_channel_config(reg_chn);
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg, 4);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ģʽ
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_set_idle(void)
|
||||
{
|
||||
rda5807_config_reg[1] &= ~(1<<0);//Power Up Disabled.
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg, 4);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ģʽ
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_set_transimt(void)
|
||||
{
|
||||
rda5807_config_reg[1] |= 1<<0;//Power Up Enable.
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg, 4);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
uint8 rda5807_read_reg[10];
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37>ȡID<49><44><EFBFBD>ڲ<EFBFBD>ʹ<EFBFBD>ã<EFBFBD><C3A3>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD>
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_read_id(void)
|
||||
{
|
||||
rda5807m_simiic_read(FM_ADDRESS,rda5807_read_reg,10);
|
||||
}
|
||||
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37>ʼ<EFBFBD><CABC>
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_init(float freq)
|
||||
{
|
||||
uint8 dat[2] = {0x00,0x02};
|
||||
|
||||
|
||||
//iic<69><63>ʼ<EFBFBD><CABC>
|
||||
simiic_init();
|
||||
simiic_delay_set(100);//<2F><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>IIC<49><43>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ΪĬ<CEAA><C4AC><EFBFBD><EFBFBD><EFBFBD>ʽϸ<CABD>
|
||||
//<2F><>λ
|
||||
rad5807m_simiic_write(FM_ADDRESS,dat,2);
|
||||
|
||||
systick_delay_ms(STM0, 600);
|
||||
|
||||
while(rda5807_read_reg[8] != 0x58)
|
||||
{
|
||||
//<2F><>ȡ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Լ졣
|
||||
rda5807m_simiic_read(FM_ADDRESS,rda5807_read_reg,10);
|
||||
systick_delay_ms(STM0, 50);
|
||||
//<2F><><EFBFBD><EFBFBD>һֱ<D2BB><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>鿴SCL<43><4C>SDA<44>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD>Ӻá<D3BA>
|
||||
//<2F><>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>SEEKFREE_IIC.h<>ļ<EFBFBD><C4BC>е<EFBFBD>SIMIIC_DELAY_TIMEֵ<45><D6B5><EFBFBD><EFBFBD>60
|
||||
}
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD>
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg,sizeof(rda5807_config_reg));
|
||||
//Ƶ<><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
rda5807_set_channel(freq);
|
||||
|
||||
simiic_delay_set(SIMIIC_DELAY_TIME);//<2F><>ԭģ<D4AD><C4A3>IICĬ<43><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,56 @@
|
||||
/*********************************************************************************************************************
|
||||
* COPYRIGHT NOTICE
|
||||
* Copyright (c) 2020,<2C><><EFBFBD>ɿƼ<C9BF>
|
||||
* All rights reserved.
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>QQȺ<51><C8BA><EFBFBD><EFBFBD>Ⱥ<EFBFBD><C8BA>824575535
|
||||
*
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD>У<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҵ<EFBFBD><D2B5>;<EFBFBD><CDBE>
|
||||
* <20><>ӭ<EFBFBD><D3AD>λʹ<CEBB>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>뱣<EFBFBD><EBB1A3><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC>İ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*
|
||||
* @file MPU6050
|
||||
* @company <09>ɶ<EFBFBD><C9B6><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD><EFBFBD>˾
|
||||
* @author <09><><EFBFBD>ɿƼ<C9BF>(QQ3184284598)
|
||||
* @version <09>鿴doc<6F><63>version<6F>ļ<EFBFBD> <20>汾˵<E6B1BE><CBB5>
|
||||
* @Software tasking v6.3r1
|
||||
* @Target core TC264D
|
||||
* @Taobao https://seekfree.taobao.com/
|
||||
* @date 2020-3-23
|
||||
* @note
|
||||
<09><><EFBFBD>߶<EFBFBD><DFB6>壺
|
||||
------------------------------------
|
||||
<09><><EFBFBD><EFBFBD>IIC
|
||||
SCL <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SCL<43>궨<EFBFBD><EAB6A8>
|
||||
SDA <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SDA<44>궨<EFBFBD><EAB6A8>
|
||||
|
||||
Ӳ<><D3B2>IIC
|
||||
SCL <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
SDA <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
------------------------------------
|
||||
ע<><D7A2><EFBFBD><EFBFBD><EFBFBD>RDA5807<30><37>SCL<43><4C>SDA<44><41><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>1K<31><4B><EFBFBD><EFBFBD>Ȼ<EFBFBD><C8BB><EFBFBD><EFBFBD><EFBFBD>뵥Ƭ<EBB5A5><C6AC><EFBFBD><EFBFBD><EFBFBD>ӣ<EFBFBD><D3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
|
||||
********************************************************************************************************************/
|
||||
|
||||
|
||||
#ifndef _FM5807_H
|
||||
#define _FM5807_H
|
||||
#include "common.h"
|
||||
#include "SEEKFREE_FONT.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void rda5807_init(float freq);
|
||||
void rda5807_set_transimt(void);
|
||||
void rda5807_set_idle(void);
|
||||
void rda5807_set_channel(float freq);
|
||||
void rda5807_channel_config(uint16 reg_chn);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -19,6 +19,7 @@
|
||||
|
||||
|
||||
#include "headfile.h"
|
||||
#pragma section all "cpu0_dsram"
|
||||
|
||||
uint16 adc_result;
|
||||
|
||||
@@ -44,3 +45,5 @@ int core0_main(void)
|
||||
}
|
||||
}
|
||||
|
||||
#pragma section all restore
|
||||
|
||||
|
||||
@@ -18,14 +18,19 @@
|
||||
********************************************************************************************************************/
|
||||
|
||||
#include "headfile.h"
|
||||
#pragma section all "cpu1_dsram"
|
||||
|
||||
|
||||
|
||||
|
||||
void core1_main(void)
|
||||
{
|
||||
disableInterrupts();
|
||||
IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
|
||||
|
||||
//<2F>û<EFBFBD><C3BB>ڴ˴<DAB4><CBB4><EFBFBD><EFBFBD>ø<EFBFBD><C3B8>ֳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
enableInterrupts();
|
||||
while (TRUE)
|
||||
{
|
||||
//<2F>û<EFBFBD><C3BB>ڴ˴<DAB4><CBB4><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
@@ -33,3 +38,9 @@ void core1_main(void)
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#pragma section all restore
|
||||
|
||||
@@ -20,28 +20,29 @@
|
||||
|
||||
#include "isr_config.h"
|
||||
#include "isr.h"
|
||||
//<2F><>isr.c<><63><EFBFBD>жϺ<D0B6><CFBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĵڶ<C4B5><DAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̶<EFBFBD>Ϊ0<CEAA><30><EFBFBD>벻Ҫ<EBB2BB><D2AA><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD>CPU1<55><31><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>Ҳ<EFBFBD><D2B2>Ҫ<EFBFBD><D2AA><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD>ҪCPU1<55><31><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA>isr_config.h<><68><EFBFBD>Ķ<DEB8>Ӧ<EFBFBD>ĺ궨<C4BA>弴<EFBFBD><E5BCB4>
|
||||
|
||||
//PIT<49>жϺ<D0B6><CFBA><EFBFBD> ʾ<><CABE>
|
||||
IFX_INTERRUPT(cc60_pit_ch0_isr, CCU6_0_CH0_INT_SERVICE, CCU6_0_CH0_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc60_pit_ch0_isr, 0, CCU6_0_CH0_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_0, PIT_CH0);
|
||||
|
||||
}
|
||||
|
||||
|
||||
IFX_INTERRUPT(cc60_pit_ch1_isr, CCU6_0_CH1_INT_SERVICE, CCU6_0_CH1_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc60_pit_ch1_isr, 0, CCU6_0_CH1_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_0, PIT_CH1);
|
||||
|
||||
}
|
||||
|
||||
IFX_INTERRUPT(cc61_pit_ch0_isr, CCU6_1_CH0_INT_SERVICE, CCU6_1_CH0_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc61_pit_ch0_isr, 0, CCU6_1_CH0_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_1, PIT_CH0);
|
||||
|
||||
}
|
||||
|
||||
IFX_INTERRUPT(cc61_pit_ch1_isr, CCU6_1_CH1_INT_SERVICE, CCU6_1_CH1_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc61_pit_ch1_isr, 0, CCU6_1_CH1_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_1, PIT_CH1);
|
||||
|
||||
@@ -50,7 +51,7 @@ IFX_INTERRUPT(cc61_pit_ch1_isr, CCU6_1_CH1_INT_SERVICE, CCU6_1_CH1_ISR_PRIORITY)
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(eru_ch0_ch4_isr, ERU_CH0_CH4_INT_SERVICE, ERU_CH0_CH4_INT_PRIO)
|
||||
IFX_INTERRUPT(eru_ch0_ch4_isr, 0, ERU_CH0_CH4_INT_PRIO)
|
||||
{
|
||||
if(GET_GPIO_FLAG(ERU_CH0_REQ4_P10_7))//ͨ<><CDA8>0<EFBFBD>ж<EFBFBD>
|
||||
{
|
||||
@@ -63,7 +64,7 @@ IFX_INTERRUPT(eru_ch0_ch4_isr, ERU_CH0_CH4_INT_SERVICE, ERU_CH0_CH4_INT_PRIO)
|
||||
}
|
||||
}
|
||||
|
||||
IFX_INTERRUPT(eru_ch1_ch5_isr, ERU_CH1_CH5_INT_SERVICE, ERU_CH1_CH5_INT_PRIO)
|
||||
IFX_INTERRUPT(eru_ch1_ch5_isr, 0, ERU_CH1_CH5_INT_PRIO)
|
||||
{
|
||||
if(GET_GPIO_FLAG(ERU_CH1_REQ5_P10_8))//ͨ<><CDA8>1<EFBFBD>ж<EFBFBD>
|
||||
{
|
||||
@@ -93,7 +94,7 @@ IFX_INTERRUPT(eru_ch1_ch5_isr, ERU_CH1_CH5_INT_SERVICE, ERU_CH1_CH5_INT_PRIO)
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(eru_ch3_ch7_isr, ERU_CH3_CH7_INT_SERVICE, ERU_CH3_CH7_INT_PRIO)
|
||||
IFX_INTERRUPT(eru_ch3_ch7_isr, 0, ERU_CH3_CH7_INT_PRIO)
|
||||
{
|
||||
if(GET_GPIO_FLAG(ERU_CH3_REQ6_P02_0))//ͨ<><CDA8>3<EFBFBD>ж<EFBFBD>
|
||||
{
|
||||
@@ -111,7 +112,7 @@ IFX_INTERRUPT(eru_ch3_ch7_isr, ERU_CH3_CH7_INT_SERVICE, ERU_CH3_CH7_INT_PRIO)
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(dma_ch5_isr, ERU_DMA_INT_SERVICE, ERU_DMA_INT_PRIO)
|
||||
IFX_INTERRUPT(dma_ch5_isr, 0, ERU_DMA_INT_PRIO)
|
||||
{
|
||||
|
||||
if (1 == camera_type) mt9v03x_dma();
|
||||
@@ -120,61 +121,61 @@ IFX_INTERRUPT(dma_ch5_isr, ERU_DMA_INT_SERVICE, ERU_DMA_INT_PRIO)
|
||||
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD>жϺ<D0B6><CFBA><EFBFBD> ʾ<><CABE>
|
||||
IFX_INTERRUPT(uart0_tx_isr, UART0_INT_SERVICE, UART0_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart0_tx_isr, 0, UART0_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart0_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart0_rx_isr, UART0_INT_SERVICE, UART0_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart0_rx_isr, 0, UART0_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart0_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart0_er_isr, UART0_INT_SERVICE, UART0_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart0_er_isr, 0, UART0_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart0_handle);
|
||||
}
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD>1Ĭ<31><C4AC><EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD><D3B5><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>ô<EFBFBD><C3B4><EFBFBD>
|
||||
IFX_INTERRUPT(uart1_tx_isr, UART1_INT_SERVICE, UART1_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart1_tx_isr, 0, UART1_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart1_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart1_rx_isr, UART1_INT_SERVICE, UART1_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart1_rx_isr, 0, UART1_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart1_handle);
|
||||
mt9v03x_uart_callback();
|
||||
}
|
||||
IFX_INTERRUPT(uart1_er_isr, UART1_INT_SERVICE, UART1_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart1_er_isr, 0, UART1_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart1_handle);
|
||||
}
|
||||
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD>2Ĭ<32><C4AC><EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD><D3B5><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>
|
||||
IFX_INTERRUPT(uart2_tx_isr, UART2_INT_SERVICE, UART2_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart2_tx_isr, 0, UART2_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart2_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart2_rx_isr, UART2_INT_SERVICE, UART2_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart2_rx_isr, 0, UART2_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart2_handle);
|
||||
wireless_uart_callback();
|
||||
}
|
||||
IFX_INTERRUPT(uart2_er_isr, UART2_INT_SERVICE, UART2_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart2_er_isr, 0, UART2_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart2_handle);
|
||||
}
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(uart3_tx_isr, UART3_INT_SERVICE, UART3_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart3_tx_isr, 0, UART3_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart3_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart3_rx_isr, UART3_INT_SERVICE, UART3_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart3_rx_isr, 0, UART3_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart3_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart3_er_isr, UART3_INT_SERVICE, UART3_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart3_er_isr, 0, UART3_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart3_handle);
|
||||
}
|
||||
|
||||
@@ -170,88 +170,6 @@
|
||||
</tool>
|
||||
<tool id="com.tasking.ctc.as.abs.debug.1390239146" name="Assembler" superClass="com.tasking.ctc.as.abs.debug">
|
||||
<option id="com.tasking.ctc.as.includePaths.1708708624" name="Include paths" superClass="com.tasking.ctc.as.includePaths" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Config}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Cfg_Illd}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Demo_Illd}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Main}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/CStart}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/Irq}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/Trap}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Config}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Config/Common}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Cfg_Illd}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Demo_Illd}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Main}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/Doc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/Doc/Source}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Build}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Impl}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Lib}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Lib/DataHandling}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Lib/InternalMux}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_PinMap}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Asclin}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Ccu6}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cif}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Dma}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Dsadc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Dts}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Emem}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Eray}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Eth}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Fce}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Fft}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Flash}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Gpt12}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Gtm}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Hssl}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/I2c}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Iom}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Msc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Mtu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Multican}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Port}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Psi5}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Psi5s}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Qspi}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Scu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Sent}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Smu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Src}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Stm}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Vadc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Platform}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Platform/Tricore}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Platform/Tricore/Compilers}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Sfr}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Sfr/TC26B}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Sfr/TC26B/_Reg}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/_Utilities}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/If}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/If/Ccu6If}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/StdIf}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Bsp}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Comm}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/General}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Math}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Time}""/>
|
||||
</option>
|
||||
<inputType id="com.tasking.ctc.asmInputType.1471959711" name="ASM" superClass="com.tasking.ctc.asmInputType"/>
|
||||
</tool>
|
||||
|
||||
@@ -270,12 +270,19 @@ derivative tc26
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
@@ -413,6 +420,7 @@ derivative tc26
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
|
||||
@@ -17,4 +17,35 @@ V1.0.2
|
||||
<09><><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.3
|
||||
<09><>spi<70><69>uart<72><74>pit<69>в<EFBFBD><D0B2>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>volatile<6C><65><EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><>spi<70><69>uart<72><74>pit<69>в<EFBFBD><D0B2>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>volatile<6C><65><EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.4
|
||||
Ĭ<>Ϲ<EFBFBD>ѡ<EFBFBD><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HEX<45>Ĺ<EFBFBD><C4B9><EFBFBD>
|
||||
<09><>Cpu1_Main.c<>е<EFBFBD>core1_main<69><6E><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϵĺ<CFB5><C4BA><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>CPU1<55><EFBFBD><DEB7><EFBFBD>Ӧ<EFBFBD>жϵ<D0B6><CFB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
ɾ<><C9BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>еİ<D0B5><C4B0><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD>Ϣ
|
||||
<09><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD>ֱ<EFBFBD>ֻ<EFBFBD>ɼ<EFBFBD>һ<EFBFBD>ε<EFBFBD><CEB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>LSL<53>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>#pragma <20><>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߳<EFBFBD><DFB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>RAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ο<EFBFBD><CEBF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Specifies_Variable_Or_Code_Location_Demo
|
||||
//ʹ<><CAB9>#pragma section all "cpu0_dsram" <20><> #pragma section all restore<72><65><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram
|
||||
//<2F><><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>仰<EFBFBD>м伴<D0BC>ɣ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
#pragma section all "cpu0_dsram"
|
||||
uint8 test_arry[5]; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D>Ϊcpu1_dsram <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu1_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>CPUִ<55>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>õı<C3B5><C4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu1_dsram<61><6D><EFBFBD><EFBFBD>
|
||||
#pragma section all restore
|
||||
|
||||
//ʹ<><CAB9>#pragma section all "cpu0_psram" <20><> #pragma section all restore<72><65><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu0_psram
|
||||
//<2F><><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>仰<EFBFBD>м伴<D0BC>ɣ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
#pragma section all "cpu0_psram"
|
||||
void delay_tset(void) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu0_psram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4>
|
||||
{
|
||||
int i;
|
||||
i = 999;
|
||||
while(i--);
|
||||
}
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_psram<61><6D>Ϊcpu1_psram <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu1_psram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>CPUִ<55>У<EFBFBD><D0A3><EFBFBD><F2BDABBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>£<EFBFBD><C2A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ǵ<EFBFBD>flash<73><68><EFBFBD>ز<EFBFBD>ִ<EFBFBD><D6B4>
|
||||
//ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAM<41><4D><EFBFBD>У<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD>еij<D0B5><C4B3><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cache<68><EFBFBD><F3A3ACBB><EFBFBD><EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD>ٶȽ<D9B6><C8BD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ǾͿ<C7BE><CDBF>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAMִ<4D>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٶ<EFBFBD>
|
||||
#pragma section all restore
|
||||
|
||||
|
||||
@@ -24,7 +24,7 @@
|
||||
|
||||
uint8 camera_type; //<2F><><EFBFBD><EFBFBD>ͷ<EFBFBD>ͺ<EFBFBD> 1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 2<><32><EFBFBD><EFBFBD>ͫ<EFBFBD><CDAB><EFBFBD><EFBFBD>δ֧<CEB4>֣<EFBFBD>3<EFBFBD><33>С<EFBFBD><D0A1><EFBFBD><EFBFBD>
|
||||
|
||||
|
||||
uint32 te;
|
||||
|
||||
App_Cpu0 g_AppCpu0; //Ƶ<><C6B5><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>
|
||||
void get_clk(void)
|
||||
@@ -40,4 +40,6 @@ void get_clk(void)
|
||||
g_AppCpu0.info.cpuFreq = IfxScuCcu_getCpuFrequency(IfxCpu_getCoreIndex());
|
||||
g_AppCpu0.info.sysFreq = IfxScuCcu_getSpbFrequency();
|
||||
g_AppCpu0.info.stmFreq = IfxStm_getFrequency(&MODULE_STM0);
|
||||
|
||||
te = IfxScuCcu_getSriFrequency();
|
||||
}
|
||||
|
||||
@@ -63,6 +63,7 @@
|
||||
#include "SEEKFREE_WIRELESS.h"
|
||||
#include "SEEKFREE_IPS200_PARALLEL8.h"
|
||||
#include "SEEKFREE_7725.h"
|
||||
#include "SEEKFREE_RDA5807.h"
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -50,7 +50,6 @@ void pit_init(CCU6N_enum ccu6n, CCU6_CHN_enum pit_ch, uint32 time);
|
||||
|
||||
|
||||
//------------------------------------<2D><><EFBFBD>´<EFBFBD><C2B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PIT<49>ж<EFBFBD>------------------------------------
|
||||
//-----------------<2D><><EFBFBD>ñ<EFBFBD><C3B1>꺯<EFBFBD><EABAAF>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD>pit_init<69><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Գ<EFBFBD>ʼ<EFBFBD><CABC>PIT<49><54><EFBFBD><EFBFBD>-------------------
|
||||
#define pit_interrupt_ms(ccu6n, pit_ch, time) pit_init(ccu6n, pit_ch, time*1000) //(<28><>λΪ <20><><EFBFBD><EFBFBD>)
|
||||
#define pit_interrupt_us(ccu6n, pit_ch, time) pit_init(ccu6n, pit_ch, time) //(<28><>λΪ <><CEA2>)
|
||||
|
||||
|
||||
@@ -314,6 +314,7 @@ void mt9v03x_init(void)
|
||||
|
||||
|
||||
uint8 mt9v03x_finish_flag = 0; //һ<><D2BB>ͼ<EFBFBD><CDBC><EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD>ɱ<EFBFBD>־λ
|
||||
uint8 mt9v03x_dma_int_num; //<2F><>ǰDMA<4D>жϴ<D0B6><CFB4><EFBFBD>
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief MT9V03X<33><58><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>ж<EFBFBD>
|
||||
// @param NULL
|
||||
@@ -324,15 +325,20 @@ uint8 mt9v03x_finish_flag = 0; //һ
|
||||
void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
|
||||
mt9v03x_dma_int_num = 0;
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
if(1 == link_list_num)
|
||||
{
|
||||
//û<>в<EFBFBD><D0B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӵ<EFBFBD><D3B4><EFBFBD>ģʽ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD>ĵ<EFBFBD>ַ
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, mt9v03x_image[0]);
|
||||
}
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
uint8 mt9v03x_dma_int_num; //<2F><>ǰDMA<4D>жϴ<D0B6><CFB4><EFBFBD>
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief MT9V03X<33><58><EFBFBD><EFBFBD>ͷDMA<4D><41><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
||||
// @param NULL
|
||||
|
||||
@@ -0,0 +1,220 @@
|
||||
/*********************************************************************************************************************
|
||||
* COPYRIGHT NOTICE
|
||||
* Copyright (c) 2020,<2C><><EFBFBD>ɿƼ<C9BF>
|
||||
* All rights reserved.
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>QQȺ<51><C8BA><EFBFBD><EFBFBD>Ⱥ<EFBFBD><C8BA>824575535
|
||||
*
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD>У<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҵ<EFBFBD><D2B5>;<EFBFBD><CDBE>
|
||||
* <20><>ӭ<EFBFBD><D3AD>λʹ<CEBB>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>뱣<EFBFBD><EBB1A3><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC>İ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*
|
||||
* @file MPU6050
|
||||
* @company <09>ɶ<EFBFBD><C9B6><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD><EFBFBD>˾
|
||||
* @author <09><><EFBFBD>ɿƼ<C9BF>(QQ3184284598)
|
||||
* @version <09>鿴doc<6F><63>version<6F>ļ<EFBFBD> <20>汾˵<E6B1BE><CBB5>
|
||||
* @Software tasking v6.3r1
|
||||
* @Target core TC264D
|
||||
* @Taobao https://seekfree.taobao.com/
|
||||
* @date 2020-3-23
|
||||
* @note
|
||||
<09><><EFBFBD>߶<EFBFBD><DFB6>壺
|
||||
------------------------------------
|
||||
<09><><EFBFBD><EFBFBD>IIC
|
||||
SCL <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SCL<43>궨<EFBFBD><EAB6A8>
|
||||
SDA <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SDA<44>궨<EFBFBD><EAB6A8>
|
||||
|
||||
Ӳ<><D3B2>IIC
|
||||
SCL <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
SDA <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
------------------------------------
|
||||
ע<><D7A2><EFBFBD><EFBFBD><EFBFBD>RDA5807<30><37>SCL<43><4C>SDA<44><41><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>1K<31><4B><EFBFBD><EFBFBD>Ȼ<EFBFBD><C8BB><EFBFBD><EFBFBD><EFBFBD>뵥Ƭ<EBB5A5><C6AC><EFBFBD><EFBFBD><EFBFBD>ӣ<EFBFBD><D3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
|
||||
********************************************************************************************************************/
|
||||
|
||||
|
||||
|
||||
#include "SEEKFREE_IIC.h"
|
||||
#include "zf_stm_systick.h"
|
||||
#include "SEEKFREE_RDA5807.h"
|
||||
|
||||
|
||||
#define ack 1 //<2F><>Ӧ<EFBFBD><D3A6>
|
||||
#define no_ack 0 //<2F><>Ӧ<EFBFBD><D3A6>
|
||||
|
||||
|
||||
#define FM_ADDRESS 0x20>>1
|
||||
|
||||
uint8 rda5807_config_reg[] = {
|
||||
0xc1, 0x03, // Register 0x2
|
||||
0x00, 0x00, // Register 0x3
|
||||
0x0a, 0x00, // Register 0x4
|
||||
0x88, 0x0f, // Register 0x5
|
||||
0x00, 0x00, // Register 0x6
|
||||
0x42, 0x02, // Register 0x7
|
||||
};
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807ģ<37><C4A3>IIC<49><43>ȡ<EFBFBD><C8A1><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @param dev_add <09>豸<EFBFBD><E8B1B8>ַ(<28><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>ַ)
|
||||
// @param data[] <09><><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD>ĵ<EFBFBD>ַָ<D6B7><D6B8>
|
||||
// @param num <09><>ȡ<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rad5807m_simiic_write(uint8 dev_add, uint8 data[], uint8 num)
|
||||
{
|
||||
uint8 i;
|
||||
simiic_start();
|
||||
send_ch( (dev_add<<1) | 0x00); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>дλ
|
||||
|
||||
for(i=0;i<num;i++)
|
||||
send_ch(data[i]); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
simiic_stop();
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief ģ<><C4A3>IIC<49><43>ȡ<EFBFBD><C8A1><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @param dev_add <09>豸<EFBFBD><E8B1B8>ַ(<28><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>ַ)
|
||||
// @param dat_add <09><><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD>ĵ<EFBFBD>ַָ<D6B7><D6B8>
|
||||
// @param num <09><>ȡ<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @return uint8 <09><><EFBFBD>ؼĴ<D8BC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807m_simiic_read(uint8 dev_add,uint8 *dat_add,uint8 num)
|
||||
{
|
||||
simiic_start();
|
||||
|
||||
send_ch( (dev_add<<1) | 0x01); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD>Ӷ<EFBFBD>λ
|
||||
while(--num)
|
||||
{
|
||||
*dat_add = read_ch(ack); //<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
|
||||
dat_add++;
|
||||
|
||||
}
|
||||
*dat_add = read_ch(no_ack); //<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
|
||||
|
||||
simiic_stop();
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief Ƶ<>ʼĴ<CABC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3>ڲ<EFBFBD>ʹ<EFBFBD>ã<EFBFBD><C3A3>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD>
|
||||
// @param channel Ƶ<>ʼĴ<CABC><C4B4><EFBFBD>ֵ
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_channel_config(uint16 reg_chn)
|
||||
{
|
||||
rda5807_config_reg[0] = 0xc0;
|
||||
rda5807_config_reg[1] = 0x01;
|
||||
rda5807_config_reg[2] = (uint8)(reg_chn >> 2);
|
||||
rda5807_config_reg[3] = (uint8)(((reg_chn & 0x3) << 6) | 0x18);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5> <09><><EFBFBD>ڲ<EFBFBD>ʹ<EFBFBD>ã<EFBFBD><C3A3>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD>
|
||||
// @param freq Ƶ<><C6B5>ֵ
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_set_channel(float freq)
|
||||
{
|
||||
uint16 reg_chn=0;
|
||||
reg_chn = (int)((freq - 76.0) * 10.0 + 0.5);
|
||||
rda5807_channel_config(reg_chn);
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg, 4);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ģʽ
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_set_idle(void)
|
||||
{
|
||||
rda5807_config_reg[1] &= ~(1<<0);//Power Up Disabled.
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg, 4);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ģʽ
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_set_transimt(void)
|
||||
{
|
||||
rda5807_config_reg[1] |= 1<<0;//Power Up Enable.
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg, 4);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
uint8 rda5807_read_reg[10];
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37>ȡID<49><44><EFBFBD>ڲ<EFBFBD>ʹ<EFBFBD>ã<EFBFBD><C3A3>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD>
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_read_id(void)
|
||||
{
|
||||
rda5807m_simiic_read(FM_ADDRESS,rda5807_read_reg,10);
|
||||
}
|
||||
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37>ʼ<EFBFBD><CABC>
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_init(float freq)
|
||||
{
|
||||
uint8 dat[2] = {0x00,0x02};
|
||||
|
||||
|
||||
//iic<69><63>ʼ<EFBFBD><CABC>
|
||||
simiic_init();
|
||||
simiic_delay_set(100);//<2F><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>IIC<49><43>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ΪĬ<CEAA><C4AC><EFBFBD><EFBFBD><EFBFBD>ʽϸ<CABD>
|
||||
//<2F><>λ
|
||||
rad5807m_simiic_write(FM_ADDRESS,dat,2);
|
||||
|
||||
systick_delay_ms(STM0, 600);
|
||||
|
||||
while(rda5807_read_reg[8] != 0x58)
|
||||
{
|
||||
//<2F><>ȡ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Լ졣
|
||||
rda5807m_simiic_read(FM_ADDRESS,rda5807_read_reg,10);
|
||||
systick_delay_ms(STM0, 50);
|
||||
//<2F><><EFBFBD><EFBFBD>һֱ<D2BB><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>鿴SCL<43><4C>SDA<44>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD>Ӻá<D3BA>
|
||||
//<2F><>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>SEEKFREE_IIC.h<>ļ<EFBFBD><C4BC>е<EFBFBD>SIMIIC_DELAY_TIMEֵ<45><D6B5><EFBFBD><EFBFBD>60
|
||||
}
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD>
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg,sizeof(rda5807_config_reg));
|
||||
//Ƶ<><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
rda5807_set_channel(freq);
|
||||
|
||||
simiic_delay_set(SIMIIC_DELAY_TIME);//<2F><>ԭģ<D4AD><C4A3>IICĬ<43><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,56 @@
|
||||
/*********************************************************************************************************************
|
||||
* COPYRIGHT NOTICE
|
||||
* Copyright (c) 2020,<2C><><EFBFBD>ɿƼ<C9BF>
|
||||
* All rights reserved.
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>QQȺ<51><C8BA><EFBFBD><EFBFBD>Ⱥ<EFBFBD><C8BA>824575535
|
||||
*
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD>У<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҵ<EFBFBD><D2B5>;<EFBFBD><CDBE>
|
||||
* <20><>ӭ<EFBFBD><D3AD>λʹ<CEBB>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>뱣<EFBFBD><EBB1A3><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC>İ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*
|
||||
* @file MPU6050
|
||||
* @company <09>ɶ<EFBFBD><C9B6><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD><EFBFBD>˾
|
||||
* @author <09><><EFBFBD>ɿƼ<C9BF>(QQ3184284598)
|
||||
* @version <09>鿴doc<6F><63>version<6F>ļ<EFBFBD> <20>汾˵<E6B1BE><CBB5>
|
||||
* @Software tasking v6.3r1
|
||||
* @Target core TC264D
|
||||
* @Taobao https://seekfree.taobao.com/
|
||||
* @date 2020-3-23
|
||||
* @note
|
||||
<09><><EFBFBD>߶<EFBFBD><DFB6>壺
|
||||
------------------------------------
|
||||
<09><><EFBFBD><EFBFBD>IIC
|
||||
SCL <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SCL<43>궨<EFBFBD><EAB6A8>
|
||||
SDA <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SDA<44>궨<EFBFBD><EAB6A8>
|
||||
|
||||
Ӳ<><D3B2>IIC
|
||||
SCL <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
SDA <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
------------------------------------
|
||||
ע<><D7A2><EFBFBD><EFBFBD><EFBFBD>RDA5807<30><37>SCL<43><4C>SDA<44><41><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>1K<31><4B><EFBFBD><EFBFBD>Ȼ<EFBFBD><C8BB><EFBFBD><EFBFBD><EFBFBD>뵥Ƭ<EBB5A5><C6AC><EFBFBD><EFBFBD><EFBFBD>ӣ<EFBFBD><D3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
|
||||
********************************************************************************************************************/
|
||||
|
||||
|
||||
#ifndef _FM5807_H
|
||||
#define _FM5807_H
|
||||
#include "common.h"
|
||||
#include "SEEKFREE_FONT.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void rda5807_init(float freq);
|
||||
void rda5807_set_transimt(void);
|
||||
void rda5807_set_idle(void);
|
||||
void rda5807_set_channel(float freq);
|
||||
void rda5807_channel_config(uint16 reg_chn);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -19,6 +19,7 @@
|
||||
|
||||
|
||||
#include "headfile.h"
|
||||
#pragma section all "cpu0_dsram"
|
||||
|
||||
uint16 adc_result;
|
||||
|
||||
@@ -42,7 +43,9 @@ int core0_main(void)
|
||||
|
||||
while (TRUE)
|
||||
{
|
||||
|
||||
//<2F><>isr.c<><63><EFBFBD>жϺ<D0B6><CFBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĵڶ<C4B5><DAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̶<EFBFBD>Ϊ0<CEAA><30><EFBFBD>벻Ҫ<EBB2BB><D2AA><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD>CPU1<55><31><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>Ҳ<EFBFBD><D2B2>Ҫ<EFBFBD><D2AA><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD>ҪCPU1<55><31><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA>isr_config.h<><68><EFBFBD>Ķ<DEB8>Ӧ<EFBFBD>ĺ궨<C4BA>弴<EFBFBD><E5BCB4>
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#pragma section all restore
|
||||
|
||||
@@ -18,14 +18,19 @@
|
||||
********************************************************************************************************************/
|
||||
|
||||
#include "headfile.h"
|
||||
#pragma section all "cpu1_dsram"
|
||||
|
||||
|
||||
|
||||
|
||||
void core1_main(void)
|
||||
{
|
||||
disableInterrupts();
|
||||
IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
|
||||
|
||||
//<2F>û<EFBFBD><C3BB>ڴ˴<DAB4><CBB4><EFBFBD><EFBFBD>ø<EFBFBD><C3B8>ֳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
enableInterrupts();
|
||||
while (TRUE)
|
||||
{
|
||||
//<2F>û<EFBFBD><C3BB>ڴ˴<DAB4><CBB4><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
@@ -33,3 +38,9 @@ void core1_main(void)
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#pragma section all restore
|
||||
|
||||
@@ -20,28 +20,30 @@
|
||||
|
||||
#include "isr_config.h"
|
||||
#include "isr.h"
|
||||
//<2F><>isr.c<><63><EFBFBD>жϺ<D0B6><CFBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĵڶ<C4B5><DAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̶<EFBFBD>Ϊ0<CEAA><30><EFBFBD>벻Ҫ<EBB2BB><D2AA><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD>CPU1<55><31><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>Ҳ<EFBFBD><D2B2>Ҫ<EFBFBD><D2AA><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD>ҪCPU1<55><31><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA>isr_config.h<><68><EFBFBD>Ķ<DEB8>Ӧ<EFBFBD>ĺ궨<C4BA>弴<EFBFBD><E5BCB4>
|
||||
|
||||
|
||||
//PIT<49>жϺ<D0B6><CFBA><EFBFBD> ʾ<><CABE>
|
||||
IFX_INTERRUPT(cc60_pit_ch0_isr, CCU6_0_CH0_INT_SERVICE, CCU6_0_CH0_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc60_pit_ch0_isr, 0, CCU6_0_CH0_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_0, PIT_CH0);
|
||||
|
||||
}
|
||||
|
||||
|
||||
IFX_INTERRUPT(cc60_pit_ch1_isr, CCU6_0_CH1_INT_SERVICE, CCU6_0_CH1_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc60_pit_ch1_isr, 0, CCU6_0_CH1_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_0, PIT_CH1);
|
||||
|
||||
}
|
||||
|
||||
IFX_INTERRUPT(cc61_pit_ch0_isr, CCU6_1_CH0_INT_SERVICE, CCU6_1_CH0_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc61_pit_ch0_isr, 0, CCU6_1_CH0_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_1, PIT_CH0);
|
||||
|
||||
}
|
||||
|
||||
IFX_INTERRUPT(cc61_pit_ch1_isr, CCU6_1_CH1_INT_SERVICE, CCU6_1_CH1_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc61_pit_ch1_isr, 0, CCU6_1_CH1_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_1, PIT_CH1);
|
||||
|
||||
@@ -50,7 +52,7 @@ IFX_INTERRUPT(cc61_pit_ch1_isr, CCU6_1_CH1_INT_SERVICE, CCU6_1_CH1_ISR_PRIORITY)
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(eru_ch0_ch4_isr, ERU_CH0_CH4_INT_SERVICE, ERU_CH0_CH4_INT_PRIO)
|
||||
IFX_INTERRUPT(eru_ch0_ch4_isr, 0, ERU_CH0_CH4_INT_PRIO)
|
||||
{
|
||||
if(GET_GPIO_FLAG(ERU_CH0_REQ4_P10_7))//ͨ<><CDA8>0<EFBFBD>ж<EFBFBD>
|
||||
{
|
||||
@@ -63,7 +65,7 @@ IFX_INTERRUPT(eru_ch0_ch4_isr, ERU_CH0_CH4_INT_SERVICE, ERU_CH0_CH4_INT_PRIO)
|
||||
}
|
||||
}
|
||||
|
||||
IFX_INTERRUPT(eru_ch1_ch5_isr, ERU_CH1_CH5_INT_SERVICE, ERU_CH1_CH5_INT_PRIO)
|
||||
IFX_INTERRUPT(eru_ch1_ch5_isr, 0, ERU_CH1_CH5_INT_PRIO)
|
||||
{
|
||||
if(GET_GPIO_FLAG(ERU_CH1_REQ5_P10_8))//ͨ<><CDA8>1<EFBFBD>ж<EFBFBD>
|
||||
{
|
||||
@@ -77,7 +79,7 @@ IFX_INTERRUPT(eru_ch1_ch5_isr, ERU_CH1_CH5_INT_SERVICE, ERU_CH1_CH5_INT_PRIO)
|
||||
}
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷpclk<6C><6B><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC>ռ<EFBFBD><D5BC><EFBFBD><EFBFBD> 2ͨ<32><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD><DAB4><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ﲻ<EFBFBD>ٶ<EFBFBD><D9B6><EFBFBD><EFBFBD>жϺ<D0B6><CFBA><EFBFBD>
|
||||
//IFX_INTERRUPT(eru_ch2_ch6_isr, ERU_CH2_CH6_INT_SERVICE, ERU_CH2_CH6_INT_PRIO)
|
||||
//IFX_INTERRUPT(eru_ch2_ch6_isr, 0, ERU_CH2_CH6_INT_PRIO)
|
||||
//{
|
||||
// if(GET_GPIO_FLAG(ERU_CH2_REQ7_P00_4))//ͨ<><CDA8>2<EFBFBD>ж<EFBFBD>
|
||||
// {
|
||||
@@ -93,7 +95,7 @@ IFX_INTERRUPT(eru_ch1_ch5_isr, ERU_CH1_CH5_INT_SERVICE, ERU_CH1_CH5_INT_PRIO)
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(eru_ch3_ch7_isr, ERU_CH3_CH7_INT_SERVICE, ERU_CH3_CH7_INT_PRIO)
|
||||
IFX_INTERRUPT(eru_ch3_ch7_isr, 0, ERU_CH3_CH7_INT_PRIO)
|
||||
{
|
||||
if(GET_GPIO_FLAG(ERU_CH3_REQ6_P02_0))//ͨ<><CDA8>3<EFBFBD>ж<EFBFBD>
|
||||
{
|
||||
@@ -111,7 +113,7 @@ IFX_INTERRUPT(eru_ch3_ch7_isr, ERU_CH3_CH7_INT_SERVICE, ERU_CH3_CH7_INT_PRIO)
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(dma_ch5_isr, ERU_DMA_INT_SERVICE, ERU_DMA_INT_PRIO)
|
||||
IFX_INTERRUPT(dma_ch5_isr, 0, ERU_DMA_INT_PRIO)
|
||||
{
|
||||
|
||||
if (1 == camera_type) mt9v03x_dma();
|
||||
@@ -120,61 +122,61 @@ IFX_INTERRUPT(dma_ch5_isr, ERU_DMA_INT_SERVICE, ERU_DMA_INT_PRIO)
|
||||
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD>жϺ<D0B6><CFBA><EFBFBD> ʾ<><CABE>
|
||||
IFX_INTERRUPT(uart0_tx_isr, UART0_INT_SERVICE, UART0_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart0_tx_isr, 0, UART0_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart0_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart0_rx_isr, UART0_INT_SERVICE, UART0_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart0_rx_isr, 0, UART0_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart0_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart0_er_isr, UART0_INT_SERVICE, UART0_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart0_er_isr, 0, UART0_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart0_handle);
|
||||
}
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD>1Ĭ<31><C4AC><EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD><D3B5><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>ô<EFBFBD><C3B4><EFBFBD>
|
||||
IFX_INTERRUPT(uart1_tx_isr, UART1_INT_SERVICE, UART1_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart1_tx_isr, 0, UART1_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart1_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart1_rx_isr, UART1_INT_SERVICE, UART1_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart1_rx_isr, 0, UART1_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart1_handle);
|
||||
mt9v03x_uart_callback();
|
||||
}
|
||||
IFX_INTERRUPT(uart1_er_isr, UART1_INT_SERVICE, UART1_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart1_er_isr, 0, UART1_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart1_handle);
|
||||
}
|
||||
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD>2Ĭ<32><C4AC><EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD><D3B5><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>
|
||||
IFX_INTERRUPT(uart2_tx_isr, UART2_INT_SERVICE, UART2_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart2_tx_isr, 0, UART2_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart2_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart2_rx_isr, UART2_INT_SERVICE, UART2_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart2_rx_isr, 0, UART2_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart2_handle);
|
||||
wireless_uart_callback();
|
||||
}
|
||||
IFX_INTERRUPT(uart2_er_isr, UART2_INT_SERVICE, UART2_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart2_er_isr, 0, UART2_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart2_handle);
|
||||
}
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(uart3_tx_isr, UART3_INT_SERVICE, UART3_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart3_tx_isr, 0, UART3_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart3_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart3_rx_isr, UART3_INT_SERVICE, UART3_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart3_rx_isr, 0, UART3_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart3_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart3_er_isr, UART3_INT_SERVICE, UART3_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart3_er_isr, 0, UART3_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart3_handle);
|
||||
}
|
||||
|
||||
@@ -170,88 +170,6 @@
|
||||
</tool>
|
||||
<tool id="com.tasking.ctc.as.abs.debug.1390239146" name="Assembler" superClass="com.tasking.ctc.as.abs.debug">
|
||||
<option id="com.tasking.ctc.as.includePaths.1708708624" name="Include paths" superClass="com.tasking.ctc.as.includePaths" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Config}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Cfg_Illd}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Demo_Illd}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Main}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/CStart}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/Irq}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/Trap}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Config}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Config/Common}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Cfg_Illd}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Demo_Illd}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Main}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/Doc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/Doc/Source}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Build}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Impl}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Lib}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Lib/DataHandling}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Lib/InternalMux}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_PinMap}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Asclin}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Ccu6}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cif}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Dma}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Dsadc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Dts}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Emem}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Eray}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Eth}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Fce}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Fft}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Flash}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Gpt12}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Gtm}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Hssl}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/I2c}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Iom}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Msc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Mtu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Multican}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Port}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Psi5}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Psi5s}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Qspi}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Scu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Sent}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Smu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Src}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Stm}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Vadc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Platform}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Platform/Tricore}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Platform/Tricore/Compilers}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Sfr}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Sfr/TC26B}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Sfr/TC26B/_Reg}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/_Utilities}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/If}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/If/Ccu6If}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/StdIf}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Bsp}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Comm}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/General}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Math}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Time}""/>
|
||||
</option>
|
||||
<inputType id="com.tasking.ctc.asmInputType.1471959711" name="ASM" superClass="com.tasking.ctc.asmInputType"/>
|
||||
</tool>
|
||||
|
||||
@@ -270,12 +270,19 @@ derivative tc26
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
@@ -413,6 +420,7 @@ derivative tc26
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
|
||||
@@ -17,4 +17,35 @@ V1.0.2
|
||||
<09><><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.3
|
||||
<09><>spi<70><69>uart<72><74>pit<69>в<EFBFBD><D0B2>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>volatile<6C><65><EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><>spi<70><69>uart<72><74>pit<69>в<EFBFBD><D0B2>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>volatile<6C><65><EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.4
|
||||
Ĭ<>Ϲ<EFBFBD>ѡ<EFBFBD><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HEX<45>Ĺ<EFBFBD><C4B9><EFBFBD>
|
||||
<09><>Cpu1_Main.c<>е<EFBFBD>core1_main<69><6E><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϵĺ<CFB5><C4BA><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>CPU1<55><EFBFBD><DEB7><EFBFBD>Ӧ<EFBFBD>жϵ<D0B6><CFB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
ɾ<><C9BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>еİ<D0B5><C4B0><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD>Ϣ
|
||||
<09><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD>ֱ<EFBFBD>ֻ<EFBFBD>ɼ<EFBFBD>һ<EFBFBD>ε<EFBFBD><CEB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>LSL<53>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>#pragma <20><>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߳<EFBFBD><DFB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>RAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ο<EFBFBD><CEBF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Specifies_Variable_Or_Code_Location_Demo
|
||||
//ʹ<><CAB9>#pragma section all "cpu0_dsram" <20><> #pragma section all restore<72><65><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram
|
||||
//<2F><><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>仰<EFBFBD>м伴<D0BC>ɣ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
#pragma section all "cpu0_dsram"
|
||||
uint8 test_arry[5]; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D>Ϊcpu1_dsram <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu1_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>CPUִ<55>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>õı<C3B5><C4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu1_dsram<61><6D><EFBFBD><EFBFBD>
|
||||
#pragma section all restore
|
||||
|
||||
//ʹ<><CAB9>#pragma section all "cpu0_psram" <20><> #pragma section all restore<72><65><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu0_psram
|
||||
//<2F><><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>仰<EFBFBD>м伴<D0BC>ɣ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
#pragma section all "cpu0_psram"
|
||||
void delay_tset(void) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu0_psram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4>
|
||||
{
|
||||
int i;
|
||||
i = 999;
|
||||
while(i--);
|
||||
}
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_psram<61><6D>Ϊcpu1_psram <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu1_psram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>CPUִ<55>У<EFBFBD><D0A3><EFBFBD><F2BDABBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>£<EFBFBD><C2A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ǵ<EFBFBD>flash<73><68><EFBFBD>ز<EFBFBD>ִ<EFBFBD><D6B4>
|
||||
//ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAM<41><4D><EFBFBD>У<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD>еij<D0B5><C4B3><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cache<68><EFBFBD><F3A3ACBB><EFBFBD><EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD>ٶȽ<D9B6><C8BD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ǾͿ<C7BE><CDBF>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAMִ<4D>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٶ<EFBFBD>
|
||||
#pragma section all restore
|
||||
|
||||
|
||||
@@ -24,7 +24,7 @@
|
||||
|
||||
uint8 camera_type; //<2F><><EFBFBD><EFBFBD>ͷ<EFBFBD>ͺ<EFBFBD> 1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 2<><32><EFBFBD><EFBFBD>ͫ<EFBFBD><CDAB><EFBFBD><EFBFBD>δ֧<CEB4>֣<EFBFBD>3<EFBFBD><33>С<EFBFBD><D0A1><EFBFBD><EFBFBD>
|
||||
|
||||
|
||||
uint32 te;
|
||||
|
||||
App_Cpu0 g_AppCpu0; //Ƶ<><C6B5><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>
|
||||
void get_clk(void)
|
||||
@@ -40,4 +40,6 @@ void get_clk(void)
|
||||
g_AppCpu0.info.cpuFreq = IfxScuCcu_getCpuFrequency(IfxCpu_getCoreIndex());
|
||||
g_AppCpu0.info.sysFreq = IfxScuCcu_getSpbFrequency();
|
||||
g_AppCpu0.info.stmFreq = IfxStm_getFrequency(&MODULE_STM0);
|
||||
|
||||
te = IfxScuCcu_getSriFrequency();
|
||||
}
|
||||
|
||||
@@ -63,6 +63,7 @@
|
||||
#include "SEEKFREE_WIRELESS.h"
|
||||
#include "SEEKFREE_IPS200_PARALLEL8.h"
|
||||
#include "SEEKFREE_7725.h"
|
||||
#include "SEEKFREE_RDA5807.h"
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -50,7 +50,6 @@ void pit_init(CCU6N_enum ccu6n, CCU6_CHN_enum pit_ch, uint32 time);
|
||||
|
||||
|
||||
//------------------------------------<2D><><EFBFBD>´<EFBFBD><C2B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PIT<49>ж<EFBFBD>------------------------------------
|
||||
//-----------------<2D><><EFBFBD>ñ<EFBFBD><C3B1>꺯<EFBFBD><EABAAF>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD>pit_init<69><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Գ<EFBFBD>ʼ<EFBFBD><CABC>PIT<49><54><EFBFBD><EFBFBD>-------------------
|
||||
#define pit_interrupt_ms(ccu6n, pit_ch, time) pit_init(ccu6n, pit_ch, time*1000) //(<28><>λΪ <20><><EFBFBD><EFBFBD>)
|
||||
#define pit_interrupt_us(ccu6n, pit_ch, time) pit_init(ccu6n, pit_ch, time) //(<28><>λΪ <><CEA2>)
|
||||
|
||||
|
||||
@@ -314,6 +314,7 @@ void mt9v03x_init(void)
|
||||
|
||||
|
||||
uint8 mt9v03x_finish_flag = 0; //һ<><D2BB>ͼ<EFBFBD><CDBC><EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD>ɱ<EFBFBD>־λ
|
||||
uint8 mt9v03x_dma_int_num; //<2F><>ǰDMA<4D>жϴ<D0B6><CFB4><EFBFBD>
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief MT9V03X<33><58><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>ж<EFBFBD>
|
||||
// @param NULL
|
||||
@@ -324,15 +325,20 @@ uint8 mt9v03x_finish_flag = 0; //һ
|
||||
void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
|
||||
mt9v03x_dma_int_num = 0;
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
if(1 == link_list_num)
|
||||
{
|
||||
//û<>в<EFBFBD><D0B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӵ<EFBFBD><D3B4><EFBFBD>ģʽ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD>ĵ<EFBFBD>ַ
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, mt9v03x_image[0]);
|
||||
}
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
uint8 mt9v03x_dma_int_num; //<2F><>ǰDMA<4D>жϴ<D0B6><CFB4><EFBFBD>
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief MT9V03X<33><58><EFBFBD><EFBFBD>ͷDMA<4D><41><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
||||
// @param NULL
|
||||
|
||||
@@ -0,0 +1,220 @@
|
||||
/*********************************************************************************************************************
|
||||
* COPYRIGHT NOTICE
|
||||
* Copyright (c) 2020,<2C><><EFBFBD>ɿƼ<C9BF>
|
||||
* All rights reserved.
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>QQȺ<51><C8BA><EFBFBD><EFBFBD>Ⱥ<EFBFBD><C8BA>824575535
|
||||
*
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD>У<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҵ<EFBFBD><D2B5>;<EFBFBD><CDBE>
|
||||
* <20><>ӭ<EFBFBD><D3AD>λʹ<CEBB>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>뱣<EFBFBD><EBB1A3><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC>İ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*
|
||||
* @file MPU6050
|
||||
* @company <09>ɶ<EFBFBD><C9B6><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD><EFBFBD>˾
|
||||
* @author <09><><EFBFBD>ɿƼ<C9BF>(QQ3184284598)
|
||||
* @version <09>鿴doc<6F><63>version<6F>ļ<EFBFBD> <20>汾˵<E6B1BE><CBB5>
|
||||
* @Software tasking v6.3r1
|
||||
* @Target core TC264D
|
||||
* @Taobao https://seekfree.taobao.com/
|
||||
* @date 2020-3-23
|
||||
* @note
|
||||
<09><><EFBFBD>߶<EFBFBD><DFB6>壺
|
||||
------------------------------------
|
||||
<09><><EFBFBD><EFBFBD>IIC
|
||||
SCL <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SCL<43>궨<EFBFBD><EAB6A8>
|
||||
SDA <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SDA<44>궨<EFBFBD><EAB6A8>
|
||||
|
||||
Ӳ<><D3B2>IIC
|
||||
SCL <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
SDA <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
------------------------------------
|
||||
ע<><D7A2><EFBFBD><EFBFBD><EFBFBD>RDA5807<30><37>SCL<43><4C>SDA<44><41><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>1K<31><4B><EFBFBD><EFBFBD>Ȼ<EFBFBD><C8BB><EFBFBD><EFBFBD><EFBFBD>뵥Ƭ<EBB5A5><C6AC><EFBFBD><EFBFBD><EFBFBD>ӣ<EFBFBD><D3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
|
||||
********************************************************************************************************************/
|
||||
|
||||
|
||||
|
||||
#include "SEEKFREE_IIC.h"
|
||||
#include "zf_stm_systick.h"
|
||||
#include "SEEKFREE_RDA5807.h"
|
||||
|
||||
|
||||
#define ack 1 //<2F><>Ӧ<EFBFBD><D3A6>
|
||||
#define no_ack 0 //<2F><>Ӧ<EFBFBD><D3A6>
|
||||
|
||||
|
||||
#define FM_ADDRESS 0x20>>1
|
||||
|
||||
uint8 rda5807_config_reg[] = {
|
||||
0xc1, 0x03, // Register 0x2
|
||||
0x00, 0x00, // Register 0x3
|
||||
0x0a, 0x00, // Register 0x4
|
||||
0x88, 0x0f, // Register 0x5
|
||||
0x00, 0x00, // Register 0x6
|
||||
0x42, 0x02, // Register 0x7
|
||||
};
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807ģ<37><C4A3>IIC<49><43>ȡ<EFBFBD><C8A1><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @param dev_add <09>豸<EFBFBD><E8B1B8>ַ(<28><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>ַ)
|
||||
// @param data[] <09><><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD>ĵ<EFBFBD>ַָ<D6B7><D6B8>
|
||||
// @param num <09><>ȡ<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rad5807m_simiic_write(uint8 dev_add, uint8 data[], uint8 num)
|
||||
{
|
||||
uint8 i;
|
||||
simiic_start();
|
||||
send_ch( (dev_add<<1) | 0x00); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>дλ
|
||||
|
||||
for(i=0;i<num;i++)
|
||||
send_ch(data[i]); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
simiic_stop();
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief ģ<><C4A3>IIC<49><43>ȡ<EFBFBD><C8A1><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @param dev_add <09>豸<EFBFBD><E8B1B8>ַ(<28><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>ַ)
|
||||
// @param dat_add <09><><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD>ĵ<EFBFBD>ַָ<D6B7><D6B8>
|
||||
// @param num <09><>ȡ<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @return uint8 <09><><EFBFBD>ؼĴ<D8BC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807m_simiic_read(uint8 dev_add,uint8 *dat_add,uint8 num)
|
||||
{
|
||||
simiic_start();
|
||||
|
||||
send_ch( (dev_add<<1) | 0x01); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD>Ӷ<EFBFBD>λ
|
||||
while(--num)
|
||||
{
|
||||
*dat_add = read_ch(ack); //<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
|
||||
dat_add++;
|
||||
|
||||
}
|
||||
*dat_add = read_ch(no_ack); //<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
|
||||
|
||||
simiic_stop();
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief Ƶ<>ʼĴ<CABC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3>ڲ<EFBFBD>ʹ<EFBFBD>ã<EFBFBD><C3A3>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD>
|
||||
// @param channel Ƶ<>ʼĴ<CABC><C4B4><EFBFBD>ֵ
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_channel_config(uint16 reg_chn)
|
||||
{
|
||||
rda5807_config_reg[0] = 0xc0;
|
||||
rda5807_config_reg[1] = 0x01;
|
||||
rda5807_config_reg[2] = (uint8)(reg_chn >> 2);
|
||||
rda5807_config_reg[3] = (uint8)(((reg_chn & 0x3) << 6) | 0x18);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5> <09><><EFBFBD>ڲ<EFBFBD>ʹ<EFBFBD>ã<EFBFBD><C3A3>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD>
|
||||
// @param freq Ƶ<><C6B5>ֵ
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_set_channel(float freq)
|
||||
{
|
||||
uint16 reg_chn=0;
|
||||
reg_chn = (int)((freq - 76.0) * 10.0 + 0.5);
|
||||
rda5807_channel_config(reg_chn);
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg, 4);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ģʽ
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_set_idle(void)
|
||||
{
|
||||
rda5807_config_reg[1] &= ~(1<<0);//Power Up Disabled.
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg, 4);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ģʽ
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_set_transimt(void)
|
||||
{
|
||||
rda5807_config_reg[1] |= 1<<0;//Power Up Enable.
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg, 4);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
uint8 rda5807_read_reg[10];
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37>ȡID<49><44><EFBFBD>ڲ<EFBFBD>ʹ<EFBFBD>ã<EFBFBD><C3A3>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD>
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_read_id(void)
|
||||
{
|
||||
rda5807m_simiic_read(FM_ADDRESS,rda5807_read_reg,10);
|
||||
}
|
||||
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37>ʼ<EFBFBD><CABC>
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_init(float freq)
|
||||
{
|
||||
uint8 dat[2] = {0x00,0x02};
|
||||
|
||||
|
||||
//iic<69><63>ʼ<EFBFBD><CABC>
|
||||
simiic_init();
|
||||
simiic_delay_set(100);//<2F><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>IIC<49><43>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ΪĬ<CEAA><C4AC><EFBFBD><EFBFBD><EFBFBD>ʽϸ<CABD>
|
||||
//<2F><>λ
|
||||
rad5807m_simiic_write(FM_ADDRESS,dat,2);
|
||||
|
||||
systick_delay_ms(STM0, 600);
|
||||
|
||||
while(rda5807_read_reg[8] != 0x58)
|
||||
{
|
||||
//<2F><>ȡ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Լ졣
|
||||
rda5807m_simiic_read(FM_ADDRESS,rda5807_read_reg,10);
|
||||
systick_delay_ms(STM0, 50);
|
||||
//<2F><><EFBFBD><EFBFBD>һֱ<D2BB><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>鿴SCL<43><4C>SDA<44>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD>Ӻá<D3BA>
|
||||
//<2F><>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>SEEKFREE_IIC.h<>ļ<EFBFBD><C4BC>е<EFBFBD>SIMIIC_DELAY_TIMEֵ<45><D6B5><EFBFBD><EFBFBD>60
|
||||
}
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD>
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg,sizeof(rda5807_config_reg));
|
||||
//Ƶ<><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
rda5807_set_channel(freq);
|
||||
|
||||
simiic_delay_set(SIMIIC_DELAY_TIME);//<2F><>ԭģ<D4AD><C4A3>IICĬ<43><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,56 @@
|
||||
/*********************************************************************************************************************
|
||||
* COPYRIGHT NOTICE
|
||||
* Copyright (c) 2020,<2C><><EFBFBD>ɿƼ<C9BF>
|
||||
* All rights reserved.
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>QQȺ<51><C8BA><EFBFBD><EFBFBD>Ⱥ<EFBFBD><C8BA>824575535
|
||||
*
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD>У<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҵ<EFBFBD><D2B5>;<EFBFBD><CDBE>
|
||||
* <20><>ӭ<EFBFBD><D3AD>λʹ<CEBB>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>뱣<EFBFBD><EBB1A3><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC>İ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*
|
||||
* @file MPU6050
|
||||
* @company <09>ɶ<EFBFBD><C9B6><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD><EFBFBD>˾
|
||||
* @author <09><><EFBFBD>ɿƼ<C9BF>(QQ3184284598)
|
||||
* @version <09>鿴doc<6F><63>version<6F>ļ<EFBFBD> <20>汾˵<E6B1BE><CBB5>
|
||||
* @Software tasking v6.3r1
|
||||
* @Target core TC264D
|
||||
* @Taobao https://seekfree.taobao.com/
|
||||
* @date 2020-3-23
|
||||
* @note
|
||||
<09><><EFBFBD>߶<EFBFBD><DFB6>壺
|
||||
------------------------------------
|
||||
<09><><EFBFBD><EFBFBD>IIC
|
||||
SCL <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SCL<43>궨<EFBFBD><EAB6A8>
|
||||
SDA <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SDA<44>궨<EFBFBD><EAB6A8>
|
||||
|
||||
Ӳ<><D3B2>IIC
|
||||
SCL <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
SDA <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
------------------------------------
|
||||
ע<><D7A2><EFBFBD><EFBFBD><EFBFBD>RDA5807<30><37>SCL<43><4C>SDA<44><41><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>1K<31><4B><EFBFBD><EFBFBD>Ȼ<EFBFBD><C8BB><EFBFBD><EFBFBD><EFBFBD>뵥Ƭ<EBB5A5><C6AC><EFBFBD><EFBFBD><EFBFBD>ӣ<EFBFBD><D3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
|
||||
********************************************************************************************************************/
|
||||
|
||||
|
||||
#ifndef _FM5807_H
|
||||
#define _FM5807_H
|
||||
#include "common.h"
|
||||
#include "SEEKFREE_FONT.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void rda5807_init(float freq);
|
||||
void rda5807_set_transimt(void);
|
||||
void rda5807_set_idle(void);
|
||||
void rda5807_set_channel(float freq);
|
||||
void rda5807_channel_config(uint16 reg_chn);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -19,6 +19,7 @@
|
||||
|
||||
|
||||
#include "headfile.h"
|
||||
#pragma section all "cpu0_dsram"
|
||||
|
||||
uint16 time;
|
||||
|
||||
@@ -42,3 +43,4 @@ int core0_main(void)
|
||||
}
|
||||
}
|
||||
|
||||
#pragma section all restore
|
||||
@@ -18,14 +18,19 @@
|
||||
********************************************************************************************************************/
|
||||
|
||||
#include "headfile.h"
|
||||
#pragma section all "cpu1_dsram"
|
||||
|
||||
|
||||
|
||||
|
||||
void core1_main(void)
|
||||
{
|
||||
disableInterrupts();
|
||||
IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
|
||||
|
||||
//<2F>û<EFBFBD><C3BB>ڴ˴<DAB4><CBB4><EFBFBD><EFBFBD>ø<EFBFBD><C3B8>ֳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
enableInterrupts();
|
||||
while (TRUE)
|
||||
{
|
||||
//<2F>û<EFBFBD><C3BB>ڴ˴<DAB4><CBB4><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
@@ -33,3 +38,9 @@ void core1_main(void)
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#pragma section all restore
|
||||
|
||||
@@ -20,28 +20,30 @@
|
||||
|
||||
#include "isr_config.h"
|
||||
#include "isr.h"
|
||||
//<2F><>isr.c<><63><EFBFBD>жϺ<D0B6><CFBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĵڶ<C4B5><DAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̶<EFBFBD>Ϊ0<CEAA><30><EFBFBD>벻Ҫ<EBB2BB><D2AA><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD>CPU1<55><31><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>Ҳ<EFBFBD><D2B2>Ҫ<EFBFBD><D2AA><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD>ҪCPU1<55><31><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA>isr_config.h<><68><EFBFBD>Ķ<DEB8>Ӧ<EFBFBD>ĺ궨<C4BA>弴<EFBFBD><E5BCB4>
|
||||
|
||||
|
||||
//PIT<49>жϺ<D0B6><CFBA><EFBFBD> ʾ<><CABE>
|
||||
IFX_INTERRUPT(cc60_pit_ch0_isr, CCU6_0_CH0_INT_SERVICE, CCU6_0_CH0_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc60_pit_ch0_isr, 0, CCU6_0_CH0_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_0, PIT_CH0);
|
||||
|
||||
}
|
||||
|
||||
|
||||
IFX_INTERRUPT(cc60_pit_ch1_isr, CCU6_0_CH1_INT_SERVICE, CCU6_0_CH1_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc60_pit_ch1_isr, 0, CCU6_0_CH1_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_0, PIT_CH1);
|
||||
|
||||
}
|
||||
|
||||
IFX_INTERRUPT(cc61_pit_ch0_isr, CCU6_1_CH0_INT_SERVICE, CCU6_1_CH0_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc61_pit_ch0_isr, 0, CCU6_1_CH0_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_1, PIT_CH0);
|
||||
|
||||
}
|
||||
|
||||
IFX_INTERRUPT(cc61_pit_ch1_isr, CCU6_1_CH1_INT_SERVICE, CCU6_1_CH1_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc61_pit_ch1_isr, 0, CCU6_1_CH1_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_1, PIT_CH1);
|
||||
|
||||
@@ -50,7 +52,7 @@ IFX_INTERRUPT(cc61_pit_ch1_isr, CCU6_1_CH1_INT_SERVICE, CCU6_1_CH1_ISR_PRIORITY)
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(eru_ch0_ch4_isr, ERU_CH0_CH4_INT_SERVICE, ERU_CH0_CH4_INT_PRIO)
|
||||
IFX_INTERRUPT(eru_ch0_ch4_isr, 0, ERU_CH0_CH4_INT_PRIO)
|
||||
{
|
||||
if(GET_GPIO_FLAG(ERU_CH0_REQ4_P10_7))//ͨ<><CDA8>0<EFBFBD>ж<EFBFBD>
|
||||
{
|
||||
@@ -63,7 +65,7 @@ IFX_INTERRUPT(eru_ch0_ch4_isr, ERU_CH0_CH4_INT_SERVICE, ERU_CH0_CH4_INT_PRIO)
|
||||
}
|
||||
}
|
||||
|
||||
IFX_INTERRUPT(eru_ch1_ch5_isr, ERU_CH1_CH5_INT_SERVICE, ERU_CH1_CH5_INT_PRIO)
|
||||
IFX_INTERRUPT(eru_ch1_ch5_isr, 0, ERU_CH1_CH5_INT_PRIO)
|
||||
{
|
||||
if(GET_GPIO_FLAG(ERU_CH1_REQ5_P10_8))//ͨ<><CDA8>1<EFBFBD>ж<EFBFBD>
|
||||
{
|
||||
@@ -77,7 +79,7 @@ IFX_INTERRUPT(eru_ch1_ch5_isr, ERU_CH1_CH5_INT_SERVICE, ERU_CH1_CH5_INT_PRIO)
|
||||
}
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷpclk<6C><6B><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC>ռ<EFBFBD><D5BC><EFBFBD><EFBFBD> 2ͨ<32><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD><DAB4><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ﲻ<EFBFBD>ٶ<EFBFBD><D9B6><EFBFBD><EFBFBD>жϺ<D0B6><CFBA><EFBFBD>
|
||||
//IFX_INTERRUPT(eru_ch2_ch6_isr, ERU_CH2_CH6_INT_SERVICE, ERU_CH2_CH6_INT_PRIO)
|
||||
//IFX_INTERRUPT(eru_ch2_ch6_isr, 0, ERU_CH2_CH6_INT_PRIO)
|
||||
//{
|
||||
// if(GET_GPIO_FLAG(ERU_CH2_REQ7_P00_4))//ͨ<><CDA8>2<EFBFBD>ж<EFBFBD>
|
||||
// {
|
||||
@@ -93,7 +95,7 @@ IFX_INTERRUPT(eru_ch1_ch5_isr, ERU_CH1_CH5_INT_SERVICE, ERU_CH1_CH5_INT_PRIO)
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(eru_ch3_ch7_isr, ERU_CH3_CH7_INT_SERVICE, ERU_CH3_CH7_INT_PRIO)
|
||||
IFX_INTERRUPT(eru_ch3_ch7_isr, 0, ERU_CH3_CH7_INT_PRIO)
|
||||
{
|
||||
if(GET_GPIO_FLAG(ERU_CH3_REQ6_P02_0))//ͨ<><CDA8>3<EFBFBD>ж<EFBFBD>
|
||||
{
|
||||
@@ -111,7 +113,7 @@ IFX_INTERRUPT(eru_ch3_ch7_isr, ERU_CH3_CH7_INT_SERVICE, ERU_CH3_CH7_INT_PRIO)
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(dma_ch5_isr, ERU_DMA_INT_SERVICE, ERU_DMA_INT_PRIO)
|
||||
IFX_INTERRUPT(dma_ch5_isr, 0, ERU_DMA_INT_PRIO)
|
||||
{
|
||||
|
||||
if (1 == camera_type) mt9v03x_dma();
|
||||
@@ -120,61 +122,61 @@ IFX_INTERRUPT(dma_ch5_isr, ERU_DMA_INT_SERVICE, ERU_DMA_INT_PRIO)
|
||||
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD>жϺ<D0B6><CFBA><EFBFBD> ʾ<><CABE>
|
||||
IFX_INTERRUPT(uart0_tx_isr, UART0_INT_SERVICE, UART0_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart0_tx_isr, 0, UART0_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart0_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart0_rx_isr, UART0_INT_SERVICE, UART0_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart0_rx_isr, 0, UART0_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart0_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart0_er_isr, UART0_INT_SERVICE, UART0_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart0_er_isr, 0, UART0_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart0_handle);
|
||||
}
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD>1Ĭ<31><C4AC><EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD><D3B5><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>ô<EFBFBD><C3B4><EFBFBD>
|
||||
IFX_INTERRUPT(uart1_tx_isr, UART1_INT_SERVICE, UART1_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart1_tx_isr, 0, UART1_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart1_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart1_rx_isr, UART1_INT_SERVICE, UART1_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart1_rx_isr, 0, UART1_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart1_handle);
|
||||
mt9v03x_uart_callback();
|
||||
}
|
||||
IFX_INTERRUPT(uart1_er_isr, UART1_INT_SERVICE, UART1_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart1_er_isr, 0, UART1_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart1_handle);
|
||||
}
|
||||
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD>2Ĭ<32><C4AC><EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD><D3B5><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>
|
||||
IFX_INTERRUPT(uart2_tx_isr, UART2_INT_SERVICE, UART2_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart2_tx_isr, 0, UART2_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart2_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart2_rx_isr, UART2_INT_SERVICE, UART2_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart2_rx_isr, 0, UART2_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart2_handle);
|
||||
wireless_uart_callback();
|
||||
}
|
||||
IFX_INTERRUPT(uart2_er_isr, UART2_INT_SERVICE, UART2_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart2_er_isr, 0, UART2_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart2_handle);
|
||||
}
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(uart3_tx_isr, UART3_INT_SERVICE, UART3_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart3_tx_isr, 0, UART3_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart3_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart3_rx_isr, UART3_INT_SERVICE, UART3_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart3_rx_isr, 0, UART3_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart3_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart3_er_isr, UART3_INT_SERVICE, UART3_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart3_er_isr, 0, UART3_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart3_handle);
|
||||
}
|
||||
|
||||
@@ -170,88 +170,6 @@
|
||||
</tool>
|
||||
<tool id="com.tasking.ctc.as.abs.debug.1390239146" name="Assembler" superClass="com.tasking.ctc.as.abs.debug">
|
||||
<option id="com.tasking.ctc.as.includePaths.1708708624" name="Include paths" superClass="com.tasking.ctc.as.includePaths" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Config}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Cfg_Illd}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Demo_Illd}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Main}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/CStart}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/Irq}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu/Trap}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Config}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Config/Common}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Cfg_Illd}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Demo_Illd}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/0_Src/AppSw/Tricore/Main}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/Doc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/AppSw/Doc/Source}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Build}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Impl}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Lib}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Lib/DataHandling}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_Lib/InternalMux}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/_PinMap}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Asclin}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Ccu6}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cif}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Cpu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Dma}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Dsadc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Dts}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Emem}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Eray}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Eth}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Fce}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Fft}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Flash}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Gpt12}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Gtm}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Hssl}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/I2c}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Iom}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Msc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Mtu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Multican}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Port}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Psi5}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Psi5s}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Qspi}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Scu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Sent}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Smu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Src}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Stm}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/iLLD/TC26B/Tricore/Vadc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Platform}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Platform/Tricore}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Platform/Tricore/Compilers}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Sfr}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Sfr/TC26B}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Infra/Sfr/TC26B/_Reg}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/_Utilities}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/If}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/If/Ccu6If}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/StdIf}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Bsp}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Comm}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/General}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Math}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/src/BaseSw/Service/CpuGeneric/SysSe/Time}""/>
|
||||
</option>
|
||||
<inputType id="com.tasking.ctc.asmInputType.1471959711" name="ASM" superClass="com.tasking.ctc.asmInputType"/>
|
||||
</tool>
|
||||
|
||||
@@ -270,12 +270,19 @@ derivative tc26
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
@@ -413,6 +420,7 @@ derivative tc26
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
|
||||
@@ -17,4 +17,35 @@ V1.0.2
|
||||
<09><><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.3
|
||||
<09><>spi<70><69>uart<72><74>pit<69>в<EFBFBD><D0B2>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>volatile<6C><65><EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><>spi<70><69>uart<72><74>pit<69>в<EFBFBD><D0B2>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>volatile<6C><65><EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.4
|
||||
Ĭ<>Ϲ<EFBFBD>ѡ<EFBFBD><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HEX<45>Ĺ<EFBFBD><C4B9><EFBFBD>
|
||||
<09><>Cpu1_Main.c<>е<EFBFBD>core1_main<69><6E><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϵĺ<CFB5><C4BA><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>CPU1<55><EFBFBD><DEB7><EFBFBD>Ӧ<EFBFBD>жϵ<D0B6><CFB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
ɾ<><C9BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>еİ<D0B5><C4B0><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD>Ϣ
|
||||
<09><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD>ֱ<EFBFBD>ֻ<EFBFBD>ɼ<EFBFBD>һ<EFBFBD>ε<EFBFBD><CEB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>LSL<53>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>#pragma <20><>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߳<EFBFBD><DFB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>RAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ο<EFBFBD><CEBF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Specifies_Variable_Or_Code_Location_Demo
|
||||
//ʹ<><CAB9>#pragma section all "cpu0_dsram" <20><> #pragma section all restore<72><65><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram
|
||||
//<2F><><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>仰<EFBFBD>м伴<D0BC>ɣ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
#pragma section all "cpu0_dsram"
|
||||
uint8 test_arry[5]; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D>Ϊcpu1_dsram <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu1_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>CPUִ<55>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>õı<C3B5><C4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu1_dsram<61><6D><EFBFBD><EFBFBD>
|
||||
#pragma section all restore
|
||||
|
||||
//ʹ<><CAB9>#pragma section all "cpu0_psram" <20><> #pragma section all restore<72><65><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu0_psram
|
||||
//<2F><><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>仰<EFBFBD>м伴<D0BC>ɣ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
#pragma section all "cpu0_psram"
|
||||
void delay_tset(void) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu0_psram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4>
|
||||
{
|
||||
int i;
|
||||
i = 999;
|
||||
while(i--);
|
||||
}
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_psram<61><6D>Ϊcpu1_psram <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu1_psram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>CPUִ<55>У<EFBFBD><D0A3><EFBFBD><F2BDABBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>£<EFBFBD><C2A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ǵ<EFBFBD>flash<73><68><EFBFBD>ز<EFBFBD>ִ<EFBFBD><D6B4>
|
||||
//ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAM<41><4D><EFBFBD>У<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD>еij<D0B5><C4B3><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cache<68><EFBFBD><F3A3ACBB><EFBFBD><EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD>ٶȽ<D9B6><C8BD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ǾͿ<C7BE><CDBF>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAMִ<4D>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٶ<EFBFBD>
|
||||
#pragma section all restore
|
||||
|
||||
|
||||
@@ -24,7 +24,7 @@
|
||||
|
||||
uint8 camera_type; //<2F><><EFBFBD><EFBFBD>ͷ<EFBFBD>ͺ<EFBFBD> 1<><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 2<><32><EFBFBD><EFBFBD>ͫ<EFBFBD><CDAB><EFBFBD><EFBFBD>δ֧<CEB4>֣<EFBFBD>3<EFBFBD><33>С<EFBFBD><D0A1><EFBFBD><EFBFBD>
|
||||
|
||||
|
||||
uint32 te;
|
||||
|
||||
App_Cpu0 g_AppCpu0; //Ƶ<><C6B5><EFBFBD><EFBFBD>Ϣ<EFBFBD><CFA2><EFBFBD><EFBFBD>
|
||||
void get_clk(void)
|
||||
@@ -40,4 +40,6 @@ void get_clk(void)
|
||||
g_AppCpu0.info.cpuFreq = IfxScuCcu_getCpuFrequency(IfxCpu_getCoreIndex());
|
||||
g_AppCpu0.info.sysFreq = IfxScuCcu_getSpbFrequency();
|
||||
g_AppCpu0.info.stmFreq = IfxStm_getFrequency(&MODULE_STM0);
|
||||
|
||||
te = IfxScuCcu_getSriFrequency();
|
||||
}
|
||||
|
||||
@@ -63,6 +63,7 @@
|
||||
#include "SEEKFREE_WIRELESS.h"
|
||||
#include "SEEKFREE_IPS200_PARALLEL8.h"
|
||||
#include "SEEKFREE_7725.h"
|
||||
#include "SEEKFREE_RDA5807.h"
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -50,7 +50,6 @@ void pit_init(CCU6N_enum ccu6n, CCU6_CHN_enum pit_ch, uint32 time);
|
||||
|
||||
|
||||
//------------------------------------<2D><><EFBFBD>´<EFBFBD><C2B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PIT<49>ж<EFBFBD>------------------------------------
|
||||
//-----------------<2D><><EFBFBD>ñ<EFBFBD><C3B1>꺯<EFBFBD><EABAAF>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȵ<EFBFBD><C8B5><EFBFBD>pit_init<69><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Գ<EFBFBD>ʼ<EFBFBD><CABC>PIT<49><54><EFBFBD><EFBFBD>-------------------
|
||||
#define pit_interrupt_ms(ccu6n, pit_ch, time) pit_init(ccu6n, pit_ch, time*1000) //(<28><>λΪ <20><><EFBFBD><EFBFBD>)
|
||||
#define pit_interrupt_us(ccu6n, pit_ch, time) pit_init(ccu6n, pit_ch, time) //(<28><>λΪ <><CEA2>)
|
||||
|
||||
|
||||
@@ -314,6 +314,7 @@ void mt9v03x_init(void)
|
||||
|
||||
|
||||
uint8 mt9v03x_finish_flag = 0; //һ<><D2BB>ͼ<EFBFBD><CDBC><EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD>ɱ<EFBFBD>־λ
|
||||
uint8 mt9v03x_dma_int_num; //<2F><>ǰDMA<4D>жϴ<D0B6><CFB4><EFBFBD>
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief MT9V03X<33><58><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>ж<EFBFBD>
|
||||
// @param NULL
|
||||
@@ -324,15 +325,20 @@ uint8 mt9v03x_finish_flag = 0; //һ
|
||||
void mt9v03x_vsync(void)
|
||||
{
|
||||
CLEAR_GPIO_FLAG(MT9V03X_VSYNC_PIN);
|
||||
|
||||
mt9v03x_dma_int_num = 0;
|
||||
if(!mt9v03x_finish_flag)//<2F>鿴ͼ<E9BFB4><CDBC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>δʹ<CEB4><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD>ɼ<EFBFBD><C9BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
{
|
||||
if(1 == link_list_num)
|
||||
{
|
||||
//û<>в<EFBFBD><D0B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӵ<EFBFBD><D3B4><EFBFBD>ģʽ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD>ĵ<EFBFBD>ַ
|
||||
DMA_SET_DESTINATION(MT9V03X_DMA_CH, mt9v03x_image[0]);
|
||||
}
|
||||
dma_start(MT9V03X_DMA_CH);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
uint8 mt9v03x_dma_int_num; //<2F><>ǰDMA<4D>жϴ<D0B6><CFB4><EFBFBD>
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief MT9V03X<33><58><EFBFBD><EFBFBD>ͷDMA<4D><41><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
|
||||
// @param NULL
|
||||
|
||||
@@ -0,0 +1,220 @@
|
||||
/*********************************************************************************************************************
|
||||
* COPYRIGHT NOTICE
|
||||
* Copyright (c) 2020,<2C><><EFBFBD>ɿƼ<C9BF>
|
||||
* All rights reserved.
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>QQȺ<51><C8BA><EFBFBD><EFBFBD>Ⱥ<EFBFBD><C8BA>824575535
|
||||
*
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD>У<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҵ<EFBFBD><D2B5>;<EFBFBD><CDBE>
|
||||
* <20><>ӭ<EFBFBD><D3AD>λʹ<CEBB>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>뱣<EFBFBD><EBB1A3><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC>İ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*
|
||||
* @file MPU6050
|
||||
* @company <09>ɶ<EFBFBD><C9B6><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD><EFBFBD>˾
|
||||
* @author <09><><EFBFBD>ɿƼ<C9BF>(QQ3184284598)
|
||||
* @version <09>鿴doc<6F><63>version<6F>ļ<EFBFBD> <20>汾˵<E6B1BE><CBB5>
|
||||
* @Software tasking v6.3r1
|
||||
* @Target core TC264D
|
||||
* @Taobao https://seekfree.taobao.com/
|
||||
* @date 2020-3-23
|
||||
* @note
|
||||
<09><><EFBFBD>߶<EFBFBD><DFB6>壺
|
||||
------------------------------------
|
||||
<09><><EFBFBD><EFBFBD>IIC
|
||||
SCL <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SCL<43>궨<EFBFBD><EAB6A8>
|
||||
SDA <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SDA<44>궨<EFBFBD><EAB6A8>
|
||||
|
||||
Ӳ<><D3B2>IIC
|
||||
SCL <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
SDA <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
------------------------------------
|
||||
ע<><D7A2><EFBFBD><EFBFBD><EFBFBD>RDA5807<30><37>SCL<43><4C>SDA<44><41><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>1K<31><4B><EFBFBD><EFBFBD>Ȼ<EFBFBD><C8BB><EFBFBD><EFBFBD><EFBFBD>뵥Ƭ<EBB5A5><C6AC><EFBFBD><EFBFBD><EFBFBD>ӣ<EFBFBD><D3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
|
||||
********************************************************************************************************************/
|
||||
|
||||
|
||||
|
||||
#include "SEEKFREE_IIC.h"
|
||||
#include "zf_stm_systick.h"
|
||||
#include "SEEKFREE_RDA5807.h"
|
||||
|
||||
|
||||
#define ack 1 //<2F><>Ӧ<EFBFBD><D3A6>
|
||||
#define no_ack 0 //<2F><>Ӧ<EFBFBD><D3A6>
|
||||
|
||||
|
||||
#define FM_ADDRESS 0x20>>1
|
||||
|
||||
uint8 rda5807_config_reg[] = {
|
||||
0xc1, 0x03, // Register 0x2
|
||||
0x00, 0x00, // Register 0x3
|
||||
0x0a, 0x00, // Register 0x4
|
||||
0x88, 0x0f, // Register 0x5
|
||||
0x00, 0x00, // Register 0x6
|
||||
0x42, 0x02, // Register 0x7
|
||||
};
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807ģ<37><C4A3>IIC<49><43>ȡ<EFBFBD><C8A1><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @param dev_add <09>豸<EFBFBD><E8B1B8>ַ(<28><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>ַ)
|
||||
// @param data[] <09><><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD>ĵ<EFBFBD>ַָ<D6B7><D6B8>
|
||||
// @param num <09><>ȡ<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rad5807m_simiic_write(uint8 dev_add, uint8 data[], uint8 num)
|
||||
{
|
||||
uint8 i;
|
||||
simiic_start();
|
||||
send_ch( (dev_add<<1) | 0x00); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>дλ
|
||||
|
||||
for(i=0;i<num;i++)
|
||||
send_ch(data[i]); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
simiic_stop();
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief ģ<><C4A3>IIC<49><43>ȡ<EFBFBD><C8A1><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @param dev_add <09>豸<EFBFBD><E8B1B8>ַ(<28><><EFBFBD><EFBFBD>λ<EFBFBD><CEBB>ַ)
|
||||
// @param dat_add <09><><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD><EFBFBD>ĵ<EFBFBD>ַָ<D6B7><D6B8>
|
||||
// @param num <09><>ȡ<EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @return uint8 <09><><EFBFBD>ؼĴ<D8BC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807m_simiic_read(uint8 dev_add,uint8 *dat_add,uint8 num)
|
||||
{
|
||||
simiic_start();
|
||||
|
||||
send_ch( (dev_add<<1) | 0x01); //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD>Ӷ<EFBFBD>λ
|
||||
while(--num)
|
||||
{
|
||||
*dat_add = read_ch(ack); //<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
|
||||
dat_add++;
|
||||
|
||||
}
|
||||
*dat_add = read_ch(no_ack); //<2F><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD>
|
||||
|
||||
simiic_stop();
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief Ƶ<>ʼĴ<CABC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3>ڲ<EFBFBD>ʹ<EFBFBD>ã<EFBFBD><C3A3>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD>
|
||||
// @param channel Ƶ<>ʼĴ<CABC><C4B4><EFBFBD>ֵ
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_channel_config(uint16 reg_chn)
|
||||
{
|
||||
rda5807_config_reg[0] = 0xc0;
|
||||
rda5807_config_reg[1] = 0x01;
|
||||
rda5807_config_reg[2] = (uint8)(reg_chn >> 2);
|
||||
rda5807_config_reg[3] = (uint8)(((reg_chn & 0x3) << 6) | 0x18);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5> <09><><EFBFBD>ڲ<EFBFBD>ʹ<EFBFBD>ã<EFBFBD><C3A3>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD>
|
||||
// @param freq Ƶ<><C6B5>ֵ
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_set_channel(float freq)
|
||||
{
|
||||
uint16 reg_chn=0;
|
||||
reg_chn = (int)((freq - 76.0) * 10.0 + 0.5);
|
||||
rda5807_channel_config(reg_chn);
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg, 4);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ģʽ
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_set_idle(void)
|
||||
{
|
||||
rda5807_config_reg[1] &= ~(1<<0);//Power Up Disabled.
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg, 4);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ģʽ
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_set_transimt(void)
|
||||
{
|
||||
rda5807_config_reg[1] |= 1<<0;//Power Up Enable.
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg, 4);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
uint8 rda5807_read_reg[10];
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37>ȡID<49><44><EFBFBD>ڲ<EFBFBD>ʹ<EFBFBD>ã<EFBFBD><C3A3>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD>
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_read_id(void)
|
||||
{
|
||||
rda5807m_simiic_read(FM_ADDRESS,rda5807_read_reg,10);
|
||||
}
|
||||
|
||||
|
||||
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
// @brief rda5807<30><37>ʼ<EFBFBD><CABC>
|
||||
// @param NULL
|
||||
// @return void
|
||||
// @since v1.0
|
||||
// Sample usage:
|
||||
//-------------------------------------------------------------------------------------------------------------------
|
||||
void rda5807_init(float freq)
|
||||
{
|
||||
uint8 dat[2] = {0x00,0x02};
|
||||
|
||||
|
||||
//iic<69><63>ʼ<EFBFBD><CABC>
|
||||
simiic_init();
|
||||
simiic_delay_set(100);//<2F><><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>IIC<49><43>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ΪĬ<CEAA><C4AC><EFBFBD><EFBFBD><EFBFBD>ʽϸ<CABD>
|
||||
//<2F><>λ
|
||||
rad5807m_simiic_write(FM_ADDRESS,dat,2);
|
||||
|
||||
systick_delay_ms(STM0, 600);
|
||||
|
||||
while(rda5807_read_reg[8] != 0x58)
|
||||
{
|
||||
//<2F><>ȡ<EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Լ졣
|
||||
rda5807m_simiic_read(FM_ADDRESS,rda5807_read_reg,10);
|
||||
systick_delay_ms(STM0, 50);
|
||||
//<2F><><EFBFBD><EFBFBD>һֱ<D2BB><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>鿴SCL<43><4C>SDA<44>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD>Ӻá<D3BA>
|
||||
//<2F><>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>SEEKFREE_IIC.h<>ļ<EFBFBD><C4BC>е<EFBFBD>SIMIIC_DELAY_TIMEֵ<45><D6B5><EFBFBD><EFBFBD>60
|
||||
}
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD>
|
||||
rad5807m_simiic_write(FM_ADDRESS,rda5807_config_reg,sizeof(rda5807_config_reg));
|
||||
//Ƶ<><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
rda5807_set_channel(freq);
|
||||
|
||||
simiic_delay_set(SIMIIC_DELAY_TIME);//<2F><>ԭģ<D4AD><C4A3>IICĬ<43><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,56 @@
|
||||
/*********************************************************************************************************************
|
||||
* COPYRIGHT NOTICE
|
||||
* Copyright (c) 2020,<2C><><EFBFBD>ɿƼ<C9BF>
|
||||
* All rights reserved.
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>QQȺ<51><C8BA><EFBFBD><EFBFBD>Ⱥ<EFBFBD><C8BA>824575535
|
||||
*
|
||||
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݰ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD>У<EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҵ<EFBFBD><D2B5>;<EFBFBD><CDBE>
|
||||
* <20><>ӭ<EFBFBD><D3AD>λʹ<CEBB>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>뱣<EFBFBD><EBB1A3><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC>İ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
*
|
||||
* @file MPU6050
|
||||
* @company <09>ɶ<EFBFBD><C9B6><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD><EFBFBD>˾
|
||||
* @author <09><><EFBFBD>ɿƼ<C9BF>(QQ3184284598)
|
||||
* @version <09>鿴doc<6F><63>version<6F>ļ<EFBFBD> <20>汾˵<E6B1BE><CBB5>
|
||||
* @Software tasking v6.3r1
|
||||
* @Target core TC264D
|
||||
* @Taobao https://seekfree.taobao.com/
|
||||
* @date 2020-3-23
|
||||
* @note
|
||||
<09><><EFBFBD>߶<EFBFBD><DFB6>壺
|
||||
------------------------------------
|
||||
<09><><EFBFBD><EFBFBD>IIC
|
||||
SCL <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SCL<43>궨<EFBFBD><EAB6A8>
|
||||
SDA <20>鿴SEEKFREE_IIC<49>ļ<EFBFBD><C4BC>ڵ<EFBFBD>SEEKFREE_SDA<44>궨<EFBFBD><EAB6A8>
|
||||
|
||||
Ӳ<><D3B2>IIC
|
||||
SCL <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
SDA <20>鿴init_mpu6050_hardware<72><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ʼ<EFBFBD><CABC>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
------------------------------------
|
||||
ע<><D7A2><EFBFBD><EFBFBD><EFBFBD>RDA5807<30><37>SCL<43><4C>SDA<44><41><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD>1K<31><4B><EFBFBD><EFBFBD>Ȼ<EFBFBD><C8BB><EFBFBD><EFBFBD><EFBFBD>뵥Ƭ<EBB5A5><C6AC><EFBFBD><EFBFBD><EFBFBD>ӣ<EFBFBD><D3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>
|
||||
********************************************************************************************************************/
|
||||
|
||||
|
||||
#ifndef _FM5807_H
|
||||
#define _FM5807_H
|
||||
#include "common.h"
|
||||
#include "SEEKFREE_FONT.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void rda5807_init(float freq);
|
||||
void rda5807_set_transimt(void);
|
||||
void rda5807_set_idle(void);
|
||||
void rda5807_set_channel(float freq);
|
||||
void rda5807_channel_config(uint16 reg_chn);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -19,6 +19,7 @@
|
||||
|
||||
|
||||
#include "headfile.h"
|
||||
#pragma section all "cpu0_dsram"
|
||||
|
||||
uint16 adc_result;
|
||||
|
||||
@@ -42,3 +43,4 @@ int core0_main(void)
|
||||
}
|
||||
}
|
||||
|
||||
#pragma section all restore
|
||||
@@ -18,20 +18,33 @@
|
||||
********************************************************************************************************************/
|
||||
|
||||
#include "headfile.h"
|
||||
#pragma section all "cpu1_dsram"
|
||||
|
||||
|
||||
|
||||
|
||||
void core1_main(void)
|
||||
{
|
||||
disableInterrupts();
|
||||
IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
|
||||
|
||||
//˫<EFBFBD>˵<EFBFBD>ʹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD>ܼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>main<EFBFBD>б<EFBFBD>д<EFBFBD><EFBFBD><EFBFBD>õij<EFBFBD><EFBFBD><EFBFBD>
|
||||
//<EFBFBD>û<EFBFBD><EFBFBD>ڴ˴<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ø<EFBFBD><EFBFBD>ֳ<EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//˫<>˵<EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD>ʵ<EFBFBD>ܼ<DCBC><F2B5A5A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>main<69>б<EFBFBD>д<EFBFBD><D0B4><EFBFBD>õij<C3B5><C4B3><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>ú<EFBFBD><C3BA><EFBFBD>0 <20><>˸P20_8<5F><38>LED <09><><EFBFBD><EFBFBD>1<EFBFBD><31>˸P20_9<5F><39>LED
|
||||
gpio_init(P20_9, GPO, 0, PUSHPULL);
|
||||
|
||||
|
||||
enableInterrupts();
|
||||
while (TRUE)
|
||||
{
|
||||
//<2F>û<EFBFBD><C3BB>ڴ˴<DAB4><CBB4><EFBFBD>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
gpio_toggle(P20_9);
|
||||
systick_delay_ms(STM1, 100);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#pragma section all restore
|
||||
|
||||
@@ -20,28 +20,30 @@
|
||||
|
||||
#include "isr_config.h"
|
||||
#include "isr.h"
|
||||
//<2F><>isr.c<><63><EFBFBD>жϺ<D0B6><CFBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĵڶ<C4B5><DAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̶<EFBFBD>Ϊ0<CEAA><30><EFBFBD>벻Ҫ<EBB2BB><D2AA><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD>CPU1<55><31><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>Ҳ<EFBFBD><D2B2>Ҫ<EFBFBD><D2AA><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD>ҪCPU1<55><31><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA>isr_config.h<><68><EFBFBD>Ķ<DEB8>Ӧ<EFBFBD>ĺ궨<C4BA>弴<EFBFBD><E5BCB4>
|
||||
|
||||
|
||||
//PIT<49>жϺ<D0B6><CFBA><EFBFBD> ʾ<><CABE>
|
||||
IFX_INTERRUPT(cc60_pit_ch0_isr, CCU6_0_CH0_INT_SERVICE, CCU6_0_CH0_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc60_pit_ch0_isr, 0, CCU6_0_CH0_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_0, PIT_CH0);
|
||||
|
||||
}
|
||||
|
||||
|
||||
IFX_INTERRUPT(cc60_pit_ch1_isr, CCU6_0_CH1_INT_SERVICE, CCU6_0_CH1_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc60_pit_ch1_isr, 0, CCU6_0_CH1_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_0, PIT_CH1);
|
||||
|
||||
}
|
||||
|
||||
IFX_INTERRUPT(cc61_pit_ch0_isr, CCU6_1_CH0_INT_SERVICE, CCU6_1_CH0_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc61_pit_ch0_isr, 0, CCU6_1_CH0_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_1, PIT_CH0);
|
||||
|
||||
}
|
||||
|
||||
IFX_INTERRUPT(cc61_pit_ch1_isr, CCU6_1_CH1_INT_SERVICE, CCU6_1_CH1_ISR_PRIORITY)
|
||||
IFX_INTERRUPT(cc61_pit_ch1_isr, 0, CCU6_1_CH1_ISR_PRIORITY)
|
||||
{
|
||||
PIT_CLEAR_FLAG(CCU6_1, PIT_CH1);
|
||||
|
||||
@@ -50,7 +52,7 @@ IFX_INTERRUPT(cc61_pit_ch1_isr, CCU6_1_CH1_INT_SERVICE, CCU6_1_CH1_ISR_PRIORITY)
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(eru_ch0_ch4_isr, ERU_CH0_CH4_INT_SERVICE, ERU_CH0_CH4_INT_PRIO)
|
||||
IFX_INTERRUPT(eru_ch0_ch4_isr, 0, ERU_CH0_CH4_INT_PRIO)
|
||||
{
|
||||
if(GET_GPIO_FLAG(ERU_CH0_REQ4_P10_7))//ͨ<><CDA8>0<EFBFBD>ж<EFBFBD>
|
||||
{
|
||||
@@ -63,7 +65,7 @@ IFX_INTERRUPT(eru_ch0_ch4_isr, ERU_CH0_CH4_INT_SERVICE, ERU_CH0_CH4_INT_PRIO)
|
||||
}
|
||||
}
|
||||
|
||||
IFX_INTERRUPT(eru_ch1_ch5_isr, ERU_CH1_CH5_INT_SERVICE, ERU_CH1_CH5_INT_PRIO)
|
||||
IFX_INTERRUPT(eru_ch1_ch5_isr, 0, ERU_CH1_CH5_INT_PRIO)
|
||||
{
|
||||
if(GET_GPIO_FLAG(ERU_CH1_REQ5_P10_8))//ͨ<><CDA8>1<EFBFBD>ж<EFBFBD>
|
||||
{
|
||||
@@ -77,7 +79,7 @@ IFX_INTERRUPT(eru_ch1_ch5_isr, ERU_CH1_CH5_INT_SERVICE, ERU_CH1_CH5_INT_PRIO)
|
||||
}
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷpclk<6C><6B><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC>ռ<EFBFBD><D5BC><EFBFBD><EFBFBD> 2ͨ<32><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD><DAB4><EFBFBD>DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ﲻ<EFBFBD>ٶ<EFBFBD><D9B6><EFBFBD><EFBFBD>жϺ<D0B6><CFBA><EFBFBD>
|
||||
//IFX_INTERRUPT(eru_ch2_ch6_isr, ERU_CH2_CH6_INT_SERVICE, ERU_CH2_CH6_INT_PRIO)
|
||||
//IFX_INTERRUPT(eru_ch2_ch6_isr, 0, ERU_CH2_CH6_INT_PRIO)
|
||||
//{
|
||||
// if(GET_GPIO_FLAG(ERU_CH2_REQ7_P00_4))//ͨ<><CDA8>2<EFBFBD>ж<EFBFBD>
|
||||
// {
|
||||
@@ -93,7 +95,7 @@ IFX_INTERRUPT(eru_ch1_ch5_isr, ERU_CH1_CH5_INT_SERVICE, ERU_CH1_CH5_INT_PRIO)
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(eru_ch3_ch7_isr, ERU_CH3_CH7_INT_SERVICE, ERU_CH3_CH7_INT_PRIO)
|
||||
IFX_INTERRUPT(eru_ch3_ch7_isr, 0, ERU_CH3_CH7_INT_PRIO)
|
||||
{
|
||||
if(GET_GPIO_FLAG(ERU_CH3_REQ6_P02_0))//ͨ<><CDA8>3<EFBFBD>ж<EFBFBD>
|
||||
{
|
||||
@@ -111,7 +113,7 @@ IFX_INTERRUPT(eru_ch3_ch7_isr, ERU_CH3_CH7_INT_SERVICE, ERU_CH3_CH7_INT_PRIO)
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(dma_ch5_isr, ERU_DMA_INT_SERVICE, ERU_DMA_INT_PRIO)
|
||||
IFX_INTERRUPT(dma_ch5_isr, 0, ERU_DMA_INT_PRIO)
|
||||
{
|
||||
|
||||
if (1 == camera_type) mt9v03x_dma();
|
||||
@@ -120,61 +122,61 @@ IFX_INTERRUPT(dma_ch5_isr, ERU_DMA_INT_SERVICE, ERU_DMA_INT_PRIO)
|
||||
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD>жϺ<D0B6><CFBA><EFBFBD> ʾ<><CABE>
|
||||
IFX_INTERRUPT(uart0_tx_isr, UART0_INT_SERVICE, UART0_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart0_tx_isr, 0, UART0_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart0_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart0_rx_isr, UART0_INT_SERVICE, UART0_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart0_rx_isr, 0, UART0_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart0_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart0_er_isr, UART0_INT_SERVICE, UART0_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart0_er_isr, 0, UART0_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart0_handle);
|
||||
}
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD>1Ĭ<31><C4AC><EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD><D3B5><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>ô<EFBFBD><C3B4><EFBFBD>
|
||||
IFX_INTERRUPT(uart1_tx_isr, UART1_INT_SERVICE, UART1_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart1_tx_isr, 0, UART1_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart1_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart1_rx_isr, UART1_INT_SERVICE, UART1_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart1_rx_isr, 0, UART1_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart1_handle);
|
||||
mt9v03x_uart_callback();
|
||||
}
|
||||
IFX_INTERRUPT(uart1_er_isr, UART1_INT_SERVICE, UART1_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart1_er_isr, 0, UART1_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart1_handle);
|
||||
}
|
||||
|
||||
|
||||
//<2F><><EFBFBD><EFBFBD>2Ĭ<32><C4AC><EFBFBD><EFBFBD><EFBFBD>ӵ<EFBFBD><D3B5><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>
|
||||
IFX_INTERRUPT(uart2_tx_isr, UART2_INT_SERVICE, UART2_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart2_tx_isr, 0, UART2_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart2_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart2_rx_isr, UART2_INT_SERVICE, UART2_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart2_rx_isr, 0, UART2_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart2_handle);
|
||||
wireless_uart_callback();
|
||||
}
|
||||
IFX_INTERRUPT(uart2_er_isr, UART2_INT_SERVICE, UART2_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart2_er_isr, 0, UART2_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart2_handle);
|
||||
}
|
||||
|
||||
|
||||
|
||||
IFX_INTERRUPT(uart3_tx_isr, UART3_INT_SERVICE, UART3_TX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart3_tx_isr, 0, UART3_TX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrTransmit(&uart3_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart3_rx_isr, UART3_INT_SERVICE, UART3_RX_INT_PRIO)
|
||||
IFX_INTERRUPT(uart3_rx_isr, 0, UART3_RX_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrReceive(&uart3_handle);
|
||||
}
|
||||
IFX_INTERRUPT(uart3_er_isr, UART3_INT_SERVICE, UART3_ER_INT_PRIO)
|
||||
IFX_INTERRUPT(uart3_er_isr, 0, UART3_ER_INT_PRIO)
|
||||
{
|
||||
IfxAsclin_Asc_isrError(&uart3_handle);
|
||||
}
|
||||
|
||||
264
Example/13-FFT_Demo/.cproject
Normal file
264
Example/13-FFT_Demo/.cproject
Normal file
@@ -0,0 +1,264 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
<cconfiguration id="com.tasking.config.ctc.abs.debug.669683410">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.ctc.abs.debug.669683410" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="com.tasking.managedbuilder.TASKING_IHEX" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="com.tasking.managedbuilder.TASKING_SRECORD" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactExtension="elf" artifactName="13-FFT_Demo" buildArtefactType="com.tasking.ctc.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.ctc.buildArtefactType.elf" cleanCommand=""${PRODDIR}/bin/rm" -rf" description="" id="com.tasking.config.ctc.abs.debug.669683410" name="Debug" parent="com.tasking.config.ctc.abs.debug">
|
||||
<folderInfo id="com.tasking.config.ctc.abs.debug.669683410." name="/" resourcePath="">
|
||||
<toolChain id="com.tasking.ctc.abs.debug.1037136091" name="TASKING VX-toolset for TriCore" superClass="com.tasking.ctc.abs.debug">
|
||||
<option id="com.tasking.ctc.pluginVersion.423126753" name="Plugin version" superClass="com.tasking.ctc.pluginVersion" value="1.238.0.0" valueType="string"/>
|
||||
<option id="com.tasking.ctc.prodDir.1364053947" name="Product directory:" superClass="com.tasking.ctc.prodDir" value="${eclipse_home}/.." valueType="string"/>
|
||||
<option id="com.tasking.ctc.cpu.1472471079" name="Processor:" superClass="com.tasking.ctc.cpu" value="tc26x" valueType="string"/>
|
||||
<option id="com.tasking.ctc.coreSelection.743380976" name="Use core:" superClass="com.tasking.ctc.coreSelection" value="vtc" valueType="string"/>
|
||||
<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF;com.tasking.managedbuilder.TASKING_SRECORD;com.tasking.managedbuilder.TASKING_IHEX" id="com.tasking.ctc.platform.abs.debug.1469966048" name="Debug" osList="" superClass="com.tasking.ctc.platform.abs.debug"/>
|
||||
<builder buildPath="${workspace_loc:/TC264_iLLD_ADC}/Debug" id="com.tasking.ctc.builder.abs.debug.671346402" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING TriCore Makefile generator" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.tasking.ctc.builder.abs.debug"/>
|
||||
<tool id="com.tasking.ctc.cc.abs.debug.252525364" name="C/C++ Compiler" superClass="com.tasking.ctc.cc.abs.debug">
|
||||
<option id="com.tasking.ctc.cc.pr36858.1455797176" name="workaround for PR36858" superClass="com.tasking.ctc.cc.pr36858" value="true" valueType="string"/>
|
||||
<option id="com.tasking.ctc.c.allocation.nearSize.376417881" name="Threshold for putting data in __near:" superClass="com.tasking.ctc.c.allocation.nearSize" value="0" valueType="string"/>
|
||||
<option id="com.tasking.ctc.cc.iso.2081233011" name="Comply to C standard:" superClass="com.tasking.ctc.cc.iso" value="com.tasking.ctc.cc.iso.c99" valueType="enumerated"/>
|
||||
<option id="com.tasking.ctc.cc.includePaths.730504544" name="Include paths" superClass="com.tasking.ctc.cc.includePaths" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/CODE}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/_Build}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/_Impl}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/_Lib}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/_Lib/DataHandling}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/_Lib/InternalMux}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/_PinMap}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Asclin}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Asclin/Asc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Asclin/Lin}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Asclin/Spi}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Asclin/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Ccu6}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Ccu6/Icu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Ccu6/PwmBc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Ccu6/PwmHl}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Ccu6/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Ccu6/Timer}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Ccu6/TimerWithTrigger}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Ccu6/TPwm}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Cif}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Cif/Cam}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Cif/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Cpu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Cpu/CStart}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Cpu/Irq}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Cpu/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Cpu/Trap}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Dma}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Dma/Dma}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Dma/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Dsadc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Dsadc/Dsadc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Dsadc/Rdc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Dsadc/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Dts}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Dts/Dts}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Dts/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Emem}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Emem/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Eray}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Eray/Eray}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Eray/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Eth}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Eth/Phy_Pef7071}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Eth/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Fce}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Fce/Crc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Fce/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Fft}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Fft/Fft}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Fft/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Flash}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Flash/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gpt12}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gpt12/IncrEnc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gpt12/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gtm}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gtm/Atom}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gtm/Atom/Pwm}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gtm/Atom/PwmHl}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gtm/Atom/Timer}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gtm/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gtm/Tim}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gtm/Tim/In}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gtm/Tom}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gtm/Tom/Pwm}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gtm/Tom/PwmHl}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gtm/Tom/Timer}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Gtm/Trig}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Hssl}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Hssl/Hssl}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Hssl/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/I2c}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/I2c/I2c}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/I2c/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Iom}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Iom/Driver}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Iom/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Msc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Msc/Msc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Msc/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Mtu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Mtu/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Multican}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Multican/Can}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Multican/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Port}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Port/Io}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Port/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Psi5}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Psi5/Psi5}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Psi5/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Psi5s}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Psi5s/Psi5s}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Psi5s/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Qspi}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Qspi/SpiMaster}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Qspi/SpiSlave}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Qspi/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Scu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Scu/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Sent}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Sent/Sent}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Sent/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Smu}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Smu/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Src}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Src/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Stm}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Stm/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Stm/Timer}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Vadc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Vadc/Adc}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/iLLD/TC26B/Tricore/Vadc/Std}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/Infra}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/Infra/Platform}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/Infra/Platform/Tricore}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/Infra/Platform/Tricore/Compilers}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/Infra/Sfr}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/Infra/Sfr/TC26B}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/Infra/Sfr/TC26B/_Reg}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/Service}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/BaseSw/Service/CpuGeneric}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/seekfree_libraries}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/seekfree_libraries/common}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Libraries/seekfree_peripheral}""/>
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/USER}""/>
|
||||
</option>
|
||||
<option id="com.tasking.ctc.cc.noTaskingSfr.31909688" name="Automatic inclusion of '.sfr' file" superClass="com.tasking.ctc.cc.noTaskingSfr" value="false" valueType="boolean"/>
|
||||
<option id="com.tasking.ctc.cc.optimize.775309643" name="Optimization level:" superClass="com.tasking.ctc.cc.optimize" value="com.tasking.ctc.cc.optimize.0" valueType="enumerated"/>
|
||||
<option id="com.tasking.ctc.cc.tradeoff.53559744" name="Trade-off between speed and size:" superClass="com.tasking.ctc.cc.tradeoff" value="com.tasking.ctc.cc.tradeoff.0" valueType="enumerated"/>
|
||||
<option id="com.tasking.ctc.cc.definedSymbols.1587155176" name="Defined symbols" superClass="com.tasking.ctc.cc.definedSymbols"/>
|
||||
<inputType id="com.tasking.ctc.cppInputType.1272022268" name="C++" superClass="com.tasking.ctc.cppInputType"/>
|
||||
<inputType id="com.tasking.ctc.cpp.cInputType.69092563" name="C" superClass="com.tasking.ctc.cpp.cInputType"/>
|
||||
<inputType id="com.tasking.ctc.cc.msInputType.1535524086" name="MS" superClass="com.tasking.ctc.cc.msInputType"/>
|
||||
</tool>
|
||||
<tool id="com.tasking.ctc.as.abs.debug.1390239146" name="Assembler" superClass="com.tasking.ctc.as.abs.debug">
|
||||
<option id="com.tasking.ctc.as.includePaths.1708708624" name="Include paths" superClass="com.tasking.ctc.as.includePaths" valueType="includePath">
|
||||
</option>
|
||||
<inputType id="com.tasking.ctc.asmInputType.1471959711" name="ASM" superClass="com.tasking.ctc.asmInputType"/>
|
||||
</tool>
|
||||
<tool id="com.tasking.ctc.lk.abs.debug.1142239087" name="Linker" superClass="com.tasking.ctc.lk.abs.debug">
|
||||
<option id="com.tasking.ctc.lk.lslFile.598041464" name="Linker script file:" superClass="com.tasking.ctc.lk.lslFile" value=""${workspace_loc:/${ProjName}/Lcf_Tasking_Tricore_Tc.lsl}"" valueType="string"/>
|
||||
<inputType id="com.tasking.ctc.lkObjInputType.654191777" name="OBJ" superClass="com.tasking.ctc.lkObjInputType"/>
|
||||
<inputType id="com.tasking.ctc.lkLibInputType.907568174" name="LIB" superClass="com.tasking.ctc.lkLibInputType"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
<storageModule addStartupFiles="false" moduleId="com.tasking.processor"/>
|
||||
<storageModule moduleId="com.tasking.toolInfo">
|
||||
<toolInfo>TASKING VX-toolset for TriCore: control program v6.3r1 Build 19041558</toolInfo>
|
||||
<toolInfo>TASKING VX-toolset for TriCore: object linker v6.3r1 Build 19041558</toolInfo>
|
||||
<toolInfo>TASKING program builder v6.3r1 Build 19041558</toolInfo>
|
||||
</storageModule>
|
||||
</cconfiguration>
|
||||
<cconfiguration id="com.tasking.config.ctc.abs.release.2134260939">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.tasking.config.ctc.abs.release.2134260939" moduleId="org.eclipse.cdt.core.settings" name="Release">
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="com.tasking.managedbuilder.TASKING_IHEX" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="com.tasking.managedbuilder.TASKING_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="com.tasking.managedbuilder.TASKING_SRECORD" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="com.tasking.managedbuilder.TskRegexErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactExtension="elf" artifactName="BaseFramework_TC264_CCU6" buildArtefactType="com.tasking.ctc.buildArtefactType.elf" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.tasking.ctc.buildArtefactType.elf" cleanCommand=""${PRODDIR}/bin/rm" -rf" description="" id="com.tasking.config.ctc.abs.release.2134260939" name="Release" parent="com.tasking.config.ctc.abs.release">
|
||||
<folderInfo id="com.tasking.config.ctc.abs.release.2134260939." name="/" resourcePath="">
|
||||
<toolChain id="com.tasking.ctc.abs.release.266576899" name="TASKING VX-toolset for TriCore" superClass="com.tasking.ctc.abs.release">
|
||||
<option id="com.tasking.ctc.pluginVersion.172838958" name="Plugin version" superClass="com.tasking.ctc.pluginVersion" value="1.238.0.0" valueType="string"/>
|
||||
<option id="com.tasking.ctc.prodDir.1113646416" name="Product directory:" superClass="com.tasking.ctc.prodDir" value="${eclipse_home}/.." valueType="string"/>
|
||||
<option id="com.tasking.ctc.cpu.1449455478" name="Processor:" superClass="com.tasking.ctc.cpu" value="tc26x" valueType="string"/>
|
||||
<option id="com.tasking.ctc.coreSelection.1874448791" name="Use core:" superClass="com.tasking.ctc.coreSelection" value="vtc" valueType="string"/>
|
||||
<targetPlatform archList="all" binaryParser="com.tasking.managedbuilder.TASKING_ELF;com.tasking.managedbuilder.TASKING_SRECORD;com.tasking.managedbuilder.TASKING_IHEX" id="com.tasking.ctc.platform.abs.release.869125735" name="Release" osList="" superClass="com.tasking.ctc.platform.abs.release"/>
|
||||
<builder buildPath="${workspace_loc:/BaseFramework_TC264_CCU6}/Release" id="com.tasking.ctc.builder.abs.debug.1954338977" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="TASKING TriCore Makefile generator" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.tasking.ctc.builder.abs.debug"/>
|
||||
<tool id="com.tasking.ctc.cc.abs.release.537444925" name="C/C++ Compiler" superClass="com.tasking.ctc.cc.abs.release">
|
||||
<option id="com.tasking.ctc.cc.pr36858.868498681" name="workaround for PR36858" superClass="com.tasking.ctc.cc.pr36858" value="true" valueType="string"/>
|
||||
<inputType id="com.tasking.ctc.cppInputType.408088544" name="C++" superClass="com.tasking.ctc.cppInputType"/>
|
||||
<inputType id="com.tasking.ctc.cpp.cInputType.567670532" name="C" superClass="com.tasking.ctc.cpp.cInputType"/>
|
||||
<inputType id="com.tasking.ctc.cc.msInputType.155457405" name="MS" superClass="com.tasking.ctc.cc.msInputType"/>
|
||||
</tool>
|
||||
<tool id="com.tasking.ctc.as.abs.release.1823544736" name="Assembler" superClass="com.tasking.ctc.as.abs.release">
|
||||
<inputType id="com.tasking.ctc.asmInputType.2104902864" name="ASM" superClass="com.tasking.ctc.asmInputType"/>
|
||||
</tool>
|
||||
<tool id="com.tasking.ctc.lk.abs.release.2036033403" name="Linker" superClass="com.tasking.ctc.lk.abs.release">
|
||||
<option id="com.tasking.ctc.lk.lslFile.475054177" name="Linker script file:" superClass="com.tasking.ctc.lk.lslFile" value="" valueType="string"/>
|
||||
<inputType id="com.tasking.ctc.lkObjInputType.2136690522" name="OBJ" superClass="com.tasking.ctc.lkObjInputType"/>
|
||||
<inputType id="com.tasking.ctc.lkLibInputType.1787013953" name="LIB" superClass="com.tasking.ctc.lkLibInputType"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
<storageModule addStartupFiles="false" moduleId="com.tasking.processor"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="TC264_iLLD_STM.com.tasking.ctc.target.abs.1634651035" name="TASKING TriCore Application" projectType="com.tasking.ctc.target.abs"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
<scannerConfigBuildInfo instanceId="com.tasking.config.ctc.abs.release.2134260939;com.tasking.config.ctc.abs.release.2134260939.">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.ctc.TskTriCoreScannerInfo"/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="com.tasking.config.ctc.abs.debug.669683410;com.tasking.config.ctc.abs.debug.669683410.">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.tasking.ctc.TskTriCoreScannerInfo"/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
|
||||
<project-mappings>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.tasking.ctc.clanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.tasking.ctc.clanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.tasking.ctc.cpplanguage"/>
|
||||
<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.tasking.ctc.cpplanguage"/>
|
||||
</project-mappings>
|
||||
</storageModule>
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
<configuration configurationName="Debug">
|
||||
<resource resourceType="PROJECT" workspacePath="/seekfree"/>
|
||||
</configuration>
|
||||
<configuration configurationName="Release">
|
||||
<resource resourceType="PROJECT" workspacePath="/seekfree"/>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
</cproject>
|
||||
20
Example/13-FFT_Demo/.project
Normal file
20
Example/13-FFT_Demo/.project
Normal file
@@ -0,0 +1,20 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>13-FFT_Demo</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>com.tasking.ctc.TskManagedBuilder</name>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
<nature>com.tasking.ctc.target</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
3
Example/13-FFT_Demo/CODE/本文件夹作用.txt
Normal file
3
Example/13-FFT_Demo/CODE/本文件夹作用.txt
Normal file
@@ -0,0 +1,3 @@
|
||||
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>û<EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Լ<EFBFBD><EFBFBD>Ĵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CODE<EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<EFBFBD><EFBFBD>Ҫ<EFBFBD>ٴ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD>У<EFBFBD>ֱ<EFBFBD>ӽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>CODE<EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
Ȼ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɱ<EFBFBD><EFBFBD><EFBFBD>
|
||||
0
Example/13-FFT_Demo/DConfig
Normal file
0
Example/13-FFT_Demo/DConfig
Normal file
21
Example/13-FFT_Demo/FFT.m
Normal file
21
Example/13-FFT_Demo/FFT.m
Normal file
@@ -0,0 +1,21 @@
|
||||
Fs = 100; % <EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD>100hz
|
||||
T = 1/Fs; % <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
L = 2000; % <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
x = (0:L-1)*T; % <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
y1 = 1024 * cos(3 * pi * x) + 512 * cos(7 * pi * x + pi / 2) + 2047 % <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
y2 = fft(y1); % <EFBFBD><EFBFBD>FFT<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
p = abs(y2*2)/(L) % <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><EFBFBD><EFBFBD>ڸ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ/(L/2)
|
||||
p = p(1:L/2) % ȡǰ<EFBFBD>벿<EFBFBD><EFBFBD>
|
||||
n = 0:L-1 % <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
f = Fs*n/L % <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD>
|
||||
f = f(1:L/2) % ȡ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǰ<EFBFBD>벿<EFBFBD><EFBFBD> ͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǻ<EFBFBD><EFBFBD>Ʒ<EFBFBD>Ƶͼֻȡǰ<EFBFBD><EFBFBD>һ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD><EFBFBD><EFBFBD>
|
||||
%Ϊʲôȡһ<EFBFBD><EFBFBD><EFBFBD>أ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˵<EFBFBD><EFBFBD>һ<EFBFBD>£<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ǿ<EFBFBD><EFBFBD>Թ۲<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĺ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD>ʣ<EFBFBD><EFBFBD>ῴ<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>0-100<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӣ<EFBFBD>
|
||||
%<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѧ<EFBFBD><EFBFBD><EFBFBD>ο<EFBFBD>˹<EFBFBD>ض<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֪<EFBFBD><EFBFBD><EFBFBD><EFBFBD>100hz<EFBFBD>IJ<EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD>ֻ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>50hzƵ<EFBFBD>ʵIJ<EFBFBD><EFBFBD>Ρ<EFBFBD>
|
||||
|
||||
plot(f,p) % <EFBFBD><EFBFBD><EFBFBD>Ʒ<EFBFBD>Ƶͼ<EFBFBD><EFBFBD>
|
||||
title('Single-Sided Amplitude Spectrum of y1(f)')
|
||||
xlabel('Ƶ<EFBFBD><EFBFBD>(Hz)')
|
||||
ylabel('<EFBFBD><EFBFBD>ֵ')
|
||||
469
Example/13-FFT_Demo/Lcf_Tasking_Tricore_Tc.lsl
Normal file
469
Example/13-FFT_Demo/Lcf_Tasking_Tricore_Tc.lsl
Normal file
@@ -0,0 +1,469 @@
|
||||
/**
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
// Specify a multi-core processor environment (mpe)
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
72
Example/13-FFT_Demo/Libraries/BaseSw/Ifx_Cfg.h
Normal file
72
Example/13-FFT_Demo/Libraries/BaseSw/Ifx_Cfg.h
Normal file
@@ -0,0 +1,72 @@
|
||||
/**
|
||||
* \file Ifx_Cfg.h
|
||||
* \brief Configuration.
|
||||
*
|
||||
* \version iLLD_Demos_1_0_1_11_0
|
||||
* \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*
|
||||
*
|
||||
* \defgroup IfxLld_Demo_StmDemo_SrcDoc_IlldConfig iLLD configuration
|
||||
* \ingroup IfxLld_Demo_StmDemo_SrcDoc
|
||||
*/
|
||||
|
||||
#ifndef IFX_CFG_H
|
||||
#define IFX_CFG_H
|
||||
|
||||
/******************************************************************************/
|
||||
/*-----------------------------------Macros-----------------------------------*/
|
||||
/******************************************************************************/
|
||||
|
||||
/** \addtogroup IfxLld_Demo_StmDemo_SrcDoc_IlldConfig
|
||||
* \{ */
|
||||
|
||||
/*______________________________________________________________________________
|
||||
** Configuration for IfxScu_cfg.h
|
||||
**____________________________________________________________________________*/
|
||||
/**
|
||||
* \name Frequency configuration
|
||||
* \{
|
||||
*/
|
||||
#define IFX_CFG_SCU_XTAL_FREQUENCY (20000000) /**< \copydoc IFX_CFG_SCU_XTAL_FREQUENCY */
|
||||
|
||||
/** \} */
|
||||
|
||||
/** \} */
|
||||
|
||||
#endif /* IFX_CFG_H */
|
||||
@@ -0,0 +1,76 @@
|
||||
/**
|
||||
* \file CompilerDcc.c
|
||||
*
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* $Date: 2014-02-27 20:08:39 GMT$
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#include "Cpu/Std/Ifx_Types.h"
|
||||
#include "Compilers.h"
|
||||
|
||||
#if defined(__DCC__)
|
||||
/*!
|
||||
* \brief Initializes C variables
|
||||
*
|
||||
* This function is called in the startup. This function initialize the all variables in .data section
|
||||
* and clears the .bss section
|
||||
*
|
||||
* Parameters: Nil
|
||||
* Return: Nil
|
||||
*/
|
||||
void Ifx_C_Init(void)
|
||||
{
|
||||
extern void __init_main(void);
|
||||
|
||||
__init_main(); /* initialize data */
|
||||
}
|
||||
|
||||
|
||||
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
|
||||
/*Dummy main function
|
||||
* This function is required only for the Windriver, which looks for main while linking
|
||||
* ! DO NOT USE THIS FUNCTION !*/
|
||||
int main(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER */
|
||||
#endif
|
||||
@@ -0,0 +1,170 @@
|
||||
/**
|
||||
* \file CompilerDcc.h
|
||||
*
|
||||
* \version iLLD_New
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef COMPILERDCC_H
|
||||
#define COMPILERDCC_H 1
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
/*Linker definitions which are specific to Dcc */
|
||||
/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
|
||||
* to use the default compiler linker varaibles and startup */
|
||||
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
|
||||
|
||||
/*Start: Core 0 definitions ********************************************** */
|
||||
|
||||
/*C extern defintions */
|
||||
#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
|
||||
extern unsigned int __USTACK##cpu[]; /**< user stack end */ \
|
||||
extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
|
||||
extern unsigned int __INTTAB_CPU##cpu[]; /**< interrupt vector table */ \
|
||||
extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap vector table */ \
|
||||
extern unsigned int __CSA##cpu[]; /**< context save area begin */ \
|
||||
extern unsigned int __CSA##cpu##_END[]; /**< context save area end */
|
||||
|
||||
#define __USTACK(cpu) __USTACK##cpu
|
||||
#define __ISTACK(cpu) __ISTACK##cpu
|
||||
#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
|
||||
#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
|
||||
#define __CSA(cpu) __CSA##cpu
|
||||
#define __CSA_END(cpu) __CSA##cpu##_END
|
||||
|
||||
#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
|
||||
__asm("\t .weak __A8_MEM, __A9_MEM"); /**< ASM extern definitions */
|
||||
|
||||
/*Wrapper macros for the tool specific definitions */
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
|
||||
#else
|
||||
#define __INTTAB(cpu) __INTTAB_CPU##cpu
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT) */
|
||||
|
||||
#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
|
||||
|
||||
#define __SDATA1(cpu) _SMALL_DATA_
|
||||
#define __SDATA2(cpu) _LITERAL_DATA_
|
||||
#define __SDATA3(cpu) __A8_MEM
|
||||
#define __SDATA4(cpu) __A9_MEM
|
||||
|
||||
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
|
||||
|
||||
/******************************************************************************/
|
||||
#define IFX_INLINE static __inline__
|
||||
|
||||
/* FXIME check how to pack structure members */
|
||||
#define IFX_PACKED
|
||||
|
||||
#define COMPILER_NAME "DCC"
|
||||
#define COMPILER_VERSION __VERSION__
|
||||
|
||||
#define COMPILER_REVISION 0
|
||||
#define IFX_INTERRUPT_FAST IFX_INTERRUPT
|
||||
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
|
||||
#endif
|
||||
|
||||
#else
|
||||
/* *INDENT-OFF* */
|
||||
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
|
||||
#endif
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
|
||||
|
||||
#ifndef IFX_INTERRUPT_INTERNAL
|
||||
#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) \
|
||||
void __interrupt(prio) __vector_table(vectabNum) isr(void)
|
||||
#endif
|
||||
|
||||
/*Macro IFX_INTERRUPT_LEGACY is to be used for compiler version pror to 5.9.3.0*/
|
||||
#define IFX_INTERRUPT_LEGACY(isr, vectabNum, prio) \
|
||||
__asm ("\t.align\t 5\n\t\
|
||||
.section .int."#prio"\n \t.sectionlink .inttab"#vectabNum".intvec."#prio"\n\
|
||||
#$$bf\n\
|
||||
__intvec_tc"#vectabNum"_"#prio":\n\
|
||||
movh.a\t %a14,"#isr"@ha\n\
|
||||
lea\t %a14,[%a14]"#isr"@l\n\
|
||||
ji\t %a14\n\
|
||||
#$$ef\n\t\
|
||||
.section .intend."#prio"\n \t.sectionlink .text");\
|
||||
__interrupt__ void isr (void)
|
||||
|
||||
/* *INDENT-ON* */
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#define IFX_ALIGN(n) __attribute__ ((aligned(n)))
|
||||
|
||||
/******************************************************************************/
|
||||
/*Memory qualifiers*/
|
||||
#ifndef IFX_FAR_ABS
|
||||
#define IFX_FAR_ABS
|
||||
#endif
|
||||
|
||||
#ifndef IFX_NEAR_ABS
|
||||
#define IFX_NEAR_ABS
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A0
|
||||
#define IFX_REL_A0
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A1
|
||||
#define IFX_REL_A1
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A8
|
||||
#define IFX_REL_A8
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A9
|
||||
#define IFX_REL_A9
|
||||
#endif
|
||||
/******************************************************************************/
|
||||
|
||||
#endif /* COMPILERDCC_H */
|
||||
@@ -0,0 +1,113 @@
|
||||
/**
|
||||
* \file CompilerGhs.c
|
||||
*
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* $Date: 2014-02-27 20:08:40 GMT$
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#include "Cpu/Std/Ifx_Types.h"
|
||||
#include "Compilers.h"
|
||||
|
||||
#if defined(__ghs__) && !defined(WIN32)
|
||||
|
||||
typedef int ptrdiff_t;
|
||||
typedef unsigned int syze_t;
|
||||
typedef signed int signed_size_t;
|
||||
#define size_t syze_t
|
||||
|
||||
extern void *memcpy(void *s1, const void *s2, syze_t n);
|
||||
extern void *memset(void *s, int c, syze_t n);
|
||||
|
||||
/* rodata is absolute */
|
||||
typedef const char rodata_ptr[];
|
||||
# define PIRBASE 0
|
||||
|
||||
#define CONST_FUNCP *const
|
||||
|
||||
/*!
|
||||
* \brief Initializes C variables.
|
||||
*
|
||||
* This function is called in the startup. This function initialize the all variables in .data section
|
||||
* and clears the .bss section
|
||||
*
|
||||
* Parameters: Nil
|
||||
* Return: Nil
|
||||
*/
|
||||
void Ifx_C_Init(void)
|
||||
{
|
||||
/*----------------------------------------------------------------------*/
|
||||
/* */
|
||||
/* Clear BSS */
|
||||
/* */
|
||||
/*----------------------------------------------------------------------*/
|
||||
{ /* The .secinfo section is in text; declare functions to force PIC */
|
||||
|
||||
#pragma ghs rodata
|
||||
extern rodata_ptr __ghsbinfo_clear;
|
||||
#pragma ghs rodata
|
||||
extern rodata_ptr __ghseinfo_clear;
|
||||
|
||||
void **b = (void **) ((char *)__ghsbinfo_clear);
|
||||
void **e = (void **) ((char *)__ghseinfo_clear);
|
||||
|
||||
while (b != e) {
|
||||
void * t; /* target pointer */
|
||||
ptrdiff_t v; /* value to set */
|
||||
size_t n; /* set n bytes */
|
||||
t = (char *)(*b++);
|
||||
v = *((ptrdiff_t *) b); b++;
|
||||
n = *((size_t *) b); b++;
|
||||
memset(t, v, n);
|
||||
}
|
||||
}
|
||||
|
||||
/*----------------*/
|
||||
/* initialize iob */
|
||||
/*----------------*/
|
||||
{
|
||||
#pragma weak __gh_iob_init
|
||||
extern void __gh_iob_init(void);
|
||||
static void (CONST_FUNCP iob_init_funcp)(void) = __gh_iob_init;
|
||||
/* if cciob.c is loaded, initialize _iob for stdin,stdout,stderr */
|
||||
if (iob_init_funcp) __gh_iob_init();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,173 @@
|
||||
/**
|
||||
* \file CompilerGhs.h
|
||||
*
|
||||
* \version iLLD_New
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef COMPILERGHS_H
|
||||
#define COMPILERGHS_H 1
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
// #include <stddef.h>
|
||||
|
||||
/*Linker definitions which are specific to Ghs */
|
||||
/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
|
||||
* to use the default compiler linker varaibles and startup */
|
||||
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
|
||||
|
||||
/*Start: Common definitions ********************************************** */
|
||||
#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
|
||||
extern unsigned int __A0_MEM[]; /**< center of A0 addressable area */ \
|
||||
extern unsigned int __A1_MEM[]; /**< center of A1 addressable area */ \
|
||||
extern unsigned int __A8_MEM[]; /**< center of A8 addressable area */ \
|
||||
extern unsigned int __A9_MEM[]; /**< center of A9 addressable area */
|
||||
|
||||
/*End: Common definitions ************************************************ */
|
||||
|
||||
/*Start: Core 0 definitions ********************************************** */
|
||||
|
||||
/*C extern defintions */
|
||||
#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
|
||||
extern unsigned int __USTACK##cpu[]; /**< user stack end */ \
|
||||
extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
|
||||
extern unsigned int __INTTAB_CPU##cpu[]; /**< Interrupt vector table */ \
|
||||
extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap table */ \
|
||||
extern unsigned int __CSA##cpu[]; /**< context save area 1 begin */ \
|
||||
extern unsigned int __CSA##cpu##_END[]; /**< context save area 1 begin */
|
||||
|
||||
#define __USTACK(cpu) __USTACK##cpu
|
||||
#define __ISTACK(cpu) __ISTACK##cpu
|
||||
#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
|
||||
#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
|
||||
#define __CSA(cpu) __CSA##cpu
|
||||
#define __CSA_END(cpu) __CSA##cpu##_END
|
||||
|
||||
/*Wrapper macros for the tool specific definitions */
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
|
||||
#else
|
||||
#define __INTTAB(cpu) __INTTAB_CPU##cpu
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT) */
|
||||
|
||||
#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
|
||||
|
||||
#define __SDATA1(cpu) __A0_MEM
|
||||
#define __SDATA2(cpu) __A1_MEM
|
||||
#define __SDATA3(cpu) __A8_MEM
|
||||
#define __SDATA4(cpu) __A9_MEM
|
||||
|
||||
/* MHWS+
|
||||
#define __SDATA1(cpu) __A0_MEM
|
||||
#define __SDATA2(cpu) __A1_MEM
|
||||
#define __SDATA3(cpu) __A8_MEM
|
||||
#define __SDATA4(cpu) __A9_MEM
|
||||
MHWS- */
|
||||
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
|
||||
|
||||
/******************************************************************************/
|
||||
#ifndef IFX_INLINE
|
||||
#define IFX_INLINE static inline __attribute__ ((always_inline)) /*Makes the function always inlined */
|
||||
#endif
|
||||
|
||||
#define IFX_PACKED __packed
|
||||
|
||||
#define COMPILER_NAME "GHS"
|
||||
#define COMPILER_VERSION __GHS_VERSION_NUMBER
|
||||
|
||||
#define COMPILER_REVISION __GHS_REVISION_VALUE
|
||||
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
|
||||
#endif
|
||||
|
||||
#else
|
||||
/* *INDENT-OFF* */
|
||||
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
|
||||
#endif
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
|
||||
|
||||
#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) \
|
||||
__attribute__((section(".intvec_tc"#vectabNum"_"#prio))) void iVecEntry##vectabNum##_##prio(void) \
|
||||
{ \
|
||||
__asm__("movh.a a14, %hi("#isr") \n" \
|
||||
"lea a14, [a14]%lo("#isr")\n" \
|
||||
"ji a14"); \
|
||||
} \
|
||||
__interrupt void isr(void)
|
||||
|
||||
/* *INDENT-ON* */
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#define IFX_ALIGN(n) __attribute__ ((aligned(n)))
|
||||
|
||||
/******************************************************************************/
|
||||
/*Memory qualifiers*/
|
||||
#ifndef IFX_FAR_ABS
|
||||
#define IFX_FAR_ABS __attribute__((fardata))
|
||||
#endif
|
||||
|
||||
#ifndef IFX_NEAR_ABS
|
||||
#define IFX_NEAR_ABS
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A0
|
||||
#define IFX_REL_A0
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A1
|
||||
#define IFX_REL_A1
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A8
|
||||
#define IFX_REL_A8
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A9
|
||||
#define IFX_REL_A9
|
||||
#endif
|
||||
/******************************************************************************/
|
||||
|
||||
#endif /* COMPILERGHS_H */
|
||||
@@ -0,0 +1,153 @@
|
||||
/**
|
||||
* \file CompilerGnuc.c
|
||||
*
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* $Date: 2014-02-27 20:08:40 GMT$
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#include "Cpu/Std/Ifx_Types.h"
|
||||
#include "Compilers.h"
|
||||
|
||||
#if defined(__HIGHTEC__) && !defined(WIN32)
|
||||
/*!
|
||||
* \brief Data s C variables.
|
||||
*/
|
||||
extern uint32 __clear_table[]; /**< clear table entry */
|
||||
extern uint32 __copy_table[]; /**< copy table entry */
|
||||
|
||||
typedef volatile union
|
||||
{
|
||||
uint8 *ucPtr;
|
||||
uint16 *usPtr;
|
||||
uint32 *uiPtr;
|
||||
unsigned long long *ullPtr;
|
||||
} IfxStart_CTablePtr;
|
||||
|
||||
/*!
|
||||
* \brief Initializes C variables.
|
||||
*
|
||||
* This function is called in the startup. This function initialize the all variables in .data section
|
||||
* and clears the .bss section
|
||||
*
|
||||
* Parameters: Nil
|
||||
* Return: Nil
|
||||
*/
|
||||
void Ifx_C_Init(void)
|
||||
{
|
||||
IfxStart_CTablePtr pBlockDest, pBlockSrc;
|
||||
uint32 uiLength, uiCnt;
|
||||
uint32 *pTable;
|
||||
/* clear table */
|
||||
pTable = (uint32 *)&__clear_table;
|
||||
|
||||
while (pTable)
|
||||
{
|
||||
pBlockDest.uiPtr = (uint32 *)*pTable++;
|
||||
uiLength = *pTable++;
|
||||
|
||||
/* we are finished when length == -1 */
|
||||
if (uiLength == 0xFFFFFFFF)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
uiCnt = uiLength / 8;
|
||||
|
||||
while (uiCnt--)
|
||||
{
|
||||
*pBlockDest.ullPtr++ = 0;
|
||||
}
|
||||
|
||||
if (uiLength & 0x4)
|
||||
{
|
||||
*pBlockDest.uiPtr++ = 0;
|
||||
}
|
||||
|
||||
if (uiLength & 0x2)
|
||||
{
|
||||
*pBlockDest.usPtr++ = 0;
|
||||
}
|
||||
|
||||
if (uiLength & 0x1)
|
||||
{
|
||||
*pBlockDest.ucPtr = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* copy table */
|
||||
pTable = (uint32 *)&__copy_table;
|
||||
|
||||
while (pTable)
|
||||
{
|
||||
pBlockSrc.uiPtr = (uint32 *)*pTable++;
|
||||
pBlockDest.uiPtr = (uint32 *)*pTable++;
|
||||
uiLength = *pTable++;
|
||||
|
||||
/* we are finished when length == -1 */
|
||||
if (uiLength == 0xFFFFFFFF)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
uiCnt = uiLength / 8;
|
||||
|
||||
while (uiCnt--)
|
||||
{
|
||||
*pBlockDest.ullPtr++ = *pBlockSrc.ullPtr++;
|
||||
}
|
||||
|
||||
if (uiLength & 0x4)
|
||||
{
|
||||
*pBlockDest.uiPtr++ = *pBlockSrc.uiPtr++;
|
||||
}
|
||||
|
||||
if (uiLength & 0x2)
|
||||
{
|
||||
*pBlockDest.usPtr++ = *pBlockSrc.usPtr++;
|
||||
}
|
||||
|
||||
if (uiLength & 0x1)
|
||||
{
|
||||
*pBlockDest.ucPtr = *pBlockSrc.ucPtr;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,186 @@
|
||||
/**
|
||||
* \file CompilerGnuc.h
|
||||
*
|
||||
* \version iLLD_New
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef COMPILERGNUC_H
|
||||
#define COMPILERGNUC_H 1
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
/*Linker definitions which are specific to Gnuc */
|
||||
/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
|
||||
* to use the default compiler linker varaibles and startup */
|
||||
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
|
||||
|
||||
/*Start: Common definitions ********************************************** */
|
||||
#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
|
||||
extern unsigned int __A0_MEM[]; /**< center of A0 addressable area */ \
|
||||
extern unsigned int __A1_MEM[]; /**< center of A1 addressable area */ \
|
||||
extern unsigned int __A8_MEM[]; /**< center of A8 addressable area */ \
|
||||
extern unsigned int __A9_MEM[]; /**< center of A9 addressable area */
|
||||
|
||||
/*End: Common definitions ************************************************ */
|
||||
|
||||
/*Start: Core 0 definitions ********************************************** */
|
||||
|
||||
/*C extern defintions */
|
||||
#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
|
||||
extern unsigned int __USTACK##cpu[]; /**< user stack end */ \
|
||||
extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
|
||||
extern unsigned int __INTTAB_CPU##cpu[]; /**< Interrupt vector table */ \
|
||||
extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap table */ \
|
||||
extern unsigned int __CSA##cpu[]; /**< context save area 1 begin */ \
|
||||
extern unsigned int __CSA##cpu##_END[]; /**< context save area 1 begin */
|
||||
|
||||
#define __USTACK(cpu) __USTACK##cpu
|
||||
#define __ISTACK(cpu) __ISTACK##cpu
|
||||
#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
|
||||
#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
|
||||
#define __CSA(cpu) __CSA##cpu
|
||||
#define __CSA_END(cpu) __CSA##cpu##_END
|
||||
|
||||
/*Wrapper macros for the tool specific definitions */
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
|
||||
#else
|
||||
#define __INTTAB(cpu) __INTTAB_CPU##cpu
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT) */
|
||||
|
||||
#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
|
||||
|
||||
#define __SDATA1(cpu) __A0_MEM
|
||||
#define __SDATA2(cpu) __A1_MEM
|
||||
#define __SDATA3(cpu) __A8_MEM
|
||||
#define __SDATA4(cpu) __A9_MEM
|
||||
|
||||
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
|
||||
|
||||
/******************************************************************************/
|
||||
#ifndef IFX_INLINE
|
||||
#define IFX_INLINE static inline __attribute__ ((always_inline)) /*Makes the function always inlined */
|
||||
#endif
|
||||
|
||||
#define IFX_PACKED __attribute__ ((packed))
|
||||
|
||||
#define COMPILER_NAME "GNUC"
|
||||
#define COMPILER_VERSION __VERSION__
|
||||
|
||||
#define COMPILER_REVISION 0
|
||||
|
||||
#define IFX_INTERRUPT_FAST IFX_INTERRUPT
|
||||
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
|
||||
#endif
|
||||
|
||||
#else
|
||||
/* *INDENT-OFF* */
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
|
||||
#endif
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
|
||||
|
||||
#ifndef IFX_INTERRUPT_INTERNAL
|
||||
#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) \
|
||||
__asm__ (".ifndef .intr.entry.include \n"\
|
||||
".altmacro \n"\
|
||||
".macro .int_entry.2 intEntryLabel, name # define the section and inttab entry code \n"\
|
||||
" .pushsection .\\intEntryLabel,\"ax\",@progbits \n"\
|
||||
" __\\intEntryLabel : \n"\
|
||||
" svlcx \n"\
|
||||
" movh.a %a14, hi:\\name \n"\
|
||||
" lea %a14, [%a14]lo:\\name \n"\
|
||||
" ji %a14 \n"\
|
||||
" .popsection \n"\
|
||||
".endm \n"\
|
||||
".macro .int_entry.1 prio,vectabNum,u,name \n"\
|
||||
".int_entry.2 intvec_tc\\vectabNum\\u\\prio,(name) # build the unique name \n"\
|
||||
".endm \n"\
|
||||
" \n"\
|
||||
".macro .intr.entry name,vectabNum,prio \n"\
|
||||
".int_entry.1 %(prio),%(vectabNum),_,name # evaluate the priority and the cpu number \n"\
|
||||
".endm \n"\
|
||||
".intr.entry.include: \n"\
|
||||
".endif \n"\
|
||||
".intr.entry "#isr","#vectabNum","#prio );\
|
||||
IFX_EXTERN void __attribute__ ((interrupt_handler)) isr(); \
|
||||
void isr (void)
|
||||
#endif /* IFX_INTERRUPT_INTERNAL */
|
||||
|
||||
/* *INDENT-ON* */
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#define IFX_ALIGN(n) __attribute__ ((aligned(n)))
|
||||
|
||||
/******************************************************************************/
|
||||
/*Memory qualifiers*/
|
||||
#ifndef IFX_FAR_ABS
|
||||
#define IFX_FAR_ABS __attribute__((fardata))
|
||||
#endif
|
||||
|
||||
#ifndef IFX_NEAR_ABS
|
||||
#define IFX_NEAR_ABS
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A0
|
||||
#define IFX_REL_A0
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A1
|
||||
#define IFX_REL_A1
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A8
|
||||
#define IFX_REL_A8
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A9
|
||||
#define IFX_REL_A9
|
||||
#endif
|
||||
/******************************************************************************/
|
||||
|
||||
#endif /* COMPILERGNUC_H */
|
||||
@@ -0,0 +1,65 @@
|
||||
/**
|
||||
* \file CompilerTasking.c
|
||||
*
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* $Date: 2014-02-27 20:08:41 GMT$
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#include "Cpu/Std/Ifx_Types.h"
|
||||
#include "Compilers.h"
|
||||
|
||||
#if defined(__TASKING__)
|
||||
/*!
|
||||
* \brief Initializes C variables
|
||||
*
|
||||
* This function is called in the startup. This function initialize the all variables in .data section
|
||||
* and clears the .bss section
|
||||
*
|
||||
* Parameters: Nil
|
||||
* Return: Nil
|
||||
*/
|
||||
void Ifx_C_Init(void)
|
||||
{
|
||||
extern void _c_init(void);
|
||||
|
||||
_c_init(); /* initialize data */
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,165 @@
|
||||
/**
|
||||
* \file CompilerTasking.h
|
||||
*
|
||||
* \version iLLD_New
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef COMPILERTASKING_H
|
||||
#define COMPILERTASKING_H 1
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
/*Linker definitions which are specific to Tasking */
|
||||
/* IFX_CFG_USE_COMPILER_DEFAULT_LINKER shall be defined in Ifx_Cfg.h
|
||||
* to use the default compiler linker varaibles and startup */
|
||||
#ifndef IFX_CFG_USE_COMPILER_DEFAULT_LINKER
|
||||
|
||||
#ifndef __cplusplus
|
||||
/*Start: Common definitions ********************************************** */
|
||||
#define IFXCOMPILER_COMMON_LINKER_SYMBOLS() \
|
||||
__asm("\t .extern _SMALL_DATA_, _LITERAL_DATA_, _A8_DATA_, _A9_DATA_");
|
||||
|
||||
/*End: Common definitions ********************************************** */
|
||||
|
||||
/*Start: Core 0 definitions ********************************************** */
|
||||
|
||||
#define IFXCOMPILER_CORE_LINKER_SYMBOLS(cpu) \
|
||||
__asm("\t .extern __USTACK"#cpu); /**< user stack end is required as asm to be used with setreg macro */ \
|
||||
extern unsigned int __ISTACK##cpu[]; /**< interrupt stack end */ \
|
||||
extern unsigned int __INTTAB_CPU##cpu[]; /**< interrupt vector table */ \
|
||||
extern unsigned int __TRAPTAB_CPU##cpu[]; /**< trap vector table */ \
|
||||
extern unsigned int __CSA##cpu[]; /**< context save area begin */ \
|
||||
extern unsigned int __CSA##cpu##_END[]; /**< context save area end */
|
||||
#endif
|
||||
|
||||
#define __USTACK(cpu) __USTACK##cpu
|
||||
#define __ISTACK(cpu) __ISTACK##cpu
|
||||
#define __INTTAB_CPU(cpu) __INTTAB_CPU##cpu
|
||||
#define __TRAPTAB_CPU(cpu) __TRAPTAB_CPU##cpu
|
||||
#define __CSA(cpu) __CSA##cpu
|
||||
#define __CSA_END(cpu) __CSA##cpu##_END
|
||||
|
||||
/*Wrapper macros for the tool specific definitions */
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
#define __INTTAB(cpu) ((unsigned int)__INTTAB_CPU##cpu | (unsigned int)0x1FE0)
|
||||
#else
|
||||
#define __INTTAB(cpu) __INTTAB_CPU##cpu
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT) */
|
||||
|
||||
#define __TRAPTAB(cpu) __TRAPTAB_CPU##cpu
|
||||
|
||||
#define __SDATA1(cpu) _SMALL_DATA_
|
||||
#define __SDATA2(cpu) _LITERAL_DATA_
|
||||
#define __SDATA3(cpu) _A8_DATA_
|
||||
#define __SDATA4(cpu) _A9_DATA_
|
||||
|
||||
#endif /*IFX_CFG_USE_COMPILER_DEFAULT_LINKER*/
|
||||
|
||||
/******************************************************************************/
|
||||
#ifdef __cplusplus
|
||||
#define IFX_INLINE static inline
|
||||
#else
|
||||
#define IFX_INLINE inline
|
||||
#endif
|
||||
|
||||
/* FXIME check how to pack structure members */
|
||||
#define IFX_PACKED
|
||||
|
||||
#define COMPILER_NAME "TASKING"
|
||||
#define COMPILER_VERSION __VERSION__
|
||||
|
||||
/* Note that __REVISION__ is only available for tasking compiler! */
|
||||
#define COMPILER_REVISION __REVISION__
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#if defined(IFX_USE_SW_MANAGED_INT)
|
||||
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) void isr(void)
|
||||
#endif
|
||||
|
||||
#else
|
||||
/* *INDENT-OFF* */
|
||||
#ifndef IFX_INTERRUPT
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio) IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio)
|
||||
#endif
|
||||
#define IFX_INTERRUPT_FAST(isr, vectabNum, prio) void __interrupt_fast(prio) __vector_table(vectabNum) isr(void)
|
||||
|
||||
#endif /*defined(IFX_USE_SW_MANAGED_INT)*/
|
||||
|
||||
#define IFX_INTERRUPT_INTERNAL(isr, vectabNum, prio) void __interrupt(prio) __vector_table(vectabNum) isr(void)
|
||||
|
||||
/* *INDENT-ON* */
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#define IFX_ALIGN(n) __attribute__ ((__align(n)))
|
||||
|
||||
/******************************************************************************/
|
||||
/*Memory qualifiers*/
|
||||
#ifndef IFX_FAR_ABS
|
||||
#define IFX_FAR_ABS __far
|
||||
#endif
|
||||
|
||||
#ifndef IFX_NEAR_ABS
|
||||
#define IFX_NEAR_ABS __near
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A0
|
||||
#define IFX_REL_A0 __a0
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A1
|
||||
#define IFX_REL_A1 __a1
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A8
|
||||
#define IFX_REL_A8 __a8
|
||||
#endif
|
||||
|
||||
#ifndef IFX_REL_A9
|
||||
#define IFX_REL_A9 __a9
|
||||
#endif
|
||||
/******************************************************************************/
|
||||
|
||||
#endif /* COMPILERTASKING_H */
|
||||
@@ -0,0 +1,144 @@
|
||||
/**
|
||||
* \file Compilers.h
|
||||
*
|
||||
* \copyright Copyright (c) 2013 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* $Date: 2014-04-07 12:13:19 GMT$
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef COMPILERS_H
|
||||
#define COMPILERS_H 1
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#include "Ifx_Cfg.h"
|
||||
|
||||
/*this file shall not be modified by the user, IFX_XXXX defines shall be defined in Ifx_Cfg.h */
|
||||
#ifndef IFX_STATIC
|
||||
#define IFX_STATIC static
|
||||
#endif
|
||||
|
||||
#ifndef IFX_CONST
|
||||
#define IFX_CONST const
|
||||
#endif
|
||||
#ifndef CONST_CFG
|
||||
#define CONST_CFG const /* configuration constants are stored in ROM */
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define IFX_EXTERN extern "C"
|
||||
#else
|
||||
#define IFX_EXTERN extern
|
||||
#endif
|
||||
|
||||
#ifndef NULL_PTR
|
||||
#ifdef __cplusplus
|
||||
#define NULL_PTR (0)
|
||||
#else /*#ifdef __cplusplus */
|
||||
#define NULL_PTR ((void *)0)
|
||||
#endif /*#ifdef __cplusplus */
|
||||
#endif /*#ifndef NULL_PTR */
|
||||
|
||||
#ifndef CFG_LONG_SIZE_T
|
||||
#define CFG_LONG_SIZE_T (0)
|
||||
#endif
|
||||
|
||||
#if defined(__DCC__)
|
||||
#include "CompilerDcc.h"
|
||||
|
||||
#elif defined(__HIGHTEC__)
|
||||
#include "CompilerGnuc.h"
|
||||
|
||||
#elif defined(__TASKING__)
|
||||
#include "CompilerTasking.h"
|
||||
|
||||
#elif defined(__ghs__)
|
||||
#include "CompilerGhs.h"
|
||||
|
||||
#elif defined(__MSVC__)
|
||||
#include "CompilerMsvc.h"
|
||||
|
||||
#else
|
||||
|
||||
/** \addtogroup IfxLld_Cpu_Std_Interrupt
|
||||
* \{ */
|
||||
/** \brief Macro to define Interrupt Service Routine.
|
||||
* This macro makes following definitions:\n
|
||||
* 1) Define linker section as .intvec_tc<vector number>_<interrupt priority>.\n
|
||||
* 2) define compiler specific attribute for the interrupt functions.\n
|
||||
* 3) define the Interrupt service routine as Isr function.\n
|
||||
* To get details about usage of this macro, refer \ref IfxLld_Cpu_Irq_Usage
|
||||
*
|
||||
* \param isr Name of the Isr function.
|
||||
* \param vectabNum Vector table number.
|
||||
* \param prio Interrupt priority. Refer Usage of Interrupt Macro for more details.
|
||||
*/
|
||||
#define IFX_INTERRUPT(isr, vectabNum, prio)
|
||||
|
||||
/** \} */
|
||||
#error "Compiler unsupported"
|
||||
#endif
|
||||
|
||||
#if defined(__HIGHTEC__)
|
||||
#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section #sec aw 4)
|
||||
#define DATA_SECTION(sec) _Pragma(#sec)
|
||||
#define END_DATA_SECTION DATA_SECTION(section)
|
||||
#elif defined(__TASKING__)
|
||||
#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section farbss #sec)
|
||||
#define DATA_SECTION(sec) _Pragma(#sec)
|
||||
#define END_DATA_SECTION DATA_SECTION(section farbss align restore) \
|
||||
DATA_SECTION(section farbss)
|
||||
#elif defined(__DCC__)
|
||||
#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section #sec WX)
|
||||
#define DATA_SECTION(sec) _Pragma(#sec)
|
||||
#define END_DATA_SECTION DATA_SECTION(section DATA X)
|
||||
#elif defined(__ghs__)
|
||||
#define BEGIN_DATA_SECTION(sec) DATA_SECTION(section #sec WX)
|
||||
#define DATA_SECTION(sec) _Pragma(#sec)
|
||||
#define END_DATA_SECTION DATA_SECTION(section DATA X)
|
||||
#else
|
||||
#error "Please specify compiler."
|
||||
#endif
|
||||
|
||||
/* Functions prototypes */
|
||||
/******************************************************************************/
|
||||
void Ifx_C_Init(void);
|
||||
/******************************************************************************/
|
||||
|
||||
|
||||
#endif /* COMPILERS_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,468 @@
|
||||
/**
|
||||
* \file IfxAsclin_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_Cfg Asclin address
|
||||
* \ingroup IfxLld_Asclin
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Asclin_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_Cfg_Asclin0 2-ASCLIN0
|
||||
* \ingroup IfxLld_Asclin_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_Cfg_Asclin1 2-ASCLIN1
|
||||
* \ingroup IfxLld_Asclin_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_Cfg_Asclin2 2-ASCLIN2
|
||||
* \ingroup IfxLld_Asclin_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_Cfg_Asclin3 2-ASCLIN3
|
||||
* \ingroup IfxLld_Asclin_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXASCLIN_REG_H
|
||||
#define IFXASCLIN_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxAsclin_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief ASCLIN object */
|
||||
#define MODULE_ASCLIN0 /*lint --e(923)*/ (*(Ifx_ASCLIN*)0xF0000600u)
|
||||
|
||||
/** \brief ASCLIN object */
|
||||
#define MODULE_ASCLIN1 /*lint --e(923)*/ (*(Ifx_ASCLIN*)0xF0000700u)
|
||||
|
||||
/** \brief ASCLIN object */
|
||||
#define MODULE_ASCLIN2 /*lint --e(923)*/ (*(Ifx_ASCLIN*)0xF0000800u)
|
||||
|
||||
/** \brief ASCLIN object */
|
||||
#define MODULE_ASCLIN3 /*lint --e(923)*/ (*(Ifx_ASCLIN*)0xF0000900u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_Cfg_Asclin0
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define ASCLIN0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00006FCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define ASCLIN0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00006F8u)
|
||||
|
||||
/** \brief 14, Bit Configuration Register */
|
||||
#define ASCLIN0_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000614u)
|
||||
|
||||
/** \brief 24, Baud Rate Detection Register */
|
||||
#define ASCLIN0_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000624u)
|
||||
|
||||
/** \brief 20, Baud Rate Generation Register */
|
||||
#define ASCLIN0_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000620u)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define ASCLIN0_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000600u)
|
||||
|
||||
/** \brief 4C, Clock Selection Register */
|
||||
#define ASCLIN0_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000064Cu)
|
||||
|
||||
/** \brief 1C, Data Configuration Register */
|
||||
#define ASCLIN0_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000061Cu)
|
||||
|
||||
/** \brief 34, Flags Register */
|
||||
#define ASCLIN0_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000634u)
|
||||
|
||||
/** \brief 3C, Flags Clear Register */
|
||||
#define ASCLIN0_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000063Cu)
|
||||
|
||||
/** \brief 40, Flags Enable Register */
|
||||
#define ASCLIN0_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000640u)
|
||||
|
||||
/** \brief 38, Flags Set Register */
|
||||
#define ASCLIN0_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000638u)
|
||||
|
||||
/** \brief 18, Frame Control Register */
|
||||
#define ASCLIN0_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000618u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define ASCLIN0_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000608u)
|
||||
|
||||
/** \brief 4, Input and Output Control Register */
|
||||
#define ASCLIN0_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000604u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define ASCLIN0_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00006F4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define ASCLIN0_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00006F0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define ASCLIN0_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00006ECu)
|
||||
|
||||
/** \brief 2C, LIN Break Timer Register */
|
||||
#define ASCLIN0_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000062Cu)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN0_LIN_BTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN0_LIN_BTIMER.
|
||||
*/
|
||||
#define ASCLIN0_LINBTIMER (ASCLIN0_LIN_BTIMER)
|
||||
|
||||
/** \brief 28, LIN Control Register */
|
||||
#define ASCLIN0_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000628u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN0_LIN_CON.
|
||||
* To use register names with standard convension, please use ASCLIN0_LIN_CON.
|
||||
*/
|
||||
#define ASCLIN0_LINCON (ASCLIN0_LIN_CON)
|
||||
|
||||
/** \brief 30, LIN Header Timer Register */
|
||||
#define ASCLIN0_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000630u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN0_LIN_HTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN0_LIN_HTIMER.
|
||||
*/
|
||||
#define ASCLIN0_LINHTIMER (ASCLIN0_LIN_HTIMER)
|
||||
|
||||
/** \brief E8, OCDS Control and Status */
|
||||
#define ASCLIN0_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00006E8u)
|
||||
|
||||
/** \brief 48, Receive Data Register */
|
||||
#define ASCLIN0_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000648u)
|
||||
|
||||
/** \brief 50, Receive Data Debug Register */
|
||||
#define ASCLIN0_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000650u)
|
||||
|
||||
/** \brief 10, RX FIFO Configuration Register */
|
||||
#define ASCLIN0_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000610u)
|
||||
|
||||
/** \brief 44, Transmit Data Register */
|
||||
#define ASCLIN0_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000644u)
|
||||
|
||||
/** \brief C, TX FIFO Configuration Register */
|
||||
#define ASCLIN0_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000060Cu)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_Cfg_Asclin1
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define ASCLIN1_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00007FCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define ASCLIN1_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00007F8u)
|
||||
|
||||
/** \brief 14, Bit Configuration Register */
|
||||
#define ASCLIN1_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000714u)
|
||||
|
||||
/** \brief 24, Baud Rate Detection Register */
|
||||
#define ASCLIN1_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000724u)
|
||||
|
||||
/** \brief 20, Baud Rate Generation Register */
|
||||
#define ASCLIN1_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000720u)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define ASCLIN1_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000700u)
|
||||
|
||||
/** \brief 4C, Clock Selection Register */
|
||||
#define ASCLIN1_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000074Cu)
|
||||
|
||||
/** \brief 1C, Data Configuration Register */
|
||||
#define ASCLIN1_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000071Cu)
|
||||
|
||||
/** \brief 34, Flags Register */
|
||||
#define ASCLIN1_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000734u)
|
||||
|
||||
/** \brief 3C, Flags Clear Register */
|
||||
#define ASCLIN1_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000073Cu)
|
||||
|
||||
/** \brief 40, Flags Enable Register */
|
||||
#define ASCLIN1_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000740u)
|
||||
|
||||
/** \brief 38, Flags Set Register */
|
||||
#define ASCLIN1_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000738u)
|
||||
|
||||
/** \brief 18, Frame Control Register */
|
||||
#define ASCLIN1_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000718u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define ASCLIN1_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000708u)
|
||||
|
||||
/** \brief 4, Input and Output Control Register */
|
||||
#define ASCLIN1_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000704u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define ASCLIN1_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00007F4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define ASCLIN1_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00007F0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define ASCLIN1_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00007ECu)
|
||||
|
||||
/** \brief 2C, LIN Break Timer Register */
|
||||
#define ASCLIN1_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000072Cu)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN1_LIN_BTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN1_LIN_BTIMER.
|
||||
*/
|
||||
#define ASCLIN1_LINBTIMER (ASCLIN1_LIN_BTIMER)
|
||||
|
||||
/** \brief 28, LIN Control Register */
|
||||
#define ASCLIN1_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000728u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN1_LIN_CON.
|
||||
* To use register names with standard convension, please use ASCLIN1_LIN_CON.
|
||||
*/
|
||||
#define ASCLIN1_LINCON (ASCLIN1_LIN_CON)
|
||||
|
||||
/** \brief 30, LIN Header Timer Register */
|
||||
#define ASCLIN1_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000730u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN1_LIN_HTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN1_LIN_HTIMER.
|
||||
*/
|
||||
#define ASCLIN1_LINHTIMER (ASCLIN1_LIN_HTIMER)
|
||||
|
||||
/** \brief E8, OCDS Control and Status */
|
||||
#define ASCLIN1_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00007E8u)
|
||||
|
||||
/** \brief 48, Receive Data Register */
|
||||
#define ASCLIN1_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000748u)
|
||||
|
||||
/** \brief 50, Receive Data Debug Register */
|
||||
#define ASCLIN1_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000750u)
|
||||
|
||||
/** \brief 10, RX FIFO Configuration Register */
|
||||
#define ASCLIN1_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000710u)
|
||||
|
||||
/** \brief 44, Transmit Data Register */
|
||||
#define ASCLIN1_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000744u)
|
||||
|
||||
/** \brief C, TX FIFO Configuration Register */
|
||||
#define ASCLIN1_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000070Cu)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_Cfg_Asclin2
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define ASCLIN2_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00008FCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define ASCLIN2_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00008F8u)
|
||||
|
||||
/** \brief 14, Bit Configuration Register */
|
||||
#define ASCLIN2_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000814u)
|
||||
|
||||
/** \brief 24, Baud Rate Detection Register */
|
||||
#define ASCLIN2_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000824u)
|
||||
|
||||
/** \brief 20, Baud Rate Generation Register */
|
||||
#define ASCLIN2_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000820u)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define ASCLIN2_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000800u)
|
||||
|
||||
/** \brief 4C, Clock Selection Register */
|
||||
#define ASCLIN2_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000084Cu)
|
||||
|
||||
/** \brief 1C, Data Configuration Register */
|
||||
#define ASCLIN2_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000081Cu)
|
||||
|
||||
/** \brief 34, Flags Register */
|
||||
#define ASCLIN2_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000834u)
|
||||
|
||||
/** \brief 3C, Flags Clear Register */
|
||||
#define ASCLIN2_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000083Cu)
|
||||
|
||||
/** \brief 40, Flags Enable Register */
|
||||
#define ASCLIN2_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000840u)
|
||||
|
||||
/** \brief 38, Flags Set Register */
|
||||
#define ASCLIN2_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000838u)
|
||||
|
||||
/** \brief 18, Frame Control Register */
|
||||
#define ASCLIN2_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000818u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define ASCLIN2_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000808u)
|
||||
|
||||
/** \brief 4, Input and Output Control Register */
|
||||
#define ASCLIN2_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000804u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define ASCLIN2_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00008F4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define ASCLIN2_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00008F0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define ASCLIN2_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00008ECu)
|
||||
|
||||
/** \brief 2C, LIN Break Timer Register */
|
||||
#define ASCLIN2_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000082Cu)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN2_LIN_BTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN2_LIN_BTIMER.
|
||||
*/
|
||||
#define ASCLIN2_LINBTIMER (ASCLIN2_LIN_BTIMER)
|
||||
|
||||
/** \brief 28, LIN Control Register */
|
||||
#define ASCLIN2_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000828u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN2_LIN_CON.
|
||||
* To use register names with standard convension, please use ASCLIN2_LIN_CON.
|
||||
*/
|
||||
#define ASCLIN2_LINCON (ASCLIN2_LIN_CON)
|
||||
|
||||
/** \brief 30, LIN Header Timer Register */
|
||||
#define ASCLIN2_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000830u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN2_LIN_HTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN2_LIN_HTIMER.
|
||||
*/
|
||||
#define ASCLIN2_LINHTIMER (ASCLIN2_LIN_HTIMER)
|
||||
|
||||
/** \brief E8, OCDS Control and Status */
|
||||
#define ASCLIN2_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00008E8u)
|
||||
|
||||
/** \brief 48, Receive Data Register */
|
||||
#define ASCLIN2_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000848u)
|
||||
|
||||
/** \brief 50, Receive Data Debug Register */
|
||||
#define ASCLIN2_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000850u)
|
||||
|
||||
/** \brief 10, RX FIFO Configuration Register */
|
||||
#define ASCLIN2_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000810u)
|
||||
|
||||
/** \brief 44, Transmit Data Register */
|
||||
#define ASCLIN2_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000844u)
|
||||
|
||||
/** \brief C, TX FIFO Configuration Register */
|
||||
#define ASCLIN2_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000080Cu)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_Cfg_Asclin3
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define ASCLIN3_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN0*)0xF00009FCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define ASCLIN3_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ACCEN1*)0xF00009F8u)
|
||||
|
||||
/** \brief 14, Bit Configuration Register */
|
||||
#define ASCLIN3_BITCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BITCON*)0xF0000914u)
|
||||
|
||||
/** \brief 24, Baud Rate Detection Register */
|
||||
#define ASCLIN3_BRD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRD*)0xF0000924u)
|
||||
|
||||
/** \brief 20, Baud Rate Generation Register */
|
||||
#define ASCLIN3_BRG /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_BRG*)0xF0000920u)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define ASCLIN3_CLC /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CLC*)0xF0000900u)
|
||||
|
||||
/** \brief 4C, Clock Selection Register */
|
||||
#define ASCLIN3_CSR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_CSR*)0xF000094Cu)
|
||||
|
||||
/** \brief 1C, Data Configuration Register */
|
||||
#define ASCLIN3_DATCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_DATCON*)0xF000091Cu)
|
||||
|
||||
/** \brief 34, Flags Register */
|
||||
#define ASCLIN3_FLAGS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGS*)0xF0000934u)
|
||||
|
||||
/** \brief 3C, Flags Clear Register */
|
||||
#define ASCLIN3_FLAGSCLEAR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSCLEAR*)0xF000093Cu)
|
||||
|
||||
/** \brief 40, Flags Enable Register */
|
||||
#define ASCLIN3_FLAGSENABLE /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSENABLE*)0xF0000940u)
|
||||
|
||||
/** \brief 38, Flags Set Register */
|
||||
#define ASCLIN3_FLAGSSET /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FLAGSSET*)0xF0000938u)
|
||||
|
||||
/** \brief 18, Frame Control Register */
|
||||
#define ASCLIN3_FRAMECON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_FRAMECON*)0xF0000918u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define ASCLIN3_ID /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_ID*)0xF0000908u)
|
||||
|
||||
/** \brief 4, Input and Output Control Register */
|
||||
#define ASCLIN3_IOCR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_IOCR*)0xF0000904u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define ASCLIN3_KRST0 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST0*)0xF00009F4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define ASCLIN3_KRST1 /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRST1*)0xF00009F0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define ASCLIN3_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_KRSTCLR*)0xF00009ECu)
|
||||
|
||||
/** \brief 2C, LIN Break Timer Register */
|
||||
#define ASCLIN3_LIN_BTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_BTIMER*)0xF000092Cu)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN3_LIN_BTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN3_LIN_BTIMER.
|
||||
*/
|
||||
#define ASCLIN3_LINBTIMER (ASCLIN3_LIN_BTIMER)
|
||||
|
||||
/** \brief 28, LIN Control Register */
|
||||
#define ASCLIN3_LIN_CON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_CON*)0xF0000928u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN3_LIN_CON.
|
||||
* To use register names with standard convension, please use ASCLIN3_LIN_CON.
|
||||
*/
|
||||
#define ASCLIN3_LINCON (ASCLIN3_LIN_CON)
|
||||
|
||||
/** \brief 30, LIN Header Timer Register */
|
||||
#define ASCLIN3_LIN_HTIMER /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_LIN_HTIMER*)0xF0000930u)
|
||||
|
||||
/** Alias (User Manual Name) for ASCLIN3_LIN_HTIMER.
|
||||
* To use register names with standard convension, please use ASCLIN3_LIN_HTIMER.
|
||||
*/
|
||||
#define ASCLIN3_LINHTIMER (ASCLIN3_LIN_HTIMER)
|
||||
|
||||
/** \brief E8, OCDS Control and Status */
|
||||
#define ASCLIN3_OCS /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_OCS*)0xF00009E8u)
|
||||
|
||||
/** \brief 48, Receive Data Register */
|
||||
#define ASCLIN3_RXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATA*)0xF0000948u)
|
||||
|
||||
/** \brief 50, Receive Data Debug Register */
|
||||
#define ASCLIN3_RXDATAD /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXDATAD*)0xF0000950u)
|
||||
|
||||
/** \brief 10, RX FIFO Configuration Register */
|
||||
#define ASCLIN3_RXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_RXFIFOCON*)0xF0000910u)
|
||||
|
||||
/** \brief 44, Transmit Data Register */
|
||||
#define ASCLIN3_TXDATA /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXDATA*)0xF0000944u)
|
||||
|
||||
/** \brief C, TX FIFO Configuration Register */
|
||||
#define ASCLIN3_TXFIFOCON /*lint --e(923)*/ (*(volatile Ifx_ASCLIN_TXFIFOCON*)0xF000090Cu)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXASCLIN_REG_H */
|
||||
@@ -0,0 +1,699 @@
|
||||
/**
|
||||
* \file IfxAsclin_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Asclin Asclin
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Asclin
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_union Union
|
||||
* \ingroup IfxLld_Asclin
|
||||
*
|
||||
* \defgroup IfxLld_Asclin_struct Struct
|
||||
* \ingroup IfxLld_Asclin
|
||||
*
|
||||
*/
|
||||
#ifndef IFXASCLIN_REGDEF_H
|
||||
#define IFXASCLIN_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_ASCLIN_ACCEN0_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_ASCLIN_ACCEN0_Bits;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef struct _Ifx_ASCLIN_ACCEN1_Bits
|
||||
{
|
||||
unsigned int reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_ACCEN1_Bits;
|
||||
|
||||
/** \brief Bit Configuration Register */
|
||||
typedef struct _Ifx_ASCLIN_BITCON_Bits
|
||||
{
|
||||
unsigned int PRESCALER:12; /**< \brief [11:0] Prescaling of the Fractional Divider (rw) */
|
||||
unsigned int reserved_12:4; /**< \brief \internal Reserved */
|
||||
unsigned int OVERSAMPLING:4; /**< \brief [19:16] Oversampling Factor (rw) */
|
||||
unsigned int reserved_20:4; /**< \brief \internal Reserved */
|
||||
unsigned int SAMPLEPOINT:4; /**< \brief [27:24] Sample Point Position (rw) */
|
||||
unsigned int reserved_28:3; /**< \brief \internal Reserved */
|
||||
unsigned int SM:1; /**< \brief [31:31] Sample Mode (rw) */
|
||||
} Ifx_ASCLIN_BITCON_Bits;
|
||||
|
||||
/** \brief Baud Rate Detection Register */
|
||||
typedef struct _Ifx_ASCLIN_BRD_Bits
|
||||
{
|
||||
unsigned int LOWERLIMIT:8; /**< \brief [7:0] Lower Limit (rw) */
|
||||
unsigned int UPPERLIMIT:8; /**< \brief [15:8] Upper Limit (rw) */
|
||||
unsigned int MEASURED:12; /**< \brief [27:16] Measured Value of the Denominator (rh) */
|
||||
unsigned int reserved_28:4; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_BRD_Bits;
|
||||
|
||||
/** \brief Baud Rate Generation Register */
|
||||
typedef struct _Ifx_ASCLIN_BRG_Bits
|
||||
{
|
||||
unsigned int DENOMINATOR:12; /**< \brief [11:0] Denominator (rw) */
|
||||
unsigned int reserved_12:4; /**< \brief \internal Reserved */
|
||||
unsigned int NUMERATOR:12; /**< \brief [27:16] Numerator (rw) */
|
||||
unsigned int reserved_28:4; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_BRG_Bits;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef struct _Ifx_ASCLIN_CLC_Bits
|
||||
{
|
||||
unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
|
||||
unsigned int reserved_2:1; /**< \brief \internal Reserved */
|
||||
unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_CLC_Bits;
|
||||
|
||||
/** \brief Clock Selection Register */
|
||||
typedef struct _Ifx_ASCLIN_CSR_Bits
|
||||
{
|
||||
unsigned int CLKSEL:5; /**< \brief [4:0] Baud Rate Logic Clock Select (rw) */
|
||||
unsigned int reserved_5:26; /**< \brief \internal Reserved */
|
||||
unsigned int CON:1; /**< \brief [31:31] Clock On Flag (rh) */
|
||||
} Ifx_ASCLIN_CSR_Bits;
|
||||
|
||||
/** \brief Data Configuration Register */
|
||||
typedef struct _Ifx_ASCLIN_DATCON_Bits
|
||||
{
|
||||
unsigned int DATLEN:4; /**< \brief [3:0] Data Length (rw) */
|
||||
unsigned int reserved_4:9; /**< \brief \internal Reserved */
|
||||
unsigned int HO:1; /**< \brief [13:13] Header Only (rw) */
|
||||
unsigned int RM:1; /**< \brief [14:14] Response Mode (rw) */
|
||||
unsigned int CSM:1; /**< \brief [15:15] Checksum Mode (rw) */
|
||||
unsigned int RESPONSE:8; /**< \brief [23:16] Response Timeout Threshold Value (rw) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_DATCON_Bits;
|
||||
|
||||
/** \brief Flags Register */
|
||||
typedef struct _Ifx_ASCLIN_FLAGS_Bits
|
||||
{
|
||||
unsigned int TH:1; /**< \brief [0:0] Transmit Header End Flag (rh) */
|
||||
unsigned int TR:1; /**< \brief [1:1] Transmit Response End Flag (rh) */
|
||||
unsigned int RH:1; /**< \brief [2:2] Receive Header End Flag (rh) */
|
||||
unsigned int RR:1; /**< \brief [3:3] Receive Response End Flag (rh) */
|
||||
unsigned int reserved_4:1; /**< \brief \internal Reserved */
|
||||
unsigned int FED:1; /**< \brief [5:5] Falling Edge from Level 1 to Level 0 Detected (rh) */
|
||||
unsigned int RED:1; /**< \brief [6:6] Rising Edge from Level 0 to Level 1 Detected (rh) */
|
||||
unsigned int reserved_7:6; /**< \brief \internal Reserved */
|
||||
unsigned int TWRQ:1; /**< \brief [13:13] Transmit Wake Request Flag (rh) */
|
||||
unsigned int THRQ:1; /**< \brief [14:14] Transmit Header Request Flag (rh) */
|
||||
unsigned int TRRQ:1; /**< \brief [15:15] Transmit Response Request Flag (rh) */
|
||||
unsigned int PE:1; /**< \brief [16:16] Parity Error Flag (rh) */
|
||||
unsigned int TC:1; /**< \brief [17:17] Transmission Completed Flag (rh) */
|
||||
unsigned int FE:1; /**< \brief [18:18] Framing Error Flag (rh) */
|
||||
unsigned int HT:1; /**< \brief [19:19] Header Timeout Flag (rh) */
|
||||
unsigned int RT:1; /**< \brief [20:20] Response Timeout Flag (rh) */
|
||||
unsigned int BD:1; /**< \brief [21:21] Break Detected Flag (rh) */
|
||||
unsigned int LP:1; /**< \brief [22:22] LIN Parity Error Flag (rh) */
|
||||
unsigned int LA:1; /**< \brief [23:23] LIN Autobaud Detection Error Flag (rh) */
|
||||
unsigned int LC:1; /**< \brief [24:24] LIN Checksum Error Flag (rh) */
|
||||
unsigned int CE:1; /**< \brief [25:25] Collision Detection Error Flag (rh) */
|
||||
unsigned int RFO:1; /**< \brief [26:26] Receive FIFO Overflow Flag (rh) */
|
||||
unsigned int RFU:1; /**< \brief [27:27] Receive FIFO Underflow Flag (rh) */
|
||||
unsigned int RFL:1; /**< \brief [28:28] Receive FIFO Level Flag (rh) */
|
||||
unsigned int reserved_29:1; /**< \brief \internal Reserved */
|
||||
unsigned int TFO:1; /**< \brief [30:30] Transmit FIFO Overflow Flag (rh) */
|
||||
unsigned int TFL:1; /**< \brief [31:31] Transmit FIFO Level Flag (rh) */
|
||||
} Ifx_ASCLIN_FLAGS_Bits;
|
||||
|
||||
/** \brief Flags Clear Register */
|
||||
typedef struct _Ifx_ASCLIN_FLAGSCLEAR_Bits
|
||||
{
|
||||
unsigned int THC:1; /**< \brief [0:0] Flag Clear Bit (w) */
|
||||
unsigned int TRC:1; /**< \brief [1:1] Flag Clear Bit (w) */
|
||||
unsigned int RHC:1; /**< \brief [2:2] Flag Clear Bit (w) */
|
||||
unsigned int RRC:1; /**< \brief [3:3] Flag Clear Bit (w) */
|
||||
unsigned int reserved_4:1; /**< \brief \internal Reserved */
|
||||
unsigned int FEDC:1; /**< \brief [5:5] Flag Clear Bit (w) */
|
||||
unsigned int REDC:1; /**< \brief [6:6] Flag Clear Bit (w) */
|
||||
unsigned int reserved_7:6; /**< \brief \internal Reserved */
|
||||
unsigned int TWRQC:1; /**< \brief [13:13] Flag Clear Bit (w) */
|
||||
unsigned int THRQC:1; /**< \brief [14:14] Flag Clear Bit (w) */
|
||||
unsigned int TRRQC:1; /**< \brief [15:15] Flag Clear Bit (w) */
|
||||
unsigned int PEC:1; /**< \brief [16:16] Flag Clear Bit (w) */
|
||||
unsigned int TCC:1; /**< \brief [17:17] Flag Clear Bit (w) */
|
||||
unsigned int FEC:1; /**< \brief [18:18] Flag Clear Bit (w) */
|
||||
unsigned int HTC:1; /**< \brief [19:19] Flag Clear Bit (w) */
|
||||
unsigned int RTC:1; /**< \brief [20:20] Flag Clear Bit (w) */
|
||||
unsigned int BDC:1; /**< \brief [21:21] Flag Clear Bit (w) */
|
||||
unsigned int LPC:1; /**< \brief [22:22] Flag Clear Bit (w) */
|
||||
unsigned int LAC:1; /**< \brief [23:23] Flag Clear Bit (w) */
|
||||
unsigned int LCC:1; /**< \brief [24:24] Flag Clear Bit (w) */
|
||||
unsigned int CEC:1; /**< \brief [25:25] Flag Clear Bit (w) */
|
||||
unsigned int RFOC:1; /**< \brief [26:26] Flag Clear Bit (w) */
|
||||
unsigned int RFUC:1; /**< \brief [27:27] Flag Clear Bit (w) */
|
||||
unsigned int RFLC:1; /**< \brief [28:28] Flag Clear Bit (w) */
|
||||
unsigned int reserved_29:1; /**< \brief \internal Reserved */
|
||||
unsigned int TFOC:1; /**< \brief [30:30] Flag Clear Bit (w) */
|
||||
unsigned int TFLC:1; /**< \brief [31:31] Flag Clear Bit (w) */
|
||||
} Ifx_ASCLIN_FLAGSCLEAR_Bits;
|
||||
|
||||
/** \brief Flags Enable Register */
|
||||
typedef struct _Ifx_ASCLIN_FLAGSENABLE_Bits
|
||||
{
|
||||
unsigned int THE:1; /**< \brief [0:0] Flag Enable Bit (rw) */
|
||||
unsigned int TRE:1; /**< \brief [1:1] Flag Enable Bit (rw) */
|
||||
unsigned int RHE:1; /**< \brief [2:2] Flag Enable Bit (rw) */
|
||||
unsigned int RRE:1; /**< \brief [3:3] Flag Enable Bit (rw) */
|
||||
unsigned int reserved_4:1; /**< \brief \internal Reserved */
|
||||
unsigned int FEDE:1; /**< \brief [5:5] Flag Enable Bit (rw) */
|
||||
unsigned int REDE:1; /**< \brief [6:6] Flag Enable Bit (rw) */
|
||||
unsigned int reserved_7:9; /**< \brief \internal Reserved */
|
||||
unsigned int PEE:1; /**< \brief [16:16] Flag Enable Bit (rw) */
|
||||
unsigned int TCE:1; /**< \brief [17:17] Flag Enable Bit (rw) */
|
||||
unsigned int FEE:1; /**< \brief [18:18] Flag Enable Bit (rw) */
|
||||
unsigned int HTE:1; /**< \brief [19:19] Flag Enable Bit (rw) */
|
||||
unsigned int RTE:1; /**< \brief [20:20] Flag Enable Bit (rw) */
|
||||
unsigned int BDE:1; /**< \brief [21:21] Flag Enable Bit (rw) */
|
||||
unsigned int LPE:1; /**< \brief [22:22] Flag Enable Bit (rw) */
|
||||
unsigned int ABE:1; /**< \brief [23:23] Flag Enable Bit (rw) */
|
||||
unsigned int LCE:1; /**< \brief [24:24] Flag Enable Bit (rw) */
|
||||
unsigned int CEE:1; /**< \brief [25:25] Flag Enable Bit (rw) */
|
||||
unsigned int RFOE:1; /**< \brief [26:26] Flag Enable Bit (rw) */
|
||||
unsigned int RFUE:1; /**< \brief [27:27] Flag Enable Bit (rw) */
|
||||
unsigned int RFLE:1; /**< \brief [28:28] Flag Enable Bit (rw) */
|
||||
unsigned int reserved_29:1; /**< \brief \internal Reserved */
|
||||
unsigned int TFOE:1; /**< \brief [30:30] Flag Enable Bit (rw) */
|
||||
unsigned int TFLE:1; /**< \brief [31:31] Flag Enable Bit (rw) */
|
||||
} Ifx_ASCLIN_FLAGSENABLE_Bits;
|
||||
|
||||
/** \brief Flags Set Register */
|
||||
typedef struct _Ifx_ASCLIN_FLAGSSET_Bits
|
||||
{
|
||||
unsigned int THS:1; /**< \brief [0:0] Flag Set Bit (w) */
|
||||
unsigned int TRS:1; /**< \brief [1:1] Flag Set Bit (w) */
|
||||
unsigned int RHS:1; /**< \brief [2:2] Flag Set Bit (w) */
|
||||
unsigned int RRS:1; /**< \brief [3:3] Flag Set Bit (w) */
|
||||
unsigned int reserved_4:1; /**< \brief \internal Reserved */
|
||||
unsigned int FEDS:1; /**< \brief [5:5] Flag Set Bit (w) */
|
||||
unsigned int REDS:1; /**< \brief [6:6] Flag Set Bit (w) */
|
||||
unsigned int reserved_7:6; /**< \brief \internal Reserved */
|
||||
unsigned int TWRQS:1; /**< \brief [13:13] Flag Set Bit (w) */
|
||||
unsigned int THRQS:1; /**< \brief [14:14] Flag Set Bit (w) */
|
||||
unsigned int TRRQS:1; /**< \brief [15:15] Flag Set Bit (w) */
|
||||
unsigned int PES:1; /**< \brief [16:16] Flag Set Bit (w) */
|
||||
unsigned int TCS:1; /**< \brief [17:17] Flag Set Bit (w) */
|
||||
unsigned int FES:1; /**< \brief [18:18] Flag Set Bit (w) */
|
||||
unsigned int HTS:1; /**< \brief [19:19] Flag Set Bit (w) */
|
||||
unsigned int RTS:1; /**< \brief [20:20] Flag Set Bit (w) */
|
||||
unsigned int BDS:1; /**< \brief [21:21] Flag Set Bit (w) */
|
||||
unsigned int LPS:1; /**< \brief [22:22] Flag Set Bit (w) */
|
||||
unsigned int LAS:1; /**< \brief [23:23] Flag Set Bit (w) */
|
||||
unsigned int LCS:1; /**< \brief [24:24] Flag Set Bit (w) */
|
||||
unsigned int CES:1; /**< \brief [25:25] Flag Set Bit (w) */
|
||||
unsigned int RFOS:1; /**< \brief [26:26] Flag Set Bit (w) */
|
||||
unsigned int RFUS:1; /**< \brief [27:27] Flag Set Bit (w) */
|
||||
unsigned int RFLS:1; /**< \brief [28:28] Flag Set Bit (w) */
|
||||
unsigned int reserved_29:1; /**< \brief \internal Reserved */
|
||||
unsigned int TFOS:1; /**< \brief [30:30] Flag Set Bit (w) */
|
||||
unsigned int TFLS:1; /**< \brief [31:31] Flag Set Bit (w) */
|
||||
} Ifx_ASCLIN_FLAGSSET_Bits;
|
||||
|
||||
/** \brief Frame Control Register */
|
||||
typedef struct _Ifx_ASCLIN_FRAMECON_Bits
|
||||
{
|
||||
unsigned int reserved_0:6; /**< \brief \internal Reserved */
|
||||
unsigned int IDLE:3; /**< \brief [8:6] Duration of the IDLE delay (rw) */
|
||||
unsigned int STOP:3; /**< \brief [11:9] Number of Stop Bits (rw) */
|
||||
unsigned int LEAD:3; /**< \brief [14:12] Duration of the Leading Delay (rw) */
|
||||
unsigned int reserved_15:1; /**< \brief \internal Reserved */
|
||||
unsigned int MODE:2; /**< \brief [17:16] Mode Selection (rw) */
|
||||
unsigned int reserved_18:10; /**< \brief \internal Reserved */
|
||||
unsigned int MSB:1; /**< \brief [28:28] Shift Direction (rw) */
|
||||
unsigned int CEN:1; /**< \brief [29:29] Collision Detection Enable (rw) */
|
||||
unsigned int PEN:1; /**< \brief [30:30] Parity Enable (rw) */
|
||||
unsigned int ODD:1; /**< \brief [31:31] Parity Type (rw) */
|
||||
} Ifx_ASCLIN_FRAMECON_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_ASCLIN_ID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_ASCLIN_ID_Bits;
|
||||
|
||||
/** \brief Input and Output Control Register */
|
||||
typedef struct _Ifx_ASCLIN_IOCR_Bits
|
||||
{
|
||||
unsigned int ALTI:3; /**< \brief [2:0] Alternate Input Select (rw) */
|
||||
unsigned int reserved_3:1; /**< \brief \internal Reserved */
|
||||
unsigned int DEPTH:6; /**< \brief [9:4] Digital Glitch Filter Depth (rw) */
|
||||
unsigned int reserved_10:6; /**< \brief \internal Reserved */
|
||||
unsigned int CTS:2; /**< \brief [17:16] CTS Select (rw) */
|
||||
unsigned int reserved_18:7; /**< \brief \internal Reserved */
|
||||
unsigned int RCPOL:1; /**< \brief [25:25] RTS CTS Polarity (rw) */
|
||||
unsigned int CPOL:1; /**< \brief [26:26] Clock Polarity in Synchronous Mode (rw) */
|
||||
unsigned int SPOL:1; /**< \brief [27:27] Slave Polarity in Synchronous Mode (rw) */
|
||||
unsigned int LB:1; /**< \brief [28:28] Loop Back Mode (rw) */
|
||||
unsigned int CTSEN:1; /**< \brief [29:29] Input Signal CTS Enable (rw) */
|
||||
unsigned int RXM:1; /**< \brief [30:30] Receive Monitor (rh) */
|
||||
unsigned int TXM:1; /**< \brief [31:31] Transmit Monitor (rh) */
|
||||
} Ifx_ASCLIN_IOCR_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef struct _Ifx_ASCLIN_KRST0_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_KRST0_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef struct _Ifx_ASCLIN_KRST1_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_KRST1_Bits;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef struct _Ifx_ASCLIN_KRSTCLR_Bits
|
||||
{
|
||||
unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_KRSTCLR_Bits;
|
||||
|
||||
/** \brief LIN Break Timer Register */
|
||||
typedef struct _Ifx_ASCLIN_LIN_BTIMER_Bits
|
||||
{
|
||||
unsigned int BREAK:6; /**< \brief [5:0] Break Pulse Generation and Detection (rw) */
|
||||
unsigned int reserved_6:26; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_LIN_BTIMER_Bits;
|
||||
|
||||
/** \brief LIN Control Register */
|
||||
typedef struct _Ifx_ASCLIN_LIN_CON_Bits
|
||||
{
|
||||
unsigned int reserved_0:23; /**< \brief \internal Reserved */
|
||||
unsigned int CSI:1; /**< \brief [23:23] Checksum Injection (rw) */
|
||||
unsigned int reserved_24:1; /**< \brief \internal Reserved */
|
||||
unsigned int CSEN:1; /**< \brief [25:25] Hardware Checksum Enable (rw) */
|
||||
unsigned int MS:1; /**< \brief [26:26] Master Slave Mode (rw) */
|
||||
unsigned int ABD:1; /**< \brief [27:27] Autobaud Detection (rw) */
|
||||
unsigned int reserved_28:4; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_LIN_CON_Bits;
|
||||
|
||||
/** \brief LIN Header Timer Register */
|
||||
typedef struct _Ifx_ASCLIN_LIN_HTIMER_Bits
|
||||
{
|
||||
unsigned int HEADER:8; /**< \brief [7:0] Header Timeout Threshold Value (rw) */
|
||||
unsigned int reserved_8:24; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_LIN_HTIMER_Bits;
|
||||
|
||||
/** \brief OCDS Control and Status */
|
||||
typedef struct _Ifx_ASCLIN_OCS_Bits
|
||||
{
|
||||
unsigned int reserved_0:24; /**< \brief \internal Reserved */
|
||||
unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
|
||||
unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
|
||||
unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
|
||||
unsigned int reserved_30:2; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_OCS_Bits;
|
||||
|
||||
/** \brief Receive Data Register */
|
||||
typedef struct _Ifx_ASCLIN_RXDATA_Bits
|
||||
{
|
||||
unsigned int DATA:32; /**< \brief [31:0] Data (rh) */
|
||||
} Ifx_ASCLIN_RXDATA_Bits;
|
||||
|
||||
/** \brief Receive Data Debug Register */
|
||||
typedef struct _Ifx_ASCLIN_RXDATAD_Bits
|
||||
{
|
||||
unsigned int DATA:32; /**< \brief [31:0] Data (rh) */
|
||||
} Ifx_ASCLIN_RXDATAD_Bits;
|
||||
|
||||
/** \brief RX FIFO Configuration Register */
|
||||
typedef struct _Ifx_ASCLIN_RXFIFOCON_Bits
|
||||
{
|
||||
unsigned int FLUSH:1; /**< \brief [0:0] Flush the receive FIFO (w) */
|
||||
unsigned int ENI:1; /**< \brief [1:1] Receive FIFO Inlet Enable (rwh) */
|
||||
unsigned int reserved_2:4; /**< \brief \internal Reserved */
|
||||
unsigned int OUTW:2; /**< \brief [7:6] Receive FIFO Outlet Width (rw) */
|
||||
unsigned int INTLEVEL:4; /**< \brief [11:8] FIFO Interrupt Level (rw) */
|
||||
unsigned int reserved_12:4; /**< \brief \internal Reserved */
|
||||
unsigned int FILL:5; /**< \brief [20:16] FIFO Filling Level (rh) */
|
||||
unsigned int reserved_21:10; /**< \brief \internal Reserved */
|
||||
unsigned int BUF:1; /**< \brief [31:31] Receive Buffer Mode (rw) */
|
||||
} Ifx_ASCLIN_RXFIFOCON_Bits;
|
||||
|
||||
/** \brief Transmit Data Register */
|
||||
typedef struct _Ifx_ASCLIN_TXDATA_Bits
|
||||
{
|
||||
unsigned int DATA:32; /**< \brief [31:0] Data (w) */
|
||||
} Ifx_ASCLIN_TXDATA_Bits;
|
||||
|
||||
/** \brief TX FIFO Configuration Register */
|
||||
typedef struct _Ifx_ASCLIN_TXFIFOCON_Bits
|
||||
{
|
||||
unsigned int FLUSH:1; /**< \brief [0:0] Flush the transmit FIFO (w) */
|
||||
unsigned int ENO:1; /**< \brief [1:1] Transmit FIFO Outlet Enable (rw) */
|
||||
unsigned int reserved_2:4; /**< \brief \internal Reserved */
|
||||
unsigned int INW:2; /**< \brief [7:6] Transmit FIFO Inlet Width (rw) */
|
||||
unsigned int INTLEVEL:4; /**< \brief [11:8] FIFO Interrupt Level (rw) */
|
||||
unsigned int reserved_12:4; /**< \brief \internal Reserved */
|
||||
unsigned int FILL:5; /**< \brief [20:16] FIFO Filling Level (rh) */
|
||||
unsigned int reserved_21:11; /**< \brief \internal Reserved */
|
||||
} Ifx_ASCLIN_TXFIFOCON_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_ACCEN0;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_ACCEN1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_ACCEN1;
|
||||
|
||||
/** \brief Bit Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_BITCON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_BITCON;
|
||||
|
||||
/** \brief Baud Rate Detection Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_BRD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_BRD;
|
||||
|
||||
/** \brief Baud Rate Generation Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_BRG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_BRG;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_CLC;
|
||||
|
||||
/** \brief Clock Selection Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_CSR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_CSR;
|
||||
|
||||
/** \brief Data Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_DATCON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_DATCON;
|
||||
|
||||
/** \brief Flags Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_FLAGS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_FLAGS;
|
||||
|
||||
/** \brief Flags Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_FLAGSCLEAR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_FLAGSCLEAR;
|
||||
|
||||
/** \brief Flags Enable Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_FLAGSENABLE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_FLAGSENABLE;
|
||||
|
||||
/** \brief Flags Set Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_FLAGSSET_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_FLAGSSET;
|
||||
|
||||
/** \brief Frame Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_FRAMECON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_FRAMECON;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_ID;
|
||||
|
||||
/** \brief Input and Output Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_IOCR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_IOCR;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_KRST0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_KRST0;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_KRST1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_KRST1;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_KRSTCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_KRSTCLR;
|
||||
|
||||
/** \brief LIN Break Timer Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_LIN_BTIMER_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_LIN_BTIMER;
|
||||
|
||||
/** \brief LIN Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_LIN_CON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_LIN_CON;
|
||||
|
||||
/** \brief LIN Header Timer Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_LIN_HTIMER_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_LIN_HTIMER;
|
||||
|
||||
/** \brief OCDS Control and Status */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_OCS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_OCS;
|
||||
|
||||
/** \brief Receive Data Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_RXDATA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_RXDATA;
|
||||
|
||||
/** \brief Receive Data Debug Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_RXDATAD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_RXDATAD;
|
||||
|
||||
/** \brief RX FIFO Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_RXFIFOCON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_RXFIFOCON;
|
||||
|
||||
/** \brief Transmit Data Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_TXDATA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_TXDATA;
|
||||
|
||||
/** \brief TX FIFO Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_ASCLIN_TXFIFOCON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_ASCLIN_TXFIFOCON;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L1
|
||||
* \{ */
|
||||
|
||||
/** \brief LIN */
|
||||
typedef volatile struct _Ifx_ASCLIN_LIN
|
||||
{
|
||||
Ifx_ASCLIN_LIN_CON CON; /**< \brief 0, LIN Control Register */
|
||||
Ifx_ASCLIN_LIN_BTIMER BTIMER; /**< \brief 4, LIN Break Timer Register */
|
||||
Ifx_ASCLIN_LIN_HTIMER HTIMER; /**< \brief 8, LIN Header Timer Register */
|
||||
} Ifx_ASCLIN_LIN;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Asclin_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief ASCLIN object */
|
||||
typedef volatile struct _Ifx_ASCLIN
|
||||
{
|
||||
Ifx_ASCLIN_CLC CLC; /**< \brief 0, Clock Control Register */
|
||||
Ifx_ASCLIN_IOCR IOCR; /**< \brief 4, Input and Output Control Register */
|
||||
Ifx_ASCLIN_ID ID; /**< \brief 8, Module Identification Register */
|
||||
Ifx_ASCLIN_TXFIFOCON TXFIFOCON; /**< \brief C, TX FIFO Configuration Register */
|
||||
Ifx_ASCLIN_RXFIFOCON RXFIFOCON; /**< \brief 10, RX FIFO Configuration Register */
|
||||
Ifx_ASCLIN_BITCON BITCON; /**< \brief 14, Bit Configuration Register */
|
||||
Ifx_ASCLIN_FRAMECON FRAMECON; /**< \brief 18, Frame Control Register */
|
||||
Ifx_ASCLIN_DATCON DATCON; /**< \brief 1C, Data Configuration Register */
|
||||
Ifx_ASCLIN_BRG BRG; /**< \brief 20, Baud Rate Generation Register */
|
||||
Ifx_ASCLIN_BRD BRD; /**< \brief 24, Baud Rate Detection Register */
|
||||
Ifx_ASCLIN_LIN LIN; /**< \brief 28, LIN */
|
||||
Ifx_ASCLIN_FLAGS FLAGS; /**< \brief 34, Flags Register */
|
||||
Ifx_ASCLIN_FLAGSSET FLAGSSET; /**< \brief 38, Flags Set Register */
|
||||
Ifx_ASCLIN_FLAGSCLEAR FLAGSCLEAR; /**< \brief 3C, Flags Clear Register */
|
||||
Ifx_ASCLIN_FLAGSENABLE FLAGSENABLE; /**< \brief 40, Flags Enable Register */
|
||||
Ifx_ASCLIN_TXDATA TXDATA; /**< \brief 44, Transmit Data Register */
|
||||
Ifx_ASCLIN_RXDATA RXDATA; /**< \brief 48, Receive Data Register */
|
||||
Ifx_ASCLIN_CSR CSR; /**< \brief 4C, Clock Selection Register */
|
||||
Ifx_ASCLIN_RXDATAD RXDATAD; /**< \brief 50, Receive Data Debug Register */
|
||||
unsigned char reserved_54[148]; /**< \brief 54, \internal Reserved */
|
||||
Ifx_ASCLIN_OCS OCS; /**< \brief E8, OCDS Control and Status */
|
||||
Ifx_ASCLIN_KRSTCLR KRSTCLR; /**< \brief EC, Kernel Reset Status Clear Register */
|
||||
Ifx_ASCLIN_KRST1 KRST1; /**< \brief F0, Kernel Reset Register 1 */
|
||||
Ifx_ASCLIN_KRST0 KRST0; /**< \brief F4, Kernel Reset Register 0 */
|
||||
Ifx_ASCLIN_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
|
||||
Ifx_ASCLIN_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
|
||||
} Ifx_ASCLIN;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXASCLIN_REGDEF_H */
|
||||
File diff suppressed because it is too large
Load Diff
33560
Example/13-FFT_Demo/Libraries/BaseSw/Infra/Sfr/TC26B/_Reg/IfxCan_reg.h
Normal file
33560
Example/13-FFT_Demo/Libraries/BaseSw/Infra/Sfr/TC26B/_Reg/IfxCan_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,269 @@
|
||||
/**
|
||||
* \file IfxCbs_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Cbs_Cfg Cbs address
|
||||
* \ingroup IfxLld_Cbs
|
||||
*
|
||||
* \defgroup IfxLld_Cbs_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Cbs_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Cbs_Cfg_Cbs 2-CBS
|
||||
* \ingroup IfxLld_Cbs_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXCBS_REG_H
|
||||
#define IFXCBS_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxCbs_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Cbs_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief CBS object */
|
||||
#define MODULE_CBS /*lint --e(923)*/ (*(Ifx_CBS*)0xF0000400u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Cbs_Cfg_Cbs
|
||||
* \{ */
|
||||
|
||||
/** \brief 68, Communication Mode Data Register */
|
||||
#define CBS_COMDATA /*lint --e(923)*/ (*(volatile Ifx_CBS_COMDATA*)0xF0000468u)
|
||||
|
||||
/** \brief 88, Internally Controlled Trace Source Register */
|
||||
#define CBS_ICTSA /*lint --e(923)*/ (*(volatile Ifx_CBS_ICTSA*)0xF0000488u)
|
||||
|
||||
/** \brief 8C, Internally Controlled Trace Destination Register */
|
||||
#define CBS_ICTTA /*lint --e(923)*/ (*(volatile Ifx_CBS_ICTTA*)0xF000048Cu)
|
||||
|
||||
/** \brief 84, Internal Mode Status and Control Register */
|
||||
#define CBS_INTMOD /*lint --e(923)*/ (*(volatile Ifx_CBS_INTMOD*)0xF0000484u)
|
||||
|
||||
/** \brief 6C, IOClient Status and Control Register */
|
||||
#define CBS_IOSR /*lint --e(923)*/ (*(volatile Ifx_CBS_IOSR*)0xF000046Cu)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define CBS_JDPID /*lint --e(923)*/ (*(volatile Ifx_CBS_JDPID*)0xF0000408u)
|
||||
|
||||
/** \brief 64, JTAG Device Identification Register */
|
||||
#define CBS_JTAGID /*lint --e(923)*/ (*(volatile Ifx_CBS_JTAGID*)0xF0000464u)
|
||||
|
||||
/** \brief 7C, OSCU Control Register */
|
||||
#define CBS_OCNTRL /*lint --e(923)*/ (*(volatile Ifx_CBS_OCNTRL*)0xF000047Cu)
|
||||
|
||||
/** \brief 78, OCDS Enable Control Register */
|
||||
#define CBS_OEC /*lint --e(923)*/ (*(volatile Ifx_CBS_OEC*)0xF0000478u)
|
||||
|
||||
/** \brief C, OCDS Interface Mode Register */
|
||||
#define CBS_OIFM /*lint --e(923)*/ (*(volatile Ifx_CBS_OIFM*)0xF000040Cu)
|
||||
|
||||
/** \brief 80, OSCU Status Register */
|
||||
#define CBS_OSTATE /*lint --e(923)*/ (*(volatile Ifx_CBS_OSTATE*)0xF0000480u)
|
||||
|
||||
/** \brief B0, TG Capture for Cores - BRKOUT */
|
||||
#define CBS_TCCB /*lint --e(923)*/ (*(volatile Ifx_CBS_TCCB*)0xF00004B0u)
|
||||
|
||||
/** \brief B4, TG Capture for Cores - HALT */
|
||||
#define CBS_TCCH /*lint --e(923)*/ (*(volatile Ifx_CBS_TCCH*)0xF00004B4u)
|
||||
|
||||
/** \brief 1C, TG Capture for TG Input Pins */
|
||||
#define CBS_TCIP /*lint --e(923)*/ (*(volatile Ifx_CBS_TCIP*)0xF000041Cu)
|
||||
|
||||
/** \brief BC, TG Capture for MCDS */
|
||||
#define CBS_TCM /*lint --e(923)*/ (*(volatile Ifx_CBS_TCM*)0xF00004BCu)
|
||||
|
||||
/** \brief B8, TG Capture for OTGB0/1 */
|
||||
#define CBS_TCTGB /*lint --e(923)*/ (*(volatile Ifx_CBS_TCTGB*)0xF00004B8u)
|
||||
|
||||
/** \brief 74, TG Capture for TG Lines */
|
||||
#define CBS_TCTL /*lint --e(923)*/ (*(volatile Ifx_CBS_TCTL*)0xF0000474u)
|
||||
|
||||
/** \brief 10, TG Input Pins Routing */
|
||||
#define CBS_TIPR /*lint --e(923)*/ (*(volatile Ifx_CBS_TIPR*)0xF0000410u)
|
||||
|
||||
/** \brief 94, TG Line 1 Suspend Targets */
|
||||
#define CBS_TL1ST /*lint --e(923)*/ (*(volatile Ifx_CBS_TL1ST*)0xF0000494u)
|
||||
|
||||
/** \brief 90, TG Line Control */
|
||||
#define CBS_TLC /*lint --e(923)*/ (*(volatile Ifx_CBS_TLC*)0xF0000490u)
|
||||
|
||||
/** \brief 40, TG Line Counter Control */
|
||||
#define CBS_TLCC0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCC*)0xF0000440u)
|
||||
|
||||
/** \brief 44, TG Line Counter Control */
|
||||
#define CBS_TLCC1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCC*)0xF0000444u)
|
||||
|
||||
/** \brief 98, TG Line Capture and Hold Enable */
|
||||
#define CBS_TLCHE /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCHE*)0xF0000498u)
|
||||
|
||||
/** \brief 9C, TG Line Capture and Hold Clear */
|
||||
#define CBS_TLCHS /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCHS*)0xF000049Cu)
|
||||
|
||||
/** \brief 50, TG Line Counter Value */
|
||||
#define CBS_TLCV0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCV*)0xF0000450u)
|
||||
|
||||
/** \brief 54, TG Line Counter Value */
|
||||
#define CBS_TLCV1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TLCV*)0xF0000454u)
|
||||
|
||||
/** \brief 70, TG Line State */
|
||||
#define CBS_TLS /*lint --e(923)*/ (*(volatile Ifx_CBS_TLS*)0xF0000470u)
|
||||
|
||||
/** \brief A8, TG Line Timer */
|
||||
#define CBS_TLT /*lint --e(923)*/ (*(volatile Ifx_CBS_TLT*)0xF00004A8u)
|
||||
|
||||
/** \brief AC, TG Lines for Trigger to Host */
|
||||
#define CBS_TLTTH /*lint --e(923)*/ (*(volatile Ifx_CBS_TLTTH*)0xF00004ACu)
|
||||
|
||||
/** \brief 18, TG Output Pins Pulse Stretcher */
|
||||
#define CBS_TOPPS /*lint --e(923)*/ (*(volatile Ifx_CBS_TOPPS*)0xF0000418u)
|
||||
|
||||
/** \brief 14, TG Output Pins Routing */
|
||||
#define CBS_TOPR /*lint --e(923)*/ (*(volatile Ifx_CBS_TOPR*)0xF0000414u)
|
||||
|
||||
/** \brief 20, TG Routing for CPU */
|
||||
#define CBS_TRC0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRC*)0xF0000420u)
|
||||
|
||||
/** \brief 24, TG Routing for CPU */
|
||||
#define CBS_TRC1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRC*)0xF0000424u)
|
||||
|
||||
/** \brief C0, TG Routing Events of CPU */
|
||||
#define CBS_TREC0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TREC*)0xF00004C0u)
|
||||
|
||||
/** \brief C4, TG Routing Events of CPU */
|
||||
#define CBS_TREC1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TREC*)0xF00004C4u)
|
||||
|
||||
/** \brief 100, Trigger to Host Register */
|
||||
#define CBS_TRIG0 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000500u)
|
||||
|
||||
/** \brief 104, Trigger to Host Register */
|
||||
#define CBS_TRIG1 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000504u)
|
||||
|
||||
/** \brief 128, Trigger to Host Register */
|
||||
#define CBS_TRIG10 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000528u)
|
||||
|
||||
/** \brief 12C, Trigger to Host Register */
|
||||
#define CBS_TRIG11 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000052Cu)
|
||||
|
||||
/** \brief 130, Trigger to Host Register */
|
||||
#define CBS_TRIG12 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000530u)
|
||||
|
||||
/** \brief 134, Trigger to Host Register */
|
||||
#define CBS_TRIG13 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000534u)
|
||||
|
||||
/** \brief 138, Trigger to Host Register */
|
||||
#define CBS_TRIG14 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000538u)
|
||||
|
||||
/** \brief 13C, Trigger to Host Register */
|
||||
#define CBS_TRIG15 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000053Cu)
|
||||
|
||||
/** \brief 140, Trigger to Host Register */
|
||||
#define CBS_TRIG16 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000540u)
|
||||
|
||||
/** \brief 144, Trigger to Host Register */
|
||||
#define CBS_TRIG17 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000544u)
|
||||
|
||||
/** \brief 148, Trigger to Host Register */
|
||||
#define CBS_TRIG18 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000548u)
|
||||
|
||||
/** \brief 14C, Trigger to Host Register */
|
||||
#define CBS_TRIG19 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000054Cu)
|
||||
|
||||
/** \brief 108, Trigger to Host Register */
|
||||
#define CBS_TRIG2 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000508u)
|
||||
|
||||
/** \brief 150, Trigger to Host Register */
|
||||
#define CBS_TRIG20 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000550u)
|
||||
|
||||
/** \brief 154, Trigger to Host Register */
|
||||
#define CBS_TRIG21 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000554u)
|
||||
|
||||
/** \brief 10C, Trigger to Host Register */
|
||||
#define CBS_TRIG3 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000050Cu)
|
||||
|
||||
/** \brief 110, Trigger to Host Register */
|
||||
#define CBS_TRIG4 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000510u)
|
||||
|
||||
/** \brief 114, Trigger to Host Register */
|
||||
#define CBS_TRIG5 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000514u)
|
||||
|
||||
/** \brief 118, Trigger to Host Register */
|
||||
#define CBS_TRIG6 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000518u)
|
||||
|
||||
/** \brief 11C, Trigger to Host Register */
|
||||
#define CBS_TRIG7 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF000051Cu)
|
||||
|
||||
/** \brief 120, Trigger to Host Register */
|
||||
#define CBS_TRIG8 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000520u)
|
||||
|
||||
/** \brief 124, Trigger to Host Register */
|
||||
#define CBS_TRIG9 /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIG*)0xF0000524u)
|
||||
|
||||
/** \brief A4, Clear Trigger to Host Register */
|
||||
#define CBS_TRIGC /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIGC*)0xF00004A4u)
|
||||
|
||||
/** \brief A0, Set Trigger to Host Register */
|
||||
#define CBS_TRIGS /*lint --e(923)*/ (*(volatile Ifx_CBS_TRIGS*)0xF00004A0u)
|
||||
|
||||
/** \brief 3C, TG Routing for MCDS Control */
|
||||
#define CBS_TRMC /*lint --e(923)*/ (*(volatile Ifx_CBS_TRMC*)0xF000043Cu)
|
||||
|
||||
/** \brief DC, TG Routing for MCDS Triggers */
|
||||
#define CBS_TRMT /*lint --e(923)*/ (*(volatile Ifx_CBS_TRMT*)0xF00004DCu)
|
||||
|
||||
/** \brief 60, TG Routing for Special Signals */
|
||||
#define CBS_TRSS /*lint --e(923)*/ (*(volatile Ifx_CBS_TRSS*)0xF0000460u)
|
||||
|
||||
/** \brief E4, TG Routing for OTGB Bits [15:8] */
|
||||
#define CBS_TRTGB0_H /*lint --e(923)*/ (*(volatile Ifx_CBS_TRTGB_H*)0xF00004E4u)
|
||||
|
||||
/** Alias (User Manual Name) for CBS_TRTGB0_H.
|
||||
* To use register names with standard convension, please use CBS_TRTGB0_H.
|
||||
*/
|
||||
#define CBS_TRTGB0H (CBS_TRTGB0_H)
|
||||
|
||||
/** \brief E0, TG Routing for OTGB Bits [7:0] */
|
||||
#define CBS_TRTGB0_L /*lint --e(923)*/ (*(volatile Ifx_CBS_TRTGB_L*)0xF00004E0u)
|
||||
|
||||
/** Alias (User Manual Name) for CBS_TRTGB0_L.
|
||||
* To use register names with standard convension, please use CBS_TRTGB0_L.
|
||||
*/
|
||||
#define CBS_TRTGB0L (CBS_TRTGB0_L)
|
||||
|
||||
/** \brief EC, TG Routing for OTGB Bits [15:8] */
|
||||
#define CBS_TRTGB1_H /*lint --e(923)*/ (*(volatile Ifx_CBS_TRTGB_H*)0xF00004ECu)
|
||||
|
||||
/** Alias (User Manual Name) for CBS_TRTGB1_H.
|
||||
* To use register names with standard convension, please use CBS_TRTGB1_H.
|
||||
*/
|
||||
#define CBS_TRTGB1H (CBS_TRTGB1_H)
|
||||
|
||||
/** \brief E8, TG Routing for OTGB Bits [7:0] */
|
||||
#define CBS_TRTGB1_L /*lint --e(923)*/ (*(volatile Ifx_CBS_TRTGB_L*)0xF00004E8u)
|
||||
|
||||
/** Alias (User Manual Name) for CBS_TRTGB1_L.
|
||||
* To use register names with standard convension, please use CBS_TRTGB1_L.
|
||||
*/
|
||||
#define CBS_TRTGB1L (CBS_TRTGB1_L)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXCBS_REG_H */
|
||||
@@ -0,0 +1,957 @@
|
||||
/**
|
||||
* \file IfxCbs_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Cbs Cbs
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Cbs_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Cbs
|
||||
*
|
||||
* \defgroup IfxLld_Cbs_union Union
|
||||
* \ingroup IfxLld_Cbs
|
||||
*
|
||||
* \defgroup IfxLld_Cbs_struct Struct
|
||||
* \ingroup IfxLld_Cbs
|
||||
*
|
||||
*/
|
||||
#ifndef IFXCBS_REGDEF_H
|
||||
#define IFXCBS_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Cbs_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Communication Mode Data Register */
|
||||
typedef struct _Ifx_CBS_COMDATA_Bits
|
||||
{
|
||||
unsigned int DATA:32; /**< \brief [31:0] Read/Write Data (rw) */
|
||||
} Ifx_CBS_COMDATA_Bits;
|
||||
|
||||
/** \brief Internally Controlled Trace Source Register */
|
||||
typedef struct _Ifx_CBS_ICTSA_Bits
|
||||
{
|
||||
unsigned int ADDR:32; /**< \brief [31:0] Source Address (rw) */
|
||||
} Ifx_CBS_ICTSA_Bits;
|
||||
|
||||
/** \brief Internally Controlled Trace Destination Register */
|
||||
typedef struct _Ifx_CBS_ICTTA_Bits
|
||||
{
|
||||
unsigned int ADDR:32; /**< \brief [31:0] Destination Address (rw) */
|
||||
} Ifx_CBS_ICTTA_Bits;
|
||||
|
||||
/** \brief Internal Mode Status and Control Register */
|
||||
typedef struct _Ifx_CBS_INTMOD_Bits
|
||||
{
|
||||
unsigned int SET_CRS:1; /**< \brief [0:0] Set Read Sync Flag (w) */
|
||||
unsigned int SET_CWS:1; /**< \brief [1:1] Set Write Sync Flag (w) */
|
||||
unsigned int SET_CS:1; /**< \brief [2:2] Set Communication Synchronization Flag (w) */
|
||||
unsigned int CLR_CS:1; /**< \brief [3:3] Clear Communication Synchronization Flag (w) */
|
||||
unsigned int CHANNEL_P:1; /**< \brief [4:4] CHANNEL Write Protection (w) */
|
||||
unsigned int CHANNEL:3; /**< \brief [7:5] Channel Indication (rw) */
|
||||
unsigned int reserved_8:8; /**< \brief \internal Reserved */
|
||||
unsigned int SET_INT_MOD:1; /**< \brief [16:16] Enter Internal Mode (w) */
|
||||
unsigned int reserved_17:1; /**< \brief \internal Reserved */
|
||||
unsigned int SET_INT_TRC:1; /**< \brief [18:18] Enable Internally Controlled Triggered Transfer (w) */
|
||||
unsigned int CLR_INT_TRC:1; /**< \brief [19:19] Disable Internally Controlled Triggered Transfer (w) */
|
||||
unsigned int TRC_MOD_P:1; /**< \brief [20:20] TRC_MOD Write Protection (w) */
|
||||
unsigned int TRC_MOD:2; /**< \brief [22:21] Data Size Definition for Triggered Transfer (rw) */
|
||||
unsigned int reserved_23:1; /**< \brief \internal Reserved */
|
||||
unsigned int INT_MOD:1; /**< \brief [24:24] Internal Mode Enabled Flag (rh) */
|
||||
unsigned int INT_TRC:1; /**< \brief [25:25] Internally Controlled Triggered Transfer Enable (rh) */
|
||||
unsigned int reserved_26:6; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_INTMOD_Bits;
|
||||
|
||||
/** \brief IOClient Status and Control Register */
|
||||
typedef struct _Ifx_CBS_IOSR_Bits
|
||||
{
|
||||
unsigned int reserved_0:4; /**< \brief \internal Reserved */
|
||||
unsigned int CRSYNC:1; /**< \brief [4:4] Communication Mode Read Sync Flag (rh) */
|
||||
unsigned int CWSYNC:1; /**< \brief [5:5] Communication Mode Write Sync Flag (rh) */
|
||||
unsigned int CW_ACK:1; /**< \brief [6:6] Communication Mode Write Acknowledge (w) */
|
||||
unsigned int COM_SYNC:1; /**< \brief [7:7] Communication Mode Synchronization Flag (rh) */
|
||||
unsigned int HOSTED:1; /**< \brief [8:8] Tool Interface in Use (rh) */
|
||||
unsigned int reserved_9:3; /**< \brief \internal Reserved */
|
||||
unsigned int CHANNEL:3; /**< \brief [14:12] Channel Indication (rh) */
|
||||
unsigned int reserved_15:17; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_IOSR_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_CBS_JDPID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_CBS_JDPID_Bits;
|
||||
|
||||
/** \brief JTAG Device Identification Register */
|
||||
typedef struct _Ifx_CBS_JTAGID_Bits
|
||||
{
|
||||
unsigned int JTAG_ID:32; /**< \brief [31:0] JTAG Device ID (rw) */
|
||||
} Ifx_CBS_JTAGID_Bits;
|
||||
|
||||
/** \brief OSCU Control Register */
|
||||
typedef struct _Ifx_CBS_OCNTRL_Bits
|
||||
{
|
||||
unsigned int OC0_P:1; /**< \brief [0:0] OC0 Write Protection (w) */
|
||||
unsigned int OC0:1; /**< \brief [1:1] Set/Clear OCDS Control Bits Bus Domain (w) */
|
||||
unsigned int OC1_P:1; /**< \brief [2:2] OC1 Write Protection (w) */
|
||||
unsigned int OC1:1; /**< \brief [3:3] Set/Clear OCDS Control Bits Bus Domain (w) */
|
||||
unsigned int OC2_P:1; /**< \brief [4:4] OC2 Write Protection (w) */
|
||||
unsigned int OC2:1; /**< \brief [5:5] Set/Clear OCDS Control Bits Bus Domain (w) */
|
||||
unsigned int OC3_P:1; /**< \brief [6:6] OC3 Write Protection (w) */
|
||||
unsigned int OC3:1; /**< \brief [7:7] Set/Clear OCDS Control Bits Bus Domain (w) */
|
||||
unsigned int OC4_P:1; /**< \brief [8:8] OC4 Write Protection (w) */
|
||||
unsigned int OC4:1; /**< \brief [9:9] Set/Clear OCDS Control Bits Bus Domain (w) */
|
||||
unsigned int OC5_P:1; /**< \brief [10:10] OC5 Write Protection (w) */
|
||||
unsigned int OC5:1; /**< \brief [11:11] Set/Clear OCDS Control Bits Bus Domain (w) */
|
||||
unsigned int WDTSUS_P:1; /**< \brief [12:12] WDTSUS Write Protection (w) */
|
||||
unsigned int WDTSUS:1; /**< \brief [13:13] Set/Clear Watchdog Timer Suspension Control (w) */
|
||||
unsigned int STABLE_P:1; /**< \brief [14:14] STABLE Write Protection (w) */
|
||||
unsigned int STABLE:1; /**< \brief [15:15] Initialize Application Reset Indication (w) */
|
||||
unsigned int OJC0_P:1; /**< \brief [16:16] OJC0 Write Protection (w) */
|
||||
unsigned int OJC0:1; /**< \brief [17:17] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
unsigned int OJC1_P:1; /**< \brief [18:18] OJC1 Write Protection (w) */
|
||||
unsigned int OJC1:1; /**< \brief [19:19] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
unsigned int OJC2_P:1; /**< \brief [20:20] OJC2 Write Protection (w) */
|
||||
unsigned int OJC2:1; /**< \brief [21:21] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
unsigned int OJC3_P:1; /**< \brief [22:22] OJC3 Write Protection (w) */
|
||||
unsigned int OJC3:1; /**< \brief [23:23] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
unsigned int OJC4_P:1; /**< \brief [24:24] OJC4 Write Protection (w) */
|
||||
unsigned int OJC4:1; /**< \brief [25:25] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
unsigned int OJC5_P:1; /**< \brief [26:26] OJC5 Write Protection (w) */
|
||||
unsigned int OJC5:1; /**< \brief [27:27] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
unsigned int OJC6_P:1; /**< \brief [28:28] OJC6 Write Protection (w) */
|
||||
unsigned int OJC6:1; /**< \brief [29:29] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
unsigned int OJC7_P:1; /**< \brief [30:30] OJC7 Write Protection (w) */
|
||||
unsigned int OJC7:1; /**< \brief [31:31] Set/Clear OCDS Control Bits IOClient Domain (w) */
|
||||
} Ifx_CBS_OCNTRL_Bits;
|
||||
|
||||
/** \brief OCDS Enable Control Register */
|
||||
typedef struct _Ifx_CBS_OEC_Bits
|
||||
{
|
||||
unsigned int PAT:8; /**< \brief [7:0] OCDS Enabling Pattern (w) */
|
||||
unsigned int DS:1; /**< \brief [8:8] Disable OCDS (w) */
|
||||
unsigned int OCO:1; /**< \brief [9:9] OCDS Clock Off (w) */
|
||||
unsigned int reserved_10:6; /**< \brief \internal Reserved */
|
||||
unsigned int IF_LCK_P:1; /**< \brief [16:16] IF_LCK Write Protection (w) */
|
||||
unsigned int IF_LCK:1; /**< \brief [17:17] Set/Clear Interface Locked Indication (w) */
|
||||
unsigned int AUT_OK_P:1; /**< \brief [18:18] AUT_OK Write Protection (w) */
|
||||
unsigned int AUT_OK:1; /**< \brief [19:19] Set/Clear the Authorization OK Indication (w) */
|
||||
unsigned int reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_OEC_Bits;
|
||||
|
||||
/** \brief OCDS Interface Mode Register */
|
||||
typedef struct _Ifx_CBS_OIFM_Bits
|
||||
{
|
||||
unsigned int DAPMODE:3; /**< \brief [2:0] DAP Interface Mode (rw) */
|
||||
unsigned int DAPRST:1; /**< \brief [3:3] DAP Protocol Clear (rwh) */
|
||||
unsigned int reserved_4:4; /**< \brief \internal Reserved */
|
||||
unsigned int F_JTAG:1; /**< \brief [8:8] Forced JTAG Mode (rw) */
|
||||
unsigned int N_JTAG:1; /**< \brief [9:9] No Switch to JTAG (rw) */
|
||||
unsigned int reserved_10:2; /**< \brief \internal Reserved */
|
||||
unsigned int PADCTL:4; /**< \brief [15:12] Pad Control for Debug Interface Pins (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_OIFM_Bits;
|
||||
|
||||
/** \brief OSCU Status Register */
|
||||
typedef struct _Ifx_CBS_OSTATE_Bits
|
||||
{
|
||||
unsigned int OEN:1; /**< \brief [0:0] OCDS Enabled Flag (rh) */
|
||||
unsigned int OC0:1; /**< \brief [1:1] OCDS Control Bits System Bus Domain (rh) */
|
||||
unsigned int OC1:1; /**< \brief [2:2] OCDS Control Bits System Bus Domain (rh) */
|
||||
unsigned int OC2:1; /**< \brief [3:3] OCDS Control Bits System Bus Domain (rh) */
|
||||
unsigned int ENIDIS:1; /**< \brief [4:4] OCDS ENDINIT Protection Override (rh) */
|
||||
unsigned int EECTRC:1; /**< \brief [5:5] On Chip Trace Enable (rh) */
|
||||
unsigned int EECDIS:1; /**< \brief [6:6] Emulation Logic Disable (rh) */
|
||||
unsigned int WDTSUS:1; /**< \brief [7:7] Control of Watchdog Timer Suspension (rh) */
|
||||
unsigned int HARR:1; /**< \brief [8:8] Halt after Reset Request (rh) */
|
||||
unsigned int OJC1:1; /**< \brief [9:9] OCDS Control Bits IOClient Domain (rh) */
|
||||
unsigned int OJC2:1; /**< \brief [10:10] OCDS Control Bits IOClient Domain (rh) */
|
||||
unsigned int OJC3:1; /**< \brief [11:11] OCDS Control Bits IOClient Domain (rh) */
|
||||
unsigned int RSTCL0:1; /**< \brief [12:12] OCDS System Reset Request (rh) */
|
||||
unsigned int RSTCL1:1; /**< \brief [13:13] OCDS Debug Reset Request (rh) */
|
||||
unsigned int OJC6:1; /**< \brief [14:14] OCDS Control Bits IOClient Domain (rh) */
|
||||
unsigned int RSTCL3:1; /**< \brief [15:15] OCDS Application Reset Request (rh) */
|
||||
unsigned int IF_LCK:1; /**< \brief [16:16] Interface Locked Indication (rh) */
|
||||
unsigned int AUT_OK:1; /**< \brief [17:17] Authorization OK Indication (rh) */
|
||||
unsigned int STABLE:1; /**< \brief [18:18] Application Reset Indication (rh) */
|
||||
unsigned int OCO:1; /**< \brief [19:19] OCDS debug resource Clock On Indication (rh) */
|
||||
unsigned int reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_OSTATE_Bits;
|
||||
|
||||
/** \brief TG Capture for Cores - BRKOUT */
|
||||
typedef struct _Ifx_CBS_TCCB_Bits
|
||||
{
|
||||
unsigned int C0:1; /**< \brief [0:0] Capture of BRKOUT Signal of CPU0 (rh) */
|
||||
unsigned int C1:1; /**< \brief [1:1] Capture of BRKOUT Signal of CPU1 (rh) */
|
||||
unsigned int C2:1; /**< \brief [2:2] Capture of BRKOUT Signal of CPU2 (rh) */
|
||||
unsigned int reserved_3:28; /**< \brief \internal Reserved */
|
||||
unsigned int HSM:1; /**< \brief [31:31] Capture of BRKOUT Signal of (rh) */
|
||||
} Ifx_CBS_TCCB_Bits;
|
||||
|
||||
/** \brief TG Capture for Cores - HALT */
|
||||
typedef struct _Ifx_CBS_TCCH_Bits
|
||||
{
|
||||
unsigned int C0:1; /**< \brief [0:0] Capture of HALT Signal of CPU0 (rh) */
|
||||
unsigned int C1:1; /**< \brief [1:1] Capture of HALT Signal of CPU1 (rh) */
|
||||
unsigned int C2:1; /**< \brief [2:2] Capture of HALT Signal of CPU2 (rh) */
|
||||
unsigned int reserved_3:28; /**< \brief \internal Reserved */
|
||||
unsigned int HSM:1; /**< \brief [31:31] Capture of HALT Signal of (rh) */
|
||||
} Ifx_CBS_TCCH_Bits;
|
||||
|
||||
/** \brief TG Capture for TG Input Pins */
|
||||
typedef struct _Ifx_CBS_TCIP_Bits
|
||||
{
|
||||
unsigned int P0:1; /**< \brief [0:0] Capture of Trigger Input Pin 0 (rh) */
|
||||
unsigned int P1:1; /**< \brief [1:1] Capture of Trigger Input Pin 1 (rh) */
|
||||
unsigned int P2:1; /**< \brief [2:2] Capture of Trigger Input Pin 2 (rh) */
|
||||
unsigned int P3:1; /**< \brief [3:3] Capture of Trigger Input Pin 3 (rh) */
|
||||
unsigned int P4:1; /**< \brief [4:4] Capture of Trigger Input Pin 4 (rh) */
|
||||
unsigned int P5:1; /**< \brief [5:5] Capture of Trigger Input Pin 5 (rh) */
|
||||
unsigned int P6:1; /**< \brief [6:6] Capture of Trigger Input Pin 6 (rh) */
|
||||
unsigned int P7:1; /**< \brief [7:7] Capture of Trigger Input Pin 7 (rh) */
|
||||
unsigned int reserved_8:24; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TCIP_Bits;
|
||||
|
||||
/** \brief TG Capture for MCDS */
|
||||
typedef struct _Ifx_CBS_TCM_Bits
|
||||
{
|
||||
unsigned int BRK:1; /**< \brief [0:0] Capture of MCDS break_out (rh) */
|
||||
unsigned int SUS:1; /**< \brief [1:1] Capture of MCDS suspend_out (rh) */
|
||||
unsigned int reserved_2:6; /**< \brief \internal Reserved */
|
||||
unsigned int T0:1; /**< \brief [8:8] Capture of MCDS trig_out 0 (rh) */
|
||||
unsigned int T1:1; /**< \brief [9:9] Capture of MCDS trig_out 1 (rh) */
|
||||
unsigned int T2:1; /**< \brief [10:10] Capture of MCDS trig_out 2 (rh) */
|
||||
unsigned int T3:1; /**< \brief [11:11] Capture of MCDS trig_out 3 (rh) */
|
||||
unsigned int reserved_12:20; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TCM_Bits;
|
||||
|
||||
/** \brief TG Capture for OTGB0/1 */
|
||||
typedef struct _Ifx_CBS_TCTGB_Bits
|
||||
{
|
||||
unsigned int OTGB0:16; /**< \brief [15:0] Capture Bits for OTGB0 (rh) */
|
||||
unsigned int OTGB1:16; /**< \brief [31:16] Capture Bits for OTGB1 (rh) */
|
||||
} Ifx_CBS_TCTGB_Bits;
|
||||
|
||||
/** \brief TG Capture for TG Lines */
|
||||
typedef struct _Ifx_CBS_TCTL_Bits
|
||||
{
|
||||
unsigned int reserved_0:1; /**< \brief \internal Reserved */
|
||||
unsigned int TL1:1; /**< \brief [1:1] Capture of Trigger Line 1 (rh) */
|
||||
unsigned int TL2:1; /**< \brief [2:2] Capture of Trigger Line 2 (rh) */
|
||||
unsigned int TL3:1; /**< \brief [3:3] Capture of Trigger Line 3 (rh) */
|
||||
unsigned int TL4:1; /**< \brief [4:4] Capture of Trigger Line 4 (rh) */
|
||||
unsigned int TL5:1; /**< \brief [5:5] Capture of Trigger Line 5 (rh) */
|
||||
unsigned int TL6:1; /**< \brief [6:6] Capture of Trigger Line 6 (rh) */
|
||||
unsigned int TL7:1; /**< \brief [7:7] Capture of Trigger Line 7 (rh) */
|
||||
unsigned int reserved_8:24; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TCTL_Bits;
|
||||
|
||||
/** \brief TG Input Pins Routing */
|
||||
typedef struct _Ifx_CBS_TIPR_Bits
|
||||
{
|
||||
unsigned int PIN0:4; /**< \brief [3:0] Trigger Pin 0 to Trigger Line Routing (rw) */
|
||||
unsigned int PIN1:4; /**< \brief [7:4] Trigger Pin 1 to Trigger Line Routing (rw) */
|
||||
unsigned int PIN2:4; /**< \brief [11:8] Trigger Pin 2 to Trigger Line Routing (rw) */
|
||||
unsigned int PIN3:4; /**< \brief [15:12] Trigger Pin 3 to Trigger Line Routing (rw) */
|
||||
unsigned int PIN4:4; /**< \brief [19:16] Trigger Pin 4 to Trigger Line Routing (rw) */
|
||||
unsigned int PIN5:4; /**< \brief [23:20] Trigger Pin 5 to Trigger Line Routing (rw) */
|
||||
unsigned int PIN6:4; /**< \brief [27:24] Trigger Pin 6 to Trigger Line Routing (rw) */
|
||||
unsigned int PIN7:4; /**< \brief [31:28] Trigger Pin 7 to Trigger Line Routing (rw) */
|
||||
} Ifx_CBS_TIPR_Bits;
|
||||
|
||||
/** \brief TG Line 1 Suspend Targets */
|
||||
typedef struct _Ifx_CBS_TL1ST_Bits
|
||||
{
|
||||
unsigned int C0:1; /**< \brief [0:0] CPU0 as Suspend Target (rw) */
|
||||
unsigned int C1:1; /**< \brief [1:1] CPU1 as Suspend Target (rw) */
|
||||
unsigned int C2:1; /**< \brief [2:2] CPU2 as Suspend Target (rw) */
|
||||
unsigned int reserved_3:25; /**< \brief \internal Reserved */
|
||||
unsigned int HSS:1; /**< \brief [28:28] HSSL as Suspend Target (rw) */
|
||||
unsigned int DMA:1; /**< \brief [29:29] DMA as Suspend Target (rw) */
|
||||
unsigned int reserved_30:1; /**< \brief \internal Reserved */
|
||||
unsigned int HSM:1; /**< \brief [31:31] as Suspend Target (rw) */
|
||||
} Ifx_CBS_TL1ST_Bits;
|
||||
|
||||
/** \brief TG Line Control */
|
||||
typedef struct _Ifx_CBS_TLC_Bits
|
||||
{
|
||||
unsigned int reserved_0:4; /**< \brief \internal Reserved */
|
||||
unsigned int TLSP1:4; /**< \brief [7:4] TG Line Signal Processing (rw) */
|
||||
unsigned int TLSP2:4; /**< \brief [11:8] TG Line Signal Processing (rw) */
|
||||
unsigned int TLSP3:4; /**< \brief [15:12] TG Line Signal Processing (rw) */
|
||||
unsigned int TLSP4:4; /**< \brief [19:16] TG Line Signal Processing (rw) */
|
||||
unsigned int TLSP5:4; /**< \brief [23:20] TG Line Signal Processing (rw) */
|
||||
unsigned int TLSP6:4; /**< \brief [27:24] TG Line Signal Processing (rw) */
|
||||
unsigned int TLSP7:4; /**< \brief [31:28] TG Line Signal Processing (rw) */
|
||||
} Ifx_CBS_TLC_Bits;
|
||||
|
||||
/** \brief TG Line Counter Control */
|
||||
typedef struct _Ifx_CBS_TLCC_Bits
|
||||
{
|
||||
unsigned int TGL:4; /**< \brief [3:0] Trigger Line to Counter Routing (rw) */
|
||||
unsigned int LE:3; /**< \brief [6:4] Level or Edge Counting (rw) */
|
||||
unsigned int reserved_7:1; /**< \brief \internal Reserved */
|
||||
unsigned int CLR:2; /**< \brief [9:8] Clear and Enable Counter(s) (w) */
|
||||
unsigned int reserved_10:2; /**< \brief \internal Reserved */
|
||||
unsigned int STOP:2; /**< \brief [13:12] Stop Counter(s) (w) */
|
||||
unsigned int reserved_14:18; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TLCC_Bits;
|
||||
|
||||
/** \brief TG Line Capture and Hold Enable */
|
||||
typedef struct _Ifx_CBS_TLCHE_Bits
|
||||
{
|
||||
unsigned int reserved_0:1; /**< \brief \internal Reserved */
|
||||
unsigned int TL1:1; /**< \brief [1:1] Capture and Hold Enable for Trigger Line 1 (rw) */
|
||||
unsigned int TL2:1; /**< \brief [2:2] Capture and Hold Enable for Trigger Line 2 (rw) */
|
||||
unsigned int TL3:1; /**< \brief [3:3] Capture and Hold Enable for Trigger Line 3 (rw) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TLCHE_Bits;
|
||||
|
||||
/** \brief TG Line Capture and Hold Clear */
|
||||
typedef struct _Ifx_CBS_TLCHS_Bits
|
||||
{
|
||||
unsigned int reserved_0:1; /**< \brief \internal Reserved */
|
||||
unsigned int TL1:1; /**< \brief [1:1] Capture and Hold Clear for Trigger Line 1 (w) */
|
||||
unsigned int TL2:1; /**< \brief [2:2] Capture and Hold Clear for Trigger Line 2 (w) */
|
||||
unsigned int TL3:1; /**< \brief [3:3] Capture and Hold Clear for Trigger Line 3 (w) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TLCHS_Bits;
|
||||
|
||||
/** \brief TG Line Counter Value */
|
||||
typedef struct _Ifx_CBS_TLCV_Bits
|
||||
{
|
||||
unsigned int CV:31; /**< \brief [30:0] Count Value (rh) */
|
||||
unsigned int SO:1; /**< \brief [31:31] Sticky Overflow Bit (rh) */
|
||||
} Ifx_CBS_TLCV_Bits;
|
||||
|
||||
/** \brief TG Line State */
|
||||
typedef struct _Ifx_CBS_TLS_Bits
|
||||
{
|
||||
unsigned int reserved_0:1; /**< \brief \internal Reserved */
|
||||
unsigned int TL1:1; /**< \brief [1:1] Current State of Trigger Line 1 (rh) */
|
||||
unsigned int TL2:1; /**< \brief [2:2] Current State of Trigger Line 2 (rh) */
|
||||
unsigned int TL3:1; /**< \brief [3:3] Current State of Trigger Line 3 (rh) */
|
||||
unsigned int TL4:1; /**< \brief [4:4] Current State of Trigger Line 4 (rh) */
|
||||
unsigned int TL5:1; /**< \brief [5:5] Current State of Trigger Line 5 (rh) */
|
||||
unsigned int TL6:1; /**< \brief [6:6] Current State of Trigger Line 6 (rh) */
|
||||
unsigned int TL7:1; /**< \brief [7:7] Current State of Trigger Line 7 (rh) */
|
||||
unsigned int reserved_8:24; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TLS_Bits;
|
||||
|
||||
/** \brief TG Line Timer */
|
||||
typedef struct _Ifx_CBS_TLT_Bits
|
||||
{
|
||||
unsigned int TGL:4; /**< \brief [3:0] Timer to Trigger Line Routing (rw) */
|
||||
unsigned int VTZ:1; /**< \brief [4:4] TG Line Value when Timer Value is Zero (rw) */
|
||||
unsigned int reserved_5:11; /**< \brief \internal Reserved */
|
||||
unsigned int TIM:16; /**< \brief [31:16] Timer Value (rwh) */
|
||||
} Ifx_CBS_TLT_Bits;
|
||||
|
||||
/** \brief TG Lines for Trigger to Host */
|
||||
typedef struct _Ifx_CBS_TLTTH_Bits
|
||||
{
|
||||
unsigned int reserved_0:2; /**< \brief \internal Reserved */
|
||||
unsigned int TL1:2; /**< \brief [3:2] TG Line Enabling for Trigger to Host (TRIG) (rw) */
|
||||
unsigned int TL2:2; /**< \brief [5:4] TG Line Enabling for Trigger to Host (TRIG) (rw) */
|
||||
unsigned int TL3:2; /**< \brief [7:6] TG Line Enabling for Trigger to Host (TRIG) (rw) */
|
||||
unsigned int TL4:2; /**< \brief [9:8] TG Line Enabling for Trigger to Host (TRIG) (rw) */
|
||||
unsigned int TL5:2; /**< \brief [11:10] TG Line Enabling for Trigger to Host (TRIG) (rw) */
|
||||
unsigned int TL6:2; /**< \brief [13:12] TG Line Enabling for Trigger to Host (TRIG) (rw) */
|
||||
unsigned int TL7:2; /**< \brief [15:14] TG Line Enabling for Trigger to Host (TRIG) (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TLTTH_Bits;
|
||||
|
||||
/** \brief TG Output Pins Pulse Stretcher */
|
||||
typedef struct _Ifx_CBS_TOPPS_Bits
|
||||
{
|
||||
unsigned int PIN0:2; /**< \brief [1:0] Pulse Stretch Control for Trigger Pin 0 (rw) */
|
||||
unsigned int PIN1:2; /**< \brief [3:2] Pulse Stretch Control for Trigger Pin 1 (rw) */
|
||||
unsigned int PIN2:2; /**< \brief [5:4] Pulse Stretch Control for Trigger Pin 2 (rw) */
|
||||
unsigned int PIN3:2; /**< \brief [7:6] Pulse Stretch Control for Trigger Pin 3 (rw) */
|
||||
unsigned int PIN4:2; /**< \brief [9:8] Pulse Stretch Control for Trigger Pin 4 (rw) */
|
||||
unsigned int PIN5:2; /**< \brief [11:10] Pulse Stretch Control for Trigger Pin 5 (rw) */
|
||||
unsigned int PIN6:2; /**< \brief [13:12] Pulse Stretch Control for Trigger Pin 6 (rw) */
|
||||
unsigned int PIN7:2; /**< \brief [15:14] Pulse Stretch Control for Trigger Pin 7 (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TOPPS_Bits;
|
||||
|
||||
/** \brief TG Output Pins Routing */
|
||||
typedef struct _Ifx_CBS_TOPR_Bits
|
||||
{
|
||||
unsigned int PIN0:4; /**< \brief [3:0] Trigger Line to Trigger Pin 0 Routing (rw) */
|
||||
unsigned int PIN1:4; /**< \brief [7:4] Trigger Line to Trigger Pin 1 Routing (rw) */
|
||||
unsigned int PIN2:4; /**< \brief [11:8] Trigger Line to Trigger Pin 2 Routing (rw) */
|
||||
unsigned int PIN3:4; /**< \brief [15:12] Trigger Line to Trigger Pin 3 Routing (rw) */
|
||||
unsigned int PIN4:4; /**< \brief [19:16] Trigger Line to Trigger Pin 4 Routing (rw) */
|
||||
unsigned int PIN5:4; /**< \brief [23:20] Trigger Line to Trigger Pin 5 Routing (rw) */
|
||||
unsigned int PIN6:4; /**< \brief [27:24] Trigger Line to Trigger Pin 6 Routing (rw) */
|
||||
unsigned int PIN7:4; /**< \brief [31:28] Trigger Line to Trigger Pin 7 Routing (rw) */
|
||||
} Ifx_CBS_TOPR_Bits;
|
||||
|
||||
/** \brief TG Routing for CPU */
|
||||
typedef struct _Ifx_CBS_TRC_Bits
|
||||
{
|
||||
unsigned int HALT:4; /**< \brief [3:0] HALT to Trigger Line Routing (rw) */
|
||||
unsigned int BRKOUT:4; /**< \brief [7:4] BRKOUT to Trigger Line Routing (rw) */
|
||||
unsigned int BT1:1; /**< \brief [8:8] BRKOUT to Trigger Line 1 Routing (rw) */
|
||||
unsigned int reserved_9:11; /**< \brief \internal Reserved */
|
||||
unsigned int BRKIN:4; /**< \brief [23:20] Trigger Line to BRKIN Routing (rw) */
|
||||
unsigned int SUSIN:4; /**< \brief [27:24] Trigger Line to SUSIN Routing (rw) */
|
||||
unsigned int reserved_28:4; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TRC_Bits;
|
||||
|
||||
/** \brief TG Routing Events of CPU */
|
||||
typedef struct _Ifx_CBS_TREC_Bits
|
||||
{
|
||||
unsigned int TR0EV:4; /**< \brief [3:0] TRxEVT to Trigger Line Routing (rw) */
|
||||
unsigned int reserved_4:4; /**< \brief \internal Reserved */
|
||||
unsigned int TR2EV:4; /**< \brief [11:8] TRxEVT to Trigger Line Routing (rw) */
|
||||
unsigned int reserved_12:4; /**< \brief \internal Reserved */
|
||||
unsigned int TR4EV:4; /**< \brief [19:16] TRxEVT to Trigger Line Routing (rw) */
|
||||
unsigned int reserved_20:4; /**< \brief \internal Reserved */
|
||||
unsigned int TR6EV:4; /**< \brief [27:24] TRxEVT to Trigger Line Routing (rw) */
|
||||
unsigned int reserved_28:4; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TREC_Bits;
|
||||
|
||||
/** \brief Trigger to Host Register */
|
||||
typedef struct _Ifx_CBS_TRIG_Bits
|
||||
{
|
||||
unsigned int TRGx_0:1; /**< \brief [0:0] Service Request Bits (rh) */
|
||||
unsigned int TRGx_1:1; /**< \brief [1:1] Service Request Bits (rh) */
|
||||
unsigned int TRGx_2:1; /**< \brief [2:2] Service Request Bits (rh) */
|
||||
unsigned int TRGx_3:1; /**< \brief [3:3] Service Request Bits (rh) */
|
||||
unsigned int TRGx_4:1; /**< \brief [4:4] Service Request Bits (rh) */
|
||||
unsigned int TRGx_5:1; /**< \brief [5:5] Service Request Bits (rh) */
|
||||
unsigned int TRGx_6:1; /**< \brief [6:6] Service Request Bits (rh) */
|
||||
unsigned int TRGx_7:1; /**< \brief [7:7] Service Request Bits (rh) */
|
||||
unsigned int TRGx_8:1; /**< \brief [8:8] Service Request Bits (rh) */
|
||||
unsigned int TRGx_9:1; /**< \brief [9:9] Service Request Bits (rh) */
|
||||
unsigned int TRGx_10:1; /**< \brief [10:10] Service Request Bits (rh) */
|
||||
unsigned int TRGx_11:1; /**< \brief [11:11] Service Request Bits (rh) */
|
||||
unsigned int TRGx_12:1; /**< \brief [12:12] Service Request Bits (rh) */
|
||||
unsigned int TRGx_13:1; /**< \brief [13:13] Service Request Bits (rh) */
|
||||
unsigned int TRGx_14:1; /**< \brief [14:14] Service Request Bits (rh) */
|
||||
unsigned int TRGx_15:1; /**< \brief [15:15] Service Request Bits (rh) */
|
||||
unsigned int TRGx_16:1; /**< \brief [16:16] Service Request Bits (rh) */
|
||||
unsigned int TRGx_17:1; /**< \brief [17:17] Service Request Bits (rh) */
|
||||
unsigned int TRGx_18:1; /**< \brief [18:18] Service Request Bits (rh) */
|
||||
unsigned int TRGx_19:1; /**< \brief [19:19] Service Request Bits (rh) */
|
||||
unsigned int TRGx_20:1; /**< \brief [20:20] Service Request Bits (rh) */
|
||||
unsigned int TRGx_21:1; /**< \brief [21:21] Service Request Bits (rh) */
|
||||
unsigned int TRGx_22:1; /**< \brief [22:22] Service Request Bits (rh) */
|
||||
unsigned int TRGx_23:1; /**< \brief [23:23] Service Request Bits (rh) */
|
||||
unsigned int x:8; /**< \brief [31:24] TRIG register number (rh) */
|
||||
} Ifx_CBS_TRIG_Bits;
|
||||
|
||||
/** \brief Clear Trigger to Host Register */
|
||||
typedef struct _Ifx_CBS_TRIGC_Bits
|
||||
{
|
||||
unsigned int TRGx_0:1; /**< \brief [0:0] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_1:1; /**< \brief [1:1] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_2:1; /**< \brief [2:2] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_3:1; /**< \brief [3:3] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_4:1; /**< \brief [4:4] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_5:1; /**< \brief [5:5] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_6:1; /**< \brief [6:6] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_7:1; /**< \brief [7:7] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_8:1; /**< \brief [8:8] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_9:1; /**< \brief [9:9] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_10:1; /**< \brief [10:10] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_11:1; /**< \brief [11:11] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_12:1; /**< \brief [12:12] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_13:1; /**< \brief [13:13] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_14:1; /**< \brief [14:14] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_15:1; /**< \brief [15:15] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_16:1; /**< \brief [16:16] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_17:1; /**< \brief [17:17] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_18:1; /**< \brief [18:18] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_19:1; /**< \brief [19:19] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_20:1; /**< \brief [20:20] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_21:1; /**< \brief [21:21] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_22:1; /**< \brief [22:22] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int TRGx_23:1; /**< \brief [23:23] Request Bits of most important register TRIGx (rh) */
|
||||
unsigned int x:8; /**< \brief [31:24] Index of most important register TRIGx (rh) */
|
||||
} Ifx_CBS_TRIGC_Bits;
|
||||
|
||||
/** \brief Set Trigger to Host Register */
|
||||
typedef struct _Ifx_CBS_TRIGS_Bits
|
||||
{
|
||||
unsigned int BITNUM:13; /**< \brief [12:0] Service Request Bit Number to Set (w) */
|
||||
unsigned int reserved_13:19; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TRIGS_Bits;
|
||||
|
||||
/** \brief TG Routing for MCDS Control */
|
||||
typedef struct _Ifx_CBS_TRMC_Bits
|
||||
{
|
||||
unsigned int reserved_0:4; /**< \brief \internal Reserved */
|
||||
unsigned int BRKOUT:4; /**< \brief [7:4] MCDS break_out to Trigger Line Routing (rw) */
|
||||
unsigned int SUSOUT:4; /**< \brief [11:8] MCDS suspend_out to Trigger Line Routing (rw) */
|
||||
unsigned int reserved_12:8; /**< \brief \internal Reserved */
|
||||
unsigned int BRKIN:4; /**< \brief [23:20] Trigger Line to MCDS break_in Routing (rw) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TRMC_Bits;
|
||||
|
||||
/** \brief TG Routing for MCDS Triggers */
|
||||
typedef struct _Ifx_CBS_TRMT_Bits
|
||||
{
|
||||
unsigned int TG0:4; /**< \brief [3:0] MCDS trig_out 0 to Trigger Line Routing (rw) */
|
||||
unsigned int TG1:4; /**< \brief [7:4] MCDS trig_out 1 to Trigger Line Routing (rw) */
|
||||
unsigned int TG2:4; /**< \brief [11:8] MCDS trig_out 2 to Trigger Line Routing (rw) */
|
||||
unsigned int TG3:4; /**< \brief [15:12] MCDS trig_out 3 to Trigger Line Routing (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TRMT_Bits;
|
||||
|
||||
/** \brief TG Routing for Special Signals */
|
||||
typedef struct _Ifx_CBS_TRSS_Bits
|
||||
{
|
||||
unsigned int TT:4; /**< \brief [3:0] Trigger Line to Cerberus’ Triggered Transfer Routing (rw) */
|
||||
unsigned int reserved_4:12; /**< \brief \internal Reserved */
|
||||
unsigned int SRC0:4; /**< \brief [19:16] Trigger Line to SRC0 Interrupt Routing (rw) */
|
||||
unsigned int SRC1:4; /**< \brief [23:20] Trigger Line to SRC1 Interrupt Routing (rw) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_CBS_TRSS_Bits;
|
||||
|
||||
/** \brief TG Routing for OTGB Bits [15:8] */
|
||||
typedef struct _Ifx_CBS_TRTGB_H_Bits
|
||||
{
|
||||
unsigned int TG8:4; /**< \brief [3:0] (rw) */
|
||||
unsigned int TG9:4; /**< \brief [7:4] (rw) */
|
||||
unsigned int TG10:4; /**< \brief [11:8] (rw) */
|
||||
unsigned int TG11:4; /**< \brief [15:12] (rw) */
|
||||
unsigned int TG12:4; /**< \brief [19:16] (rw) */
|
||||
unsigned int TG13:4; /**< \brief [23:20] (rw) */
|
||||
unsigned int TG14:4; /**< \brief [27:24] (rw) */
|
||||
unsigned int TG15:4; /**< \brief [31:28] (rw) */
|
||||
} Ifx_CBS_TRTGB_H_Bits;
|
||||
|
||||
/** \brief TG Routing for OTGB Bits [7:0] */
|
||||
typedef struct _Ifx_CBS_TRTGB_L_Bits
|
||||
{
|
||||
unsigned int TG0:4; /**< \brief [3:0] (rw) */
|
||||
unsigned int TG1:4; /**< \brief [7:4] (rw) */
|
||||
unsigned int TG2:4; /**< \brief [11:8] (rw) */
|
||||
unsigned int TG3:4; /**< \brief [15:12] (rw) */
|
||||
unsigned int TG4:4; /**< \brief [19:16] (rw) */
|
||||
unsigned int TG5:4; /**< \brief [23:20] (rw) */
|
||||
unsigned int TG6:4; /**< \brief [27:24] (rw) */
|
||||
unsigned int TG7:4; /**< \brief [31:28] (rw) */
|
||||
} Ifx_CBS_TRTGB_L_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Cbs_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Communication Mode Data Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_COMDATA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_COMDATA;
|
||||
|
||||
/** \brief Internally Controlled Trace Source Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_ICTSA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_ICTSA;
|
||||
|
||||
/** \brief Internally Controlled Trace Destination Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_ICTTA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_ICTTA;
|
||||
|
||||
/** \brief Internal Mode Status and Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_INTMOD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_INTMOD;
|
||||
|
||||
/** \brief IOClient Status and Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_IOSR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_IOSR;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_JDPID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_JDPID;
|
||||
|
||||
/** \brief JTAG Device Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_JTAGID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_JTAGID;
|
||||
|
||||
/** \brief OSCU Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_OCNTRL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_OCNTRL;
|
||||
|
||||
/** \brief OCDS Enable Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_OEC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_OEC;
|
||||
|
||||
/** \brief OCDS Interface Mode Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_OIFM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_OIFM;
|
||||
|
||||
/** \brief OSCU Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_OSTATE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_OSTATE;
|
||||
|
||||
/** \brief TG Capture for Cores - BRKOUT */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TCCB_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TCCB;
|
||||
|
||||
/** \brief TG Capture for Cores - HALT */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TCCH_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TCCH;
|
||||
|
||||
/** \brief TG Capture for TG Input Pins */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TCIP_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TCIP;
|
||||
|
||||
/** \brief TG Capture for MCDS */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TCM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TCM;
|
||||
|
||||
/** \brief TG Capture for OTGB0/1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TCTGB_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TCTGB;
|
||||
|
||||
/** \brief TG Capture for TG Lines */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TCTL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TCTL;
|
||||
|
||||
/** \brief TG Input Pins Routing */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TIPR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TIPR;
|
||||
|
||||
/** \brief TG Line 1 Suspend Targets */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TL1ST_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TL1ST;
|
||||
|
||||
/** \brief TG Line Control */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLC;
|
||||
|
||||
/** \brief TG Line Counter Control */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLCC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLCC;
|
||||
|
||||
/** \brief TG Line Capture and Hold Enable */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLCHE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLCHE;
|
||||
|
||||
/** \brief TG Line Capture and Hold Clear */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLCHS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLCHS;
|
||||
|
||||
/** \brief TG Line Counter Value */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLCV_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLCV;
|
||||
|
||||
/** \brief TG Line State */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLS;
|
||||
|
||||
/** \brief TG Line Timer */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLT;
|
||||
|
||||
/** \brief TG Lines for Trigger to Host */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TLTTH_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TLTTH;
|
||||
|
||||
/** \brief TG Output Pins Pulse Stretcher */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TOPPS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TOPPS;
|
||||
|
||||
/** \brief TG Output Pins Routing */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TOPR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TOPR;
|
||||
|
||||
/** \brief TG Routing for CPU */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRC;
|
||||
|
||||
/** \brief TG Routing Events of CPU */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TREC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TREC;
|
||||
|
||||
/** \brief Trigger to Host Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRIG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRIG;
|
||||
|
||||
/** \brief Clear Trigger to Host Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRIGC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRIGC;
|
||||
|
||||
/** \brief Set Trigger to Host Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRIGS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRIGS;
|
||||
|
||||
/** \brief TG Routing for MCDS Control */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRMC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRMC;
|
||||
|
||||
/** \brief TG Routing for MCDS Triggers */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRMT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRMT;
|
||||
|
||||
/** \brief TG Routing for Special Signals */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRSS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRSS;
|
||||
|
||||
/** \brief TG Routing for OTGB Bits [15:8] */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRTGB_H_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRTGB_H;
|
||||
|
||||
/** \brief TG Routing for OTGB Bits [7:0] */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_CBS_TRTGB_L_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_CBS_TRTGB_L;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Cbs_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L1
|
||||
* \{ */
|
||||
|
||||
/** \brief TG Routing for OTGB */
|
||||
typedef volatile struct _Ifx_CBS_TRTGB
|
||||
{
|
||||
Ifx_CBS_TRTGB_L L; /**< \brief 0, TG Routing for OTGB Bits [7:0] */
|
||||
Ifx_CBS_TRTGB_H H; /**< \brief 4, TG Routing for OTGB Bits [15:8] */
|
||||
} Ifx_CBS_TRTGB;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Cbs_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief CBS object */
|
||||
typedef volatile struct _Ifx_CBS
|
||||
{
|
||||
unsigned char reserved_0[8]; /**< \brief 0, \internal Reserved */
|
||||
Ifx_CBS_JDPID JDPID; /**< \brief 8, Module Identification Register */
|
||||
Ifx_CBS_OIFM OIFM; /**< \brief C, OCDS Interface Mode Register */
|
||||
Ifx_CBS_TIPR TIPR; /**< \brief 10, TG Input Pins Routing */
|
||||
Ifx_CBS_TOPR TOPR; /**< \brief 14, TG Output Pins Routing */
|
||||
Ifx_CBS_TOPPS TOPPS; /**< \brief 18, TG Output Pins Pulse Stretcher */
|
||||
Ifx_CBS_TCIP TCIP; /**< \brief 1C, TG Capture for TG Input Pins */
|
||||
Ifx_CBS_TRC TRC[2]; /**< \brief 20, TG Routing for CPU */
|
||||
unsigned char reserved_28[20]; /**< \brief 28, \internal Reserved */
|
||||
Ifx_CBS_TRMC TRMC; /**< \brief 3C, TG Routing for MCDS Control */
|
||||
Ifx_CBS_TLCC TLCC[2]; /**< \brief 40, TG Line Counter Control */
|
||||
unsigned char reserved_48[8]; /**< \brief 48, \internal Reserved */
|
||||
Ifx_CBS_TLCV TLCV[2]; /**< \brief 50, TG Line Counter Value */
|
||||
unsigned char reserved_58[8]; /**< \brief 58, \internal Reserved */
|
||||
Ifx_CBS_TRSS TRSS; /**< \brief 60, TG Routing for Special Signals */
|
||||
Ifx_CBS_JTAGID JTAGID; /**< \brief 64, JTAG Device Identification Register */
|
||||
Ifx_CBS_COMDATA COMDATA; /**< \brief 68, Communication Mode Data Register */
|
||||
Ifx_CBS_IOSR IOSR; /**< \brief 6C, IOClient Status and Control Register */
|
||||
Ifx_CBS_TLS TLS; /**< \brief 70, TG Line State */
|
||||
Ifx_CBS_TCTL TCTL; /**< \brief 74, TG Capture for TG Lines */
|
||||
Ifx_CBS_OEC OEC; /**< \brief 78, OCDS Enable Control Register */
|
||||
Ifx_CBS_OCNTRL OCNTRL; /**< \brief 7C, OSCU Control Register */
|
||||
Ifx_CBS_OSTATE OSTATE; /**< \brief 80, OSCU Status Register */
|
||||
Ifx_CBS_INTMOD INTMOD; /**< \brief 84, Internal Mode Status and Control Register */
|
||||
Ifx_CBS_ICTSA ICTSA; /**< \brief 88, Internally Controlled Trace Source Register */
|
||||
Ifx_CBS_ICTTA ICTTA; /**< \brief 8C, Internally Controlled Trace Destination Register */
|
||||
Ifx_CBS_TLC TLC; /**< \brief 90, TG Line Control */
|
||||
Ifx_CBS_TL1ST TL1ST; /**< \brief 94, TG Line 1 Suspend Targets */
|
||||
Ifx_CBS_TLCHE TLCHE; /**< \brief 98, TG Line Capture and Hold Enable */
|
||||
Ifx_CBS_TLCHS TLCHS; /**< \brief 9C, TG Line Capture and Hold Clear */
|
||||
Ifx_CBS_TRIGS TRIGS; /**< \brief A0, Set Trigger to Host Register */
|
||||
Ifx_CBS_TRIGC TRIGC; /**< \brief A4, Clear Trigger to Host Register */
|
||||
Ifx_CBS_TLT TLT; /**< \brief A8, TG Line Timer */
|
||||
Ifx_CBS_TLTTH TLTTH; /**< \brief AC, TG Lines for Trigger to Host */
|
||||
Ifx_CBS_TCCB TCCB; /**< \brief B0, TG Capture for Cores - BRKOUT */
|
||||
Ifx_CBS_TCCH TCCH; /**< \brief B4, TG Capture for Cores - HALT */
|
||||
Ifx_CBS_TCTGB TCTGB; /**< \brief B8, TG Capture for OTGB0/1 */
|
||||
Ifx_CBS_TCM TCM; /**< \brief BC, TG Capture for MCDS */
|
||||
Ifx_CBS_TREC TREC[2]; /**< \brief C0, TG Routing Events of CPU */
|
||||
unsigned char reserved_C8[20]; /**< \brief C8, \internal Reserved */
|
||||
Ifx_CBS_TRMT TRMT; /**< \brief DC, TG Routing for MCDS Triggers */
|
||||
Ifx_CBS_TRTGB TRTGB[2]; /**< \brief E0, TG Routing for OTGB */
|
||||
unsigned char reserved_F0[16]; /**< \brief F0, \internal Reserved */
|
||||
Ifx_CBS_TRIG TRIG[22]; /**< \brief 100, Trigger to Host Register */
|
||||
unsigned char reserved_158[168]; /**< \brief 158, \internal Reserved */
|
||||
} Ifx_CBS;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXCBS_REGDEF_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,329 @@
|
||||
/**
|
||||
* \file IfxCcu6_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Ccu6_Cfg Ccu6 address
|
||||
* \ingroup IfxLld_Ccu6
|
||||
*
|
||||
* \defgroup IfxLld_Ccu6_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Ccu6_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Ccu6_Cfg_Ccu60 2-CCU60
|
||||
* \ingroup IfxLld_Ccu6_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Ccu6_Cfg_Ccu61 2-CCU61
|
||||
* \ingroup IfxLld_Ccu6_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXCCU6_REG_H
|
||||
#define IFXCCU6_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxCcu6_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ccu6_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief CCU6 object */
|
||||
#define MODULE_CCU60 /*lint --e(923)*/ (*(Ifx_CCU6*)0xF0002A00u)
|
||||
|
||||
/** \brief CCU6 object */
|
||||
#define MODULE_CCU61 /*lint --e(923)*/ (*(Ifx_CCU6*)0xF0002B00u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ccu6_Cfg_Ccu60
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define CCU60_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_ACCEN0*)0xF0002AFCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define CCU60_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_CCU6_ACCEN1*)0xF0002AF8u)
|
||||
|
||||
/** \brief 30, Capture/Compare Register for Channel CC60 */
|
||||
#define CCU60_CC60R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC60R*)0xF0002A30u)
|
||||
|
||||
/** \brief 40, Capture/Compare Shadow Reg. for Channel CC60 */
|
||||
#define CCU60_CC60SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC60SR*)0xF0002A40u)
|
||||
|
||||
/** \brief 34, Capture/Compare Register for Channel CC61 */
|
||||
#define CCU60_CC61R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC61R*)0xF0002A34u)
|
||||
|
||||
/** \brief 44, Capture/Compare Shadow Reg. for Channel CC61 */
|
||||
#define CCU60_CC61SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC61SR*)0xF0002A44u)
|
||||
|
||||
/** \brief 38, Capture/Compare Register for Channel CC62 */
|
||||
#define CCU60_CC62R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC62R*)0xF0002A38u)
|
||||
|
||||
/** \brief 48, Capture/Compare Shadow Reg. for Channel CC62 */
|
||||
#define CCU60_CC62SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC62SR*)0xF0002A48u)
|
||||
|
||||
/** \brief 58, Compare Register for T13 */
|
||||
#define CCU60_CC63R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC63R*)0xF0002A58u)
|
||||
|
||||
/** \brief 5C, Compare Shadow Register for T13 */
|
||||
#define CCU60_CC63SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC63SR*)0xF0002A5Cu)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define CCU60_CLC /*lint --e(923)*/ (*(volatile Ifx_CCU6_CLC*)0xF0002A00u)
|
||||
|
||||
/** \brief 64, Compare State Modification Register */
|
||||
#define CCU60_CMPMODIF /*lint --e(923)*/ (*(volatile Ifx_CCU6_CMPMODIF*)0xF0002A64u)
|
||||
|
||||
/** \brief 60, Compare State Register */
|
||||
#define CCU60_CMPSTAT /*lint --e(923)*/ (*(volatile Ifx_CCU6_CMPSTAT*)0xF0002A60u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define CCU60_ID /*lint --e(923)*/ (*(volatile Ifx_CCU6_ID*)0xF0002A08u)
|
||||
|
||||
/** \brief B0, Interrupt Enable Register */
|
||||
#define CCU60_IEN /*lint --e(923)*/ (*(volatile Ifx_CCU6_IEN*)0xF0002AB0u)
|
||||
|
||||
/** \brief 98, Input Monitoring Register */
|
||||
#define CCU60_IMON /*lint --e(923)*/ (*(volatile Ifx_CCU6_IMON*)0xF0002A98u)
|
||||
|
||||
/** \brief AC, Interrupt Node Pointer Register */
|
||||
#define CCU60_INP /*lint --e(923)*/ (*(volatile Ifx_CCU6_INP*)0xF0002AACu)
|
||||
|
||||
/** \brief A0, Interrupt Status Register */
|
||||
#define CCU60_IS /*lint --e(923)*/ (*(volatile Ifx_CCU6_IS*)0xF0002AA0u)
|
||||
|
||||
/** \brief A8, Interrupt Status Reset Register */
|
||||
#define CCU60_ISR /*lint --e(923)*/ (*(volatile Ifx_CCU6_ISR*)0xF0002AA8u)
|
||||
|
||||
/** \brief A4, Interrupt Status Set Register */
|
||||
#define CCU60_ISS /*lint --e(923)*/ (*(volatile Ifx_CCU6_ISS*)0xF0002AA4u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define CCU60_KRST0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRST0*)0xF0002AF4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define CCU60_KRST1 /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRST1*)0xF0002AF0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define CCU60_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRSTCLR*)0xF0002AECu)
|
||||
|
||||
/** \brief 1C, Kernel State Control Sensitivity Register */
|
||||
#define CCU60_KSCSR /*lint --e(923)*/ (*(volatile Ifx_CCU6_KSCSR*)0xF0002A1Cu)
|
||||
|
||||
/** \brief 9C, Lost Indicator Register */
|
||||
#define CCU60_LI /*lint --e(923)*/ (*(volatile Ifx_CCU6_LI*)0xF0002A9Cu)
|
||||
|
||||
/** \brief 4, Module Configuration Register */
|
||||
#define CCU60_MCFG /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCFG*)0xF0002A04u)
|
||||
|
||||
/** \brief 94, Multi-Channel Mode Control Register */
|
||||
#define CCU60_MCMCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMCTR*)0xF0002A94u)
|
||||
|
||||
/** \brief 90, Multi-Channel Mode Output Register */
|
||||
#define CCU60_MCMOUT /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMOUT*)0xF0002A90u)
|
||||
|
||||
/** \brief 8C, Multi-Channel Mode Output Shadow Register */
|
||||
#define CCU60_MCMOUTS /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMOUTS*)0xF0002A8Cu)
|
||||
|
||||
/** \brief 80, Modulation Control Register */
|
||||
#define CCU60_MODCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_MODCTR*)0xF0002A80u)
|
||||
|
||||
/** \brief C, CCU60 Module Output Select Register */
|
||||
#define CCU60_MOSEL /*lint --e(923)*/ (*(volatile Ifx_CCU6_MOSEL*)0xF0002A0Cu)
|
||||
|
||||
/** \brief E8, OCDS Control and Status Register */
|
||||
#define CCU60_OCS /*lint --e(923)*/ (*(volatile Ifx_CCU6_OCS*)0xF0002AE8u)
|
||||
|
||||
/** \brief 10, Port Input Select Register 0 */
|
||||
#define CCU60_PISEL0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_PISEL0*)0xF0002A10u)
|
||||
|
||||
/** \brief 14, Port Input Select Register 2 */
|
||||
#define CCU60_PISEL2 /*lint --e(923)*/ (*(volatile Ifx_CCU6_PISEL2*)0xF0002A14u)
|
||||
|
||||
/** \brief 88, Passive State Level Register */
|
||||
#define CCU60_PSLR /*lint --e(923)*/ (*(volatile Ifx_CCU6_PSLR*)0xF0002A88u)
|
||||
|
||||
/** \brief 20, Timer T12 Counter Register */
|
||||
#define CCU60_T12 /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12*)0xF0002A20u)
|
||||
|
||||
/** \brief 28, Dead-Time Control Register for Timer12 */
|
||||
#define CCU60_T12DTC /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12DTC*)0xF0002A28u)
|
||||
|
||||
/** \brief 68, T12 Mode Select Register */
|
||||
#define CCU60_T12MSEL /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12MSEL*)0xF0002A68u)
|
||||
|
||||
/** \brief 24, Timer 12 Period Register */
|
||||
#define CCU60_T12PR /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12PR*)0xF0002A24u)
|
||||
|
||||
/** \brief 50, Timer T13 Counter Register */
|
||||
#define CCU60_T13 /*lint --e(923)*/ (*(volatile Ifx_CCU6_T13*)0xF0002A50u)
|
||||
|
||||
/** \brief 54, Timer 13 Period Register */
|
||||
#define CCU60_T13PR /*lint --e(923)*/ (*(volatile Ifx_CCU6_T13PR*)0xF0002A54u)
|
||||
|
||||
/** \brief 70, Timer Control Register 0 */
|
||||
#define CCU60_TCTR0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR0*)0xF0002A70u)
|
||||
|
||||
/** \brief 74, Timer Control Register 2 */
|
||||
#define CCU60_TCTR2 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR2*)0xF0002A74u)
|
||||
|
||||
/** \brief 78, Timer Control Register 4 */
|
||||
#define CCU60_TCTR4 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR4*)0xF0002A78u)
|
||||
|
||||
/** \brief 84, Trap Control Register */
|
||||
#define CCU60_TRPCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_TRPCTR*)0xF0002A84u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ccu6_Cfg_Ccu61
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define CCU61_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_ACCEN0*)0xF0002BFCu)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define CCU61_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_CCU6_ACCEN1*)0xF0002BF8u)
|
||||
|
||||
/** \brief 30, Capture/Compare Register for Channel CC60 */
|
||||
#define CCU61_CC60R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC60R*)0xF0002B30u)
|
||||
|
||||
/** \brief 40, Capture/Compare Shadow Reg. for Channel CC60 */
|
||||
#define CCU61_CC60SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC60SR*)0xF0002B40u)
|
||||
|
||||
/** \brief 34, Capture/Compare Register for Channel CC61 */
|
||||
#define CCU61_CC61R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC61R*)0xF0002B34u)
|
||||
|
||||
/** \brief 44, Capture/Compare Shadow Reg. for Channel CC61 */
|
||||
#define CCU61_CC61SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC61SR*)0xF0002B44u)
|
||||
|
||||
/** \brief 38, Capture/Compare Register for Channel CC62 */
|
||||
#define CCU61_CC62R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC62R*)0xF0002B38u)
|
||||
|
||||
/** \brief 48, Capture/Compare Shadow Reg. for Channel CC62 */
|
||||
#define CCU61_CC62SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC62SR*)0xF0002B48u)
|
||||
|
||||
/** \brief 58, Compare Register for T13 */
|
||||
#define CCU61_CC63R /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC63R*)0xF0002B58u)
|
||||
|
||||
/** \brief 5C, Compare Shadow Register for T13 */
|
||||
#define CCU61_CC63SR /*lint --e(923)*/ (*(volatile Ifx_CCU6_CC63SR*)0xF0002B5Cu)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define CCU61_CLC /*lint --e(923)*/ (*(volatile Ifx_CCU6_CLC*)0xF0002B00u)
|
||||
|
||||
/** \brief 64, Compare State Modification Register */
|
||||
#define CCU61_CMPMODIF /*lint --e(923)*/ (*(volatile Ifx_CCU6_CMPMODIF*)0xF0002B64u)
|
||||
|
||||
/** \brief 60, Compare State Register */
|
||||
#define CCU61_CMPSTAT /*lint --e(923)*/ (*(volatile Ifx_CCU6_CMPSTAT*)0xF0002B60u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define CCU61_ID /*lint --e(923)*/ (*(volatile Ifx_CCU6_ID*)0xF0002B08u)
|
||||
|
||||
/** \brief B0, Interrupt Enable Register */
|
||||
#define CCU61_IEN /*lint --e(923)*/ (*(volatile Ifx_CCU6_IEN*)0xF0002BB0u)
|
||||
|
||||
/** \brief 98, Input Monitoring Register */
|
||||
#define CCU61_IMON /*lint --e(923)*/ (*(volatile Ifx_CCU6_IMON*)0xF0002B98u)
|
||||
|
||||
/** \brief AC, Interrupt Node Pointer Register */
|
||||
#define CCU61_INP /*lint --e(923)*/ (*(volatile Ifx_CCU6_INP*)0xF0002BACu)
|
||||
|
||||
/** \brief A0, Interrupt Status Register */
|
||||
#define CCU61_IS /*lint --e(923)*/ (*(volatile Ifx_CCU6_IS*)0xF0002BA0u)
|
||||
|
||||
/** \brief A8, Interrupt Status Reset Register */
|
||||
#define CCU61_ISR /*lint --e(923)*/ (*(volatile Ifx_CCU6_ISR*)0xF0002BA8u)
|
||||
|
||||
/** \brief A4, Interrupt Status Set Register */
|
||||
#define CCU61_ISS /*lint --e(923)*/ (*(volatile Ifx_CCU6_ISS*)0xF0002BA4u)
|
||||
|
||||
/** \brief F4, Kernel Reset Register 0 */
|
||||
#define CCU61_KRST0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRST0*)0xF0002BF4u)
|
||||
|
||||
/** \brief F0, Kernel Reset Register 1 */
|
||||
#define CCU61_KRST1 /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRST1*)0xF0002BF0u)
|
||||
|
||||
/** \brief EC, Kernel Reset Status Clear Register */
|
||||
#define CCU61_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_CCU6_KRSTCLR*)0xF0002BECu)
|
||||
|
||||
/** \brief 1C, Kernel State Control Sensitivity Register */
|
||||
#define CCU61_KSCSR /*lint --e(923)*/ (*(volatile Ifx_CCU6_KSCSR*)0xF0002B1Cu)
|
||||
|
||||
/** \brief 9C, Lost Indicator Register */
|
||||
#define CCU61_LI /*lint --e(923)*/ (*(volatile Ifx_CCU6_LI*)0xF0002B9Cu)
|
||||
|
||||
/** \brief 4, Module Configuration Register */
|
||||
#define CCU61_MCFG /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCFG*)0xF0002B04u)
|
||||
|
||||
/** \brief 94, Multi-Channel Mode Control Register */
|
||||
#define CCU61_MCMCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMCTR*)0xF0002B94u)
|
||||
|
||||
/** \brief 90, Multi-Channel Mode Output Register */
|
||||
#define CCU61_MCMOUT /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMOUT*)0xF0002B90u)
|
||||
|
||||
/** \brief 8C, Multi-Channel Mode Output Shadow Register */
|
||||
#define CCU61_MCMOUTS /*lint --e(923)*/ (*(volatile Ifx_CCU6_MCMOUTS*)0xF0002B8Cu)
|
||||
|
||||
/** \brief 80, Modulation Control Register */
|
||||
#define CCU61_MODCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_MODCTR*)0xF0002B80u)
|
||||
|
||||
/** \brief E8, OCDS Control and Status Register */
|
||||
#define CCU61_OCS /*lint --e(923)*/ (*(volatile Ifx_CCU6_OCS*)0xF0002BE8u)
|
||||
|
||||
/** \brief 10, Port Input Select Register 0 */
|
||||
#define CCU61_PISEL0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_PISEL0*)0xF0002B10u)
|
||||
|
||||
/** \brief 14, Port Input Select Register 2 */
|
||||
#define CCU61_PISEL2 /*lint --e(923)*/ (*(volatile Ifx_CCU6_PISEL2*)0xF0002B14u)
|
||||
|
||||
/** \brief 88, Passive State Level Register */
|
||||
#define CCU61_PSLR /*lint --e(923)*/ (*(volatile Ifx_CCU6_PSLR*)0xF0002B88u)
|
||||
|
||||
/** \brief 20, Timer T12 Counter Register */
|
||||
#define CCU61_T12 /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12*)0xF0002B20u)
|
||||
|
||||
/** \brief 28, Dead-Time Control Register for Timer12 */
|
||||
#define CCU61_T12DTC /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12DTC*)0xF0002B28u)
|
||||
|
||||
/** \brief 68, T12 Mode Select Register */
|
||||
#define CCU61_T12MSEL /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12MSEL*)0xF0002B68u)
|
||||
|
||||
/** \brief 24, Timer 12 Period Register */
|
||||
#define CCU61_T12PR /*lint --e(923)*/ (*(volatile Ifx_CCU6_T12PR*)0xF0002B24u)
|
||||
|
||||
/** \brief 50, Timer T13 Counter Register */
|
||||
#define CCU61_T13 /*lint --e(923)*/ (*(volatile Ifx_CCU6_T13*)0xF0002B50u)
|
||||
|
||||
/** \brief 54, Timer 13 Period Register */
|
||||
#define CCU61_T13PR /*lint --e(923)*/ (*(volatile Ifx_CCU6_T13PR*)0xF0002B54u)
|
||||
|
||||
/** \brief 70, Timer Control Register 0 */
|
||||
#define CCU61_TCTR0 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR0*)0xF0002B70u)
|
||||
|
||||
/** \brief 74, Timer Control Register 2 */
|
||||
#define CCU61_TCTR2 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR2*)0xF0002B74u)
|
||||
|
||||
/** \brief 78, Timer Control Register 4 */
|
||||
#define CCU61_TCTR4 /*lint --e(923)*/ (*(volatile Ifx_CCU6_TCTR4*)0xF0002B78u)
|
||||
|
||||
/** \brief 84, Trap Control Register */
|
||||
#define CCU61_TRPCTR /*lint --e(923)*/ (*(volatile Ifx_CCU6_TRPCTR*)0xF0002B84u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXCCU6_REG_H */
|
||||
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@@ -0,0 +1,435 @@
|
||||
/**
|
||||
* \file IfxDsadc_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Dsadc_Cfg Dsadc address
|
||||
* \ingroup IfxLld_Dsadc
|
||||
*
|
||||
* \defgroup IfxLld_Dsadc_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Dsadc_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Dsadc_Cfg_Dsadc 2-DSADC
|
||||
* \ingroup IfxLld_Dsadc_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXDSADC_REG_H
|
||||
#define IFXDSADC_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxDsadc_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Dsadc_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief DSADC object */
|
||||
#define MODULE_DSADC /*lint --e(923)*/ (*(Ifx_DSADC*)0xF0024000u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Dsadc_Cfg_Dsadc
|
||||
* \{ */
|
||||
|
||||
/** \brief 3C, Access Enable Register 0 */
|
||||
#define DSADC_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_DSADC_ACCEN0*)0xF002403Cu)
|
||||
|
||||
/** \brief 90, Access Protection Register */
|
||||
#define DSADC_ACCPROT /*lint --e(923)*/ (*(volatile Ifx_DSADC_ACCPROT*)0xF0024090u)
|
||||
|
||||
/** \brief A0, Carrier Generator Configuration Register */
|
||||
#define DSADC_CGCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CGCFG*)0xF00240A0u)
|
||||
|
||||
/** \brief 128, Boundary Select Register */
|
||||
#define DSADC_CH0_BOUNDSEL /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_BOUNDSEL*)0xF0024128u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_BOUNDSEL.
|
||||
* To use register names with standard convension, please use DSADC_CH0_BOUNDSEL.
|
||||
*/
|
||||
#define DSADC_BOUNDSEL0 (DSADC_CH0_BOUNDSEL)
|
||||
|
||||
/** \brief 1A0, Carrier Generator Synchronization Register */
|
||||
#define DSADC_CH0_CGSYNC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_CGSYNC*)0xF00241A0u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_CGSYNC.
|
||||
* To use register names with standard convension, please use DSADC_CH0_CGSYNC.
|
||||
*/
|
||||
#define DSADC_CGSYNC0 (DSADC_CH0_CGSYNC)
|
||||
|
||||
/** \brief 108, Demodulator Input Configuration Register */
|
||||
#define DSADC_CH0_DICFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_DICFG*)0xF0024108u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_DICFG.
|
||||
* To use register names with standard convension, please use DSADC_CH0_DICFG.
|
||||
*/
|
||||
#define DSADC_DICFG0 (DSADC_CH0_DICFG)
|
||||
|
||||
/** \brief 118, Filter Configuration Register, Auxiliary Filter */
|
||||
#define DSADC_CH0_FCFGA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGA*)0xF0024118u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_FCFGA.
|
||||
* To use register names with standard convension, please use DSADC_CH0_FCFGA.
|
||||
*/
|
||||
#define DSADC_FCFGA0 (DSADC_CH0_FCFGA)
|
||||
|
||||
/** \brief 114, Filter Configuration Register, Main CIC Filter */
|
||||
#define DSADC_CH0_FCFGC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGC*)0xF0024114u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_FCFGC.
|
||||
* To use register names with standard convension, please use DSADC_CH0_FCFGC.
|
||||
*/
|
||||
#define DSADC_FCFGC0 (DSADC_CH0_FCFGC)
|
||||
|
||||
/** \brief 110, Filter Configuration Register, Main Filter Chain */
|
||||
#define DSADC_CH0_FCFGM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGM*)0xF0024110u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_FCFGM.
|
||||
* To use register names with standard convension, please use DSADC_CH0_FCFGM.
|
||||
*/
|
||||
#define DSADC_FCFGM0 (DSADC_CH0_FCFGM)
|
||||
|
||||
/** \brief 1D0, Initial Channel Config. Reg. 0 */
|
||||
#define DSADC_CH0_ICCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_ICCFG*)0xF00241D0u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_ICCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH0_ICCFG.
|
||||
*/
|
||||
#define DSADC_ICCFG0 (DSADC_CH0_ICCFG)
|
||||
|
||||
/** \brief 120, Integration Window Control Register */
|
||||
#define DSADC_CH0_IWCTR /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_IWCTR*)0xF0024120u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_IWCTR.
|
||||
* To use register names with standard convension, please use DSADC_CH0_IWCTR.
|
||||
*/
|
||||
#define DSADC_IWCTR0 (DSADC_CH0_IWCTR)
|
||||
|
||||
/** \brief 100, Modulator Configuration Register */
|
||||
#define DSADC_CH0_MODCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_MODCFG*)0xF0024100u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_MODCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH0_MODCFG.
|
||||
*/
|
||||
#define DSADC_MODCFG0 (DSADC_CH0_MODCFG)
|
||||
|
||||
/** \brief 138, Offset Register Main Filter */
|
||||
#define DSADC_CH0_OFFM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_OFFM*)0xF0024138u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_OFFM.
|
||||
* To use register names with standard convension, please use DSADC_CH0_OFFM.
|
||||
*/
|
||||
#define DSADC_OFFM0 (DSADC_CH0_OFFM)
|
||||
|
||||
/** \brief 1A8, Rectification Configuration Register */
|
||||
#define DSADC_CH0_RECTCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RECTCFG*)0xF00241A8u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_RECTCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH0_RECTCFG.
|
||||
*/
|
||||
#define DSADC_RECTCFG0 (DSADC_CH0_RECTCFG)
|
||||
|
||||
/** \brief 140, Result Register Auxiliary Filter */
|
||||
#define DSADC_CH0_RESA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESA*)0xF0024140u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_RESA.
|
||||
* To use register names with standard convension, please use DSADC_CH0_RESA.
|
||||
*/
|
||||
#define DSADC_RESA0 (DSADC_CH0_RESA)
|
||||
|
||||
/** \brief 130, Result Register Main Filter */
|
||||
#define DSADC_CH0_RESM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESM*)0xF0024130u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_RESM.
|
||||
* To use register names with standard convension, please use DSADC_CH0_RESM.
|
||||
*/
|
||||
#define DSADC_RESM0 (DSADC_CH0_RESM)
|
||||
|
||||
/** \brief 150, Time-Stamp Register */
|
||||
#define DSADC_CH0_TSTMP /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_TSTMP*)0xF0024150u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH0_TSTMP.
|
||||
* To use register names with standard convension, please use DSADC_CH0_TSTMP.
|
||||
*/
|
||||
#define DSADC_TSTMP0 (DSADC_CH0_TSTMP)
|
||||
|
||||
/** \brief 328, Boundary Select Register */
|
||||
#define DSADC_CH2_BOUNDSEL /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_BOUNDSEL*)0xF0024328u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_BOUNDSEL.
|
||||
* To use register names with standard convension, please use DSADC_CH2_BOUNDSEL.
|
||||
*/
|
||||
#define DSADC_BOUNDSEL2 (DSADC_CH2_BOUNDSEL)
|
||||
|
||||
/** \brief 3A0, Carrier Generator Synchronization Register */
|
||||
#define DSADC_CH2_CGSYNC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_CGSYNC*)0xF00243A0u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_CGSYNC.
|
||||
* To use register names with standard convension, please use DSADC_CH2_CGSYNC.
|
||||
*/
|
||||
#define DSADC_CGSYNC2 (DSADC_CH2_CGSYNC)
|
||||
|
||||
/** \brief 308, Demodulator Input Configuration Register */
|
||||
#define DSADC_CH2_DICFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_DICFG*)0xF0024308u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_DICFG.
|
||||
* To use register names with standard convension, please use DSADC_CH2_DICFG.
|
||||
*/
|
||||
#define DSADC_DICFG2 (DSADC_CH2_DICFG)
|
||||
|
||||
/** \brief 318, Filter Configuration Register, Auxiliary Filter */
|
||||
#define DSADC_CH2_FCFGA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGA*)0xF0024318u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_FCFGA.
|
||||
* To use register names with standard convension, please use DSADC_CH2_FCFGA.
|
||||
*/
|
||||
#define DSADC_FCFGA2 (DSADC_CH2_FCFGA)
|
||||
|
||||
/** \brief 314, Filter Configuration Register, Main CIC Filter */
|
||||
#define DSADC_CH2_FCFGC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGC*)0xF0024314u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_FCFGC.
|
||||
* To use register names with standard convension, please use DSADC_CH2_FCFGC.
|
||||
*/
|
||||
#define DSADC_FCFGC2 (DSADC_CH2_FCFGC)
|
||||
|
||||
/** \brief 310, Filter Configuration Register, Main Filter Chain */
|
||||
#define DSADC_CH2_FCFGM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGM*)0xF0024310u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_FCFGM.
|
||||
* To use register names with standard convension, please use DSADC_CH2_FCFGM.
|
||||
*/
|
||||
#define DSADC_FCFGM2 (DSADC_CH2_FCFGM)
|
||||
|
||||
/** \brief 3D0, Initial Channel Config. Reg. 0 */
|
||||
#define DSADC_CH2_ICCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_ICCFG*)0xF00243D0u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_ICCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH2_ICCFG.
|
||||
*/
|
||||
#define DSADC_ICCFG2 (DSADC_CH2_ICCFG)
|
||||
|
||||
/** \brief 320, Integration Window Control Register */
|
||||
#define DSADC_CH2_IWCTR /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_IWCTR*)0xF0024320u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_IWCTR.
|
||||
* To use register names with standard convension, please use DSADC_CH2_IWCTR.
|
||||
*/
|
||||
#define DSADC_IWCTR2 (DSADC_CH2_IWCTR)
|
||||
|
||||
/** \brief 300, Modulator Configuration Register */
|
||||
#define DSADC_CH2_MODCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_MODCFG*)0xF0024300u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_MODCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH2_MODCFG.
|
||||
*/
|
||||
#define DSADC_MODCFG2 (DSADC_CH2_MODCFG)
|
||||
|
||||
/** \brief 338, Offset Register Main Filter */
|
||||
#define DSADC_CH2_OFFM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_OFFM*)0xF0024338u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_OFFM.
|
||||
* To use register names with standard convension, please use DSADC_CH2_OFFM.
|
||||
*/
|
||||
#define DSADC_OFFM2 (DSADC_CH2_OFFM)
|
||||
|
||||
/** \brief 3A8, Rectification Configuration Register */
|
||||
#define DSADC_CH2_RECTCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RECTCFG*)0xF00243A8u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_RECTCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH2_RECTCFG.
|
||||
*/
|
||||
#define DSADC_RECTCFG2 (DSADC_CH2_RECTCFG)
|
||||
|
||||
/** \brief 340, Result Register Auxiliary Filter */
|
||||
#define DSADC_CH2_RESA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESA*)0xF0024340u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_RESA.
|
||||
* To use register names with standard convension, please use DSADC_CH2_RESA.
|
||||
*/
|
||||
#define DSADC_RESA2 (DSADC_CH2_RESA)
|
||||
|
||||
/** \brief 330, Result Register Main Filter */
|
||||
#define DSADC_CH2_RESM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESM*)0xF0024330u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_RESM.
|
||||
* To use register names with standard convension, please use DSADC_CH2_RESM.
|
||||
*/
|
||||
#define DSADC_RESM2 (DSADC_CH2_RESM)
|
||||
|
||||
/** \brief 350, Time-Stamp Register */
|
||||
#define DSADC_CH2_TSTMP /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_TSTMP*)0xF0024350u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH2_TSTMP.
|
||||
* To use register names with standard convension, please use DSADC_CH2_TSTMP.
|
||||
*/
|
||||
#define DSADC_TSTMP2 (DSADC_CH2_TSTMP)
|
||||
|
||||
/** \brief 428, Boundary Select Register */
|
||||
#define DSADC_CH3_BOUNDSEL /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_BOUNDSEL*)0xF0024428u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_BOUNDSEL.
|
||||
* To use register names with standard convension, please use DSADC_CH3_BOUNDSEL.
|
||||
*/
|
||||
#define DSADC_BOUNDSEL3 (DSADC_CH3_BOUNDSEL)
|
||||
|
||||
/** \brief 4A0, Carrier Generator Synchronization Register */
|
||||
#define DSADC_CH3_CGSYNC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_CGSYNC*)0xF00244A0u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_CGSYNC.
|
||||
* To use register names with standard convension, please use DSADC_CH3_CGSYNC.
|
||||
*/
|
||||
#define DSADC_CGSYNC3 (DSADC_CH3_CGSYNC)
|
||||
|
||||
/** \brief 408, Demodulator Input Configuration Register */
|
||||
#define DSADC_CH3_DICFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_DICFG*)0xF0024408u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_DICFG.
|
||||
* To use register names with standard convension, please use DSADC_CH3_DICFG.
|
||||
*/
|
||||
#define DSADC_DICFG3 (DSADC_CH3_DICFG)
|
||||
|
||||
/** \brief 418, Filter Configuration Register, Auxiliary Filter */
|
||||
#define DSADC_CH3_FCFGA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGA*)0xF0024418u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_FCFGA.
|
||||
* To use register names with standard convension, please use DSADC_CH3_FCFGA.
|
||||
*/
|
||||
#define DSADC_FCFGA3 (DSADC_CH3_FCFGA)
|
||||
|
||||
/** \brief 414, Filter Configuration Register, Main CIC Filter */
|
||||
#define DSADC_CH3_FCFGC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGC*)0xF0024414u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_FCFGC.
|
||||
* To use register names with standard convension, please use DSADC_CH3_FCFGC.
|
||||
*/
|
||||
#define DSADC_FCFGC3 (DSADC_CH3_FCFGC)
|
||||
|
||||
/** \brief 410, Filter Configuration Register, Main Filter Chain */
|
||||
#define DSADC_CH3_FCFGM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_FCFGM*)0xF0024410u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_FCFGM.
|
||||
* To use register names with standard convension, please use DSADC_CH3_FCFGM.
|
||||
*/
|
||||
#define DSADC_FCFGM3 (DSADC_CH3_FCFGM)
|
||||
|
||||
/** \brief 4D0, Initial Channel Config. Reg. 0 */
|
||||
#define DSADC_CH3_ICCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_ICCFG*)0xF00244D0u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_ICCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH3_ICCFG.
|
||||
*/
|
||||
#define DSADC_ICCFG3 (DSADC_CH3_ICCFG)
|
||||
|
||||
/** \brief 420, Integration Window Control Register */
|
||||
#define DSADC_CH3_IWCTR /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_IWCTR*)0xF0024420u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_IWCTR.
|
||||
* To use register names with standard convension, please use DSADC_CH3_IWCTR.
|
||||
*/
|
||||
#define DSADC_IWCTR3 (DSADC_CH3_IWCTR)
|
||||
|
||||
/** \brief 400, Modulator Configuration Register */
|
||||
#define DSADC_CH3_MODCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_MODCFG*)0xF0024400u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_MODCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH3_MODCFG.
|
||||
*/
|
||||
#define DSADC_MODCFG3 (DSADC_CH3_MODCFG)
|
||||
|
||||
/** \brief 438, Offset Register Main Filter */
|
||||
#define DSADC_CH3_OFFM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_OFFM*)0xF0024438u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_OFFM.
|
||||
* To use register names with standard convension, please use DSADC_CH3_OFFM.
|
||||
*/
|
||||
#define DSADC_OFFM3 (DSADC_CH3_OFFM)
|
||||
|
||||
/** \brief 4A8, Rectification Configuration Register */
|
||||
#define DSADC_CH3_RECTCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RECTCFG*)0xF00244A8u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_RECTCFG.
|
||||
* To use register names with standard convension, please use DSADC_CH3_RECTCFG.
|
||||
*/
|
||||
#define DSADC_RECTCFG3 (DSADC_CH3_RECTCFG)
|
||||
|
||||
/** \brief 440, Result Register Auxiliary Filter */
|
||||
#define DSADC_CH3_RESA /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESA*)0xF0024440u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_RESA.
|
||||
* To use register names with standard convension, please use DSADC_CH3_RESA.
|
||||
*/
|
||||
#define DSADC_RESA3 (DSADC_CH3_RESA)
|
||||
|
||||
/** \brief 430, Result Register Main Filter */
|
||||
#define DSADC_CH3_RESM /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_RESM*)0xF0024430u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_RESM.
|
||||
* To use register names with standard convension, please use DSADC_CH3_RESM.
|
||||
*/
|
||||
#define DSADC_RESM3 (DSADC_CH3_RESM)
|
||||
|
||||
/** \brief 450, Time-Stamp Register */
|
||||
#define DSADC_CH3_TSTMP /*lint --e(923)*/ (*(volatile Ifx_DSADC_CH_TSTMP*)0xF0024450u)
|
||||
|
||||
/** Alias (User Manual Name) for DSADC_CH3_TSTMP.
|
||||
* To use register names with standard convension, please use DSADC_CH3_TSTMP.
|
||||
*/
|
||||
#define DSADC_TSTMP3 (DSADC_CH3_TSTMP)
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define DSADC_CLC /*lint --e(923)*/ (*(volatile Ifx_DSADC_CLC*)0xF0024000u)
|
||||
|
||||
/** \brief E0, Event Flag Register */
|
||||
#define DSADC_EVFLAG /*lint --e(923)*/ (*(volatile Ifx_DSADC_EVFLAG*)0xF00240E0u)
|
||||
|
||||
/** \brief E4, Event Flag Clear Register */
|
||||
#define DSADC_EVFLAGCLR /*lint --e(923)*/ (*(volatile Ifx_DSADC_EVFLAGCLR*)0xF00240E4u)
|
||||
|
||||
/** \brief 80, Global Configuration Register */
|
||||
#define DSADC_GLOBCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_GLOBCFG*)0xF0024080u)
|
||||
|
||||
/** \brief 88, Global Run Control Register */
|
||||
#define DSADC_GLOBRC /*lint --e(923)*/ (*(volatile Ifx_DSADC_GLOBRC*)0xF0024088u)
|
||||
|
||||
/** \brief B0, Common Mode Hold Voltage Register 0 */
|
||||
#define DSADC_GLOBVCMH0 /*lint --e(923)*/ (*(volatile Ifx_DSADC_GLOBVCMH0*)0xF00240B0u)
|
||||
|
||||
/** \brief B8, Common Mode Hold Voltage Register 2 */
|
||||
#define DSADC_GLOBVCMH2 /*lint --e(923)*/ (*(volatile Ifx_DSADC_GLOBVCMH2*)0xF00240B8u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define DSADC_ID /*lint --e(923)*/ (*(volatile Ifx_DSADC_ID*)0xF0024008u)
|
||||
|
||||
/** \brief D0, Initial Global Config. Register */
|
||||
#define DSADC_IGCFG /*lint --e(923)*/ (*(volatile Ifx_DSADC_IGCFG*)0xF00240D0u)
|
||||
|
||||
/** \brief 34, Kernel Reset Register 0 */
|
||||
#define DSADC_KRST0 /*lint --e(923)*/ (*(volatile Ifx_DSADC_KRST0*)0xF0024034u)
|
||||
|
||||
/** \brief 30, Kernel Reset Register 1 */
|
||||
#define DSADC_KRST1 /*lint --e(923)*/ (*(volatile Ifx_DSADC_KRST1*)0xF0024030u)
|
||||
|
||||
/** \brief 2C, Kernel Reset Status Clear Register */
|
||||
#define DSADC_KRSTCLR /*lint --e(923)*/ (*(volatile Ifx_DSADC_KRSTCLR*)0xF002402Cu)
|
||||
|
||||
/** \brief 28, OCDS Control and Status Register */
|
||||
#define DSADC_OCS /*lint --e(923)*/ (*(volatile Ifx_DSADC_OCS*)0xF0024028u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXDSADC_REG_H */
|
||||
@@ -0,0 +1,761 @@
|
||||
/**
|
||||
* \file IfxDsadc_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2015 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC26XB_UM_V1.2.R0
|
||||
* Specification: tc26xB_um_v1.2_MCSFR.xml (Revision: UM_V1.2)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Dsadc Dsadc
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Dsadc_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Dsadc
|
||||
*
|
||||
* \defgroup IfxLld_Dsadc_union Union
|
||||
* \ingroup IfxLld_Dsadc
|
||||
*
|
||||
* \defgroup IfxLld_Dsadc_struct Struct
|
||||
* \ingroup IfxLld_Dsadc
|
||||
*
|
||||
*/
|
||||
#ifndef IFXDSADC_REGDEF_H
|
||||
#define IFXDSADC_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Dsadc_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_DSADC_ACCEN0_Bits
|
||||
{
|
||||
unsigned int EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID 0 (rw) */
|
||||
unsigned int EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID 1 (rw) */
|
||||
unsigned int EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID 2 (rw) */
|
||||
unsigned int EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID 3 (rw) */
|
||||
unsigned int EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID 4 (rw) */
|
||||
unsigned int EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID 5 (rw) */
|
||||
unsigned int EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID 6 (rw) */
|
||||
unsigned int EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID 7 (rw) */
|
||||
unsigned int EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID 8 (rw) */
|
||||
unsigned int EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID 9 (rw) */
|
||||
unsigned int EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID 10 (rw) */
|
||||
unsigned int EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID 11 (rw) */
|
||||
unsigned int EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID 12 (rw) */
|
||||
unsigned int EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID 13 (rw) */
|
||||
unsigned int EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID 14 (rw) */
|
||||
unsigned int EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID 15 (rw) */
|
||||
unsigned int EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID 16 (rw) */
|
||||
unsigned int EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID 17 (rw) */
|
||||
unsigned int EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID 18 (rw) */
|
||||
unsigned int EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID 19 (rw) */
|
||||
unsigned int EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID 20 (rw) */
|
||||
unsigned int EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID 21 (rw) */
|
||||
unsigned int EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID 22 (rw) */
|
||||
unsigned int EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID 23 (rw) */
|
||||
unsigned int EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID 24 (rw) */
|
||||
unsigned int EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID 25 (rw) */
|
||||
unsigned int EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID 26 (rw) */
|
||||
unsigned int EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID 27 (rw) */
|
||||
unsigned int EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID 28 (rw) */
|
||||
unsigned int EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID 29 (rw) */
|
||||
unsigned int EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID 30 (rw) */
|
||||
unsigned int EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID 31 (rw) */
|
||||
} Ifx_DSADC_ACCEN0_Bits;
|
||||
|
||||
/** \brief Access Protection Register */
|
||||
typedef struct _Ifx_DSADC_ACCPROT_Bits
|
||||
{
|
||||
unsigned int RG00:1; /**< \brief [0:0] Register Group 0, Channels 0, 2, 3 (rw) */
|
||||
unsigned int RG01:1; /**< \brief [1:1] Register Group 1, Channels 0, 2, 3 (rw) */
|
||||
unsigned int RG02:1; /**< \brief [2:2] Register Group 2, Channels 0, 2, 3 (rw) */
|
||||
unsigned int RG03:1; /**< \brief [3:3] Register Group 3, Channels 0, 2, 3 (rw) */
|
||||
unsigned int RG04:1; /**< \brief [4:4] Register Group 4, Channels 0, 2, 3 (rw) */
|
||||
unsigned int reserved_5:9; /**< \brief \internal Reserved */
|
||||
unsigned int RG10:1; /**< \brief [14:14] Register Group 0/1, General Control (rw) */
|
||||
unsigned int RG11:1; /**< \brief [15:15] Register Group 0/1, General Control (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_ACCPROT_Bits;
|
||||
|
||||
/** \brief Carrier Generator Configuration Register */
|
||||
typedef struct _Ifx_DSADC_CGCFG_Bits
|
||||
{
|
||||
unsigned int CGMOD:2; /**< \brief [1:0] Carrier Generator Operating Mode (rw) */
|
||||
unsigned int BREV:1; /**< \brief [2:2] Bit-Reverse PWM Generation (rw) */
|
||||
unsigned int SIGPOL:1; /**< \brief [3:3] Signal Polarity (rw) */
|
||||
unsigned int DIVCG:4; /**< \brief [7:4] Divider Factor for the PWM Pattern Signal Generator (rw) */
|
||||
unsigned int reserved_8:7; /**< \brief \internal Reserved */
|
||||
unsigned int RUN:1; /**< \brief [15:15] Run Indicator (rh) */
|
||||
unsigned int BITCOUNT:5; /**< \brief [20:16] Bit Counter (rh) */
|
||||
unsigned int reserved_21:3; /**< \brief \internal Reserved */
|
||||
unsigned int STEPCOUNT:4; /**< \brief [27:24] Step Counter (rh) */
|
||||
unsigned int STEPS:1; /**< \brief [28:28] Step Counter Sign (rh) */
|
||||
unsigned int STEPD:1; /**< \brief [29:29] Step Counter Direction (rh) */
|
||||
unsigned int SGNCG:1; /**< \brief [30:30] Sign Signal from Carrier Generator (rh) */
|
||||
unsigned int reserved_31:1; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_CGCFG_Bits;
|
||||
|
||||
/** \brief Boundary Select Register */
|
||||
typedef struct _Ifx_DSADC_CH_BOUNDSEL_Bits
|
||||
{
|
||||
unsigned int BOUNDARYL:16; /**< \brief [15:0] Lower Boundary Value for Limit Checking (rw) */
|
||||
unsigned int BOUNDARYU:16; /**< \brief [31:16] Upper Boundary Value for Limit Checking (rw) */
|
||||
} Ifx_DSADC_CH_BOUNDSEL_Bits;
|
||||
|
||||
/** \brief Carrier Generator Synchronization Register */
|
||||
typedef struct _Ifx_DSADC_CH_CGSYNC_Bits
|
||||
{
|
||||
unsigned int SDCOUNT:8; /**< \brief [7:0] Sign Delay Counter (rh) */
|
||||
unsigned int SDCAP:8; /**< \brief [15:8] Sign Delay Capture Value (rh) */
|
||||
unsigned int SDPOS:8; /**< \brief [23:16] Sign Delay Value for Positive Halfwave (rw) */
|
||||
unsigned int SDNEG:8; /**< \brief [31:24] Sign Delay Value for Negative Halfwave (rw) */
|
||||
} Ifx_DSADC_CH_CGSYNC_Bits;
|
||||
|
||||
/** \brief Demodulator Input Configuration Register */
|
||||
typedef struct _Ifx_DSADC_CH_DICFG_Bits
|
||||
{
|
||||
unsigned int DSRC:4; /**< \brief [3:0] Input Data Source Select (rw) */
|
||||
unsigned int reserved_4:3; /**< \brief \internal Reserved */
|
||||
unsigned int DSWC:1; /**< \brief [7:7] Write Control for Data Selection (w) */
|
||||
unsigned int ITRMODE:2; /**< \brief [9:8] Integrator Trigger Mode (rw) */
|
||||
unsigned int TSTRMODE:2; /**< \brief [11:10] Timestamp Trigger Mode (rw) */
|
||||
unsigned int TRSEL:3; /**< \brief [14:12] Trigger Select (rw) */
|
||||
unsigned int TRWC:1; /**< \brief [15:15] Write Control for Trigger Parameters (w) */
|
||||
unsigned int CSRC:4; /**< \brief [19:16] Sample Clock Source Select (rw) */
|
||||
unsigned int STROBE:4; /**< \brief [23:20] Data Strobe Generation Mode (rw) */
|
||||
unsigned int reserved_24:7; /**< \brief \internal Reserved */
|
||||
unsigned int SCWC:1; /**< \brief [31:31] Write Control for Strobe/Clock Selection (w) */
|
||||
} Ifx_DSADC_CH_DICFG_Bits;
|
||||
|
||||
/** \brief Filter Configuration Register, Auxiliary Filter */
|
||||
typedef struct _Ifx_DSADC_CH_FCFGA_Bits
|
||||
{
|
||||
unsigned int CFADF:8; /**< \brief [7:0] CIC Filter (Auxiliary) Decimation Factor (rw) */
|
||||
unsigned int CFAC:2; /**< \brief [9:8] CIC Filter (Auxiliary) Configuration (rw) */
|
||||
unsigned int SRGA:2; /**< \brief [11:10] Service Request Generation Auxiliary Filter (rw) */
|
||||
unsigned int ESEL:2; /**< \brief [13:12] Event Select (rw) */
|
||||
unsigned int EGT:1; /**< \brief [14:14] Event Gating (rw) */
|
||||
unsigned int reserved_15:1; /**< \brief \internal Reserved */
|
||||
unsigned int AFSC:2; /**< \brief [17:16] Auxiliary Filter Shift Control (rw) */
|
||||
unsigned int reserved_18:6; /**< \brief \internal Reserved */
|
||||
unsigned int CFADCNT:8; /**< \brief [31:24] CIC Filter (Auxiliary) Decimation Counter (rh) */
|
||||
} Ifx_DSADC_CH_FCFGA_Bits;
|
||||
|
||||
/** \brief Filter Configuration Register, Main CIC Filter */
|
||||
typedef struct _Ifx_DSADC_CH_FCFGC_Bits
|
||||
{
|
||||
unsigned int CFMDF:8; /**< \brief [7:0] CIC Filter (Main Chain) Decimation Factor (rw) */
|
||||
unsigned int CFMC:2; /**< \brief [9:8] CIC Filter (Main Chain) Configuration (rw) */
|
||||
unsigned int CFEN:1; /**< \brief [10:10] CIC Filter Enable (rw) */
|
||||
unsigned int reserved_11:1; /**< \brief \internal Reserved */
|
||||
unsigned int MFSC:2; /**< \brief [13:12] Main Filter Shift Control (rw) */
|
||||
unsigned int SRGM:2; /**< \brief [15:14] Service Request Generation Main Chain (rw) */
|
||||
unsigned int CFMSV:8; /**< \brief [23:16] CIC Filter (Main Chain) Start Value (rw) */
|
||||
unsigned int CFMDCNT:8; /**< \brief [31:24] CIC Filter (Main Chain) Decimation Counter (rh) */
|
||||
} Ifx_DSADC_CH_FCFGC_Bits;
|
||||
|
||||
/** \brief Filter Configuration Register, Main Filter Chain */
|
||||
typedef struct _Ifx_DSADC_CH_FCFGM_Bits
|
||||
{
|
||||
unsigned int FIR0EN:1; /**< \brief [0:0] FIR Filter 0 Enable (rw) */
|
||||
unsigned int FIR1EN:1; /**< \brief [1:1] FIR Filter 1 Enable (rw) */
|
||||
unsigned int OCEN:1; /**< \brief [2:2] Offset Compensation Filter Enable (rw) */
|
||||
unsigned int DSH:2; /**< \brief [4:3] Data Shift Control (rw) */
|
||||
unsigned int FSH:1; /**< \brief [5:5] FIR Shift Control (rw) */
|
||||
unsigned int reserved_6:26; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_CH_FCFGM_Bits;
|
||||
|
||||
/** \brief Initial Channel Config. Reg. 0 */
|
||||
typedef struct _Ifx_DSADC_CH_ICCFG_Bits
|
||||
{
|
||||
unsigned int DI0:1; /**< \brief [0:0] Dithering Function Enable (rw) */
|
||||
unsigned int DI1:1; /**< \brief [1:1] Dithering Function Enable (rw) */
|
||||
unsigned int reserved_2:2; /**< \brief \internal Reserved */
|
||||
unsigned int IREN:1; /**< \brief [4:4] Integrator Reset Enable (rw) */
|
||||
unsigned int reserved_5:3; /**< \brief \internal Reserved */
|
||||
unsigned int TWINSP:6; /**< \brief [13:8] Setup Parameters for this Twin Modulator (rw) */
|
||||
unsigned int reserved_14:17; /**< \brief \internal Reserved */
|
||||
unsigned int WREN:1; /**< \brief [31:31] Write Enable (rw) */
|
||||
} Ifx_DSADC_CH_ICCFG_Bits;
|
||||
|
||||
/** \brief Integration Window Control Register */
|
||||
typedef struct _Ifx_DSADC_CH_IWCTR_Bits
|
||||
{
|
||||
unsigned int NVALCNT:6; /**< \brief [5:0] Number of Values Counted (rh) */
|
||||
unsigned int reserved_6:1; /**< \brief \internal Reserved */
|
||||
unsigned int INTEN:1; /**< \brief [7:7] Integration Enable (rh) */
|
||||
unsigned int REPCNT:4; /**< \brief [11:8] Integration Cycle Counter (rh) */
|
||||
unsigned int REPVAL:4; /**< \brief [15:12] Number of Integration Cycles (rw) */
|
||||
unsigned int NVALDIS:6; /**< \brief [21:16] Number of Values Discarded (rw) */
|
||||
unsigned int reserved_22:1; /**< \brief \internal Reserved */
|
||||
unsigned int IWS:1; /**< \brief [23:23] Integration Window Size (rw) */
|
||||
unsigned int NVALINT:6; /**< \brief [29:24] Number of Values Integrated (rw) */
|
||||
unsigned int reserved_30:2; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_CH_IWCTR_Bits;
|
||||
|
||||
/** \brief Modulator Configuration Register */
|
||||
typedef struct _Ifx_DSADC_CH_MODCFG_Bits
|
||||
{
|
||||
unsigned int INCFGP:2; /**< \brief [1:0] Configuration of Positive Input Line (rw) */
|
||||
unsigned int INCFGN:2; /**< \brief [3:2] Configuration of Negative Input Line (rw) */
|
||||
unsigned int GAINSEL:4; /**< \brief [7:4] Gain Select of Analog Input Path (rw) */
|
||||
unsigned int INSEL:2; /**< \brief [9:8] Input Pin Selection (rw) */
|
||||
unsigned int INMUX:2; /**< \brief [11:10] Input Multiplexer Setting (rh) */
|
||||
unsigned int INMODE:2; /**< \brief [13:12] Input Multiplexer Control Mode (rw) */
|
||||
unsigned int INMAC:1; /**< \brief [14:14] Input Multiplexer Action Control (rw) */
|
||||
unsigned int INCWC:1; /**< \brief [15:15] Write Control for Input Parameters (w) */
|
||||
unsigned int DIVM:4; /**< \brief [19:16] Divider Factor for Modulator Clock (rw) */
|
||||
unsigned int reserved_20:3; /**< \brief \internal Reserved */
|
||||
unsigned int DWC:1; /**< \brief [23:23] Write Control for Divider Factor (w) */
|
||||
unsigned int CMVS:2; /**< \brief [25:24] Common Mode Voltage Selection (rw) */
|
||||
unsigned int MCFG:2; /**< \brief [27:26] Modulator Configuration (rw) */
|
||||
unsigned int GCEN:1; /**< \brief [28:28] Gain Calibration Enable (rw) */
|
||||
unsigned int APC:1; /**< \brief [29:29] Automatic Power Control (rw) */
|
||||
unsigned int reserved_30:1; /**< \brief \internal Reserved */
|
||||
unsigned int MWC:1; /**< \brief [31:31] Write Control for Mode Selection (w) */
|
||||
} Ifx_DSADC_CH_MODCFG_Bits;
|
||||
|
||||
/** \brief Offset Register Main Filter */
|
||||
typedef struct _Ifx_DSADC_CH_OFFM_Bits
|
||||
{
|
||||
unsigned int OFFSET:16; /**< \brief [15:0] Offset Value (rw) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_CH_OFFM_Bits;
|
||||
|
||||
/** \brief Rectification Configuration Register */
|
||||
typedef struct _Ifx_DSADC_CH_RECTCFG_Bits
|
||||
{
|
||||
unsigned int RFEN:1; /**< \brief [0:0] Rectification Enable (rw) */
|
||||
unsigned int reserved_1:3; /**< \brief \internal Reserved */
|
||||
unsigned int SSRC:2; /**< \brief [5:4] Sign Source (rw) */
|
||||
unsigned int reserved_6:9; /**< \brief \internal Reserved */
|
||||
unsigned int SDCVAL:1; /**< \brief [15:15] Sign Delay Capture Valid Flag (rh) */
|
||||
unsigned int reserved_16:14; /**< \brief \internal Reserved */
|
||||
unsigned int SGNCS:1; /**< \brief [30:30] Selected Carrier Sign Signal (rh) */
|
||||
unsigned int SGND:1; /**< \brief [31:31] Sign Signal Delayed (rh) */
|
||||
} Ifx_DSADC_CH_RECTCFG_Bits;
|
||||
|
||||
/** \brief Result Register Auxiliary Filter */
|
||||
typedef struct _Ifx_DSADC_CH_RESA_Bits
|
||||
{
|
||||
unsigned int RESULT:16; /**< \brief [15:0] Result of most recent conversion (rh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_CH_RESA_Bits;
|
||||
|
||||
/** \brief Result Register Main Filter */
|
||||
typedef struct _Ifx_DSADC_CH_RESM_Bits
|
||||
{
|
||||
unsigned int RESULT:16; /**< \brief [15:0] Result of most recent conversion (rh) */
|
||||
unsigned int reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_CH_RESM_Bits;
|
||||
|
||||
/** \brief Time-Stamp Register */
|
||||
typedef struct _Ifx_DSADC_CH_TSTMP_Bits
|
||||
{
|
||||
unsigned int RESULT:16; /**< \brief [15:0] Result of most recent conversion (rh) */
|
||||
unsigned int CFMDCNT:8; /**< \brief [23:16] CIC Filter (Main Chain) Decimation Counter (rh) */
|
||||
unsigned int NVALCNT:6; /**< \brief [29:24] Number of Values Counted (rh) */
|
||||
unsigned int TSVAL:1; /**< \brief [30:30] Timestamp Valid (rh) */
|
||||
unsigned int TSSR:1; /**< \brief [31:31] Timestamp Service Request (rw) */
|
||||
} Ifx_DSADC_CH_TSTMP_Bits;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef struct _Ifx_DSADC_CLC_Bits
|
||||
{
|
||||
unsigned int DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
unsigned int DISS:1; /**< \brief [1:1] Module Disable Status Bit (r) */
|
||||
unsigned int reserved_2:1; /**< \brief \internal Reserved */
|
||||
unsigned int EDIS:1; /**< \brief [3:3] Sleep Mode Enable Control (rw) */
|
||||
unsigned int reserved_4:28; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_CLC_Bits;
|
||||
|
||||
/** \brief Event Flag Register */
|
||||
typedef struct _Ifx_DSADC_EVFLAG_Bits
|
||||
{
|
||||
unsigned int RESEV0:1; /**< \brief [0:0] Result Event (rwh) */
|
||||
unsigned int reserved_1:1; /**< \brief \internal Reserved */
|
||||
unsigned int RESEV2:1; /**< \brief [2:2] Result Event (rwh) */
|
||||
unsigned int RESEV3:1; /**< \brief [3:3] Result Event (rwh) */
|
||||
unsigned int reserved_4:12; /**< \brief \internal Reserved */
|
||||
unsigned int ALEV0:1; /**< \brief [16:16] Alarm Event (rwh) */
|
||||
unsigned int reserved_17:1; /**< \brief \internal Reserved */
|
||||
unsigned int ALEV2:1; /**< \brief [18:18] Alarm Event (rwh) */
|
||||
unsigned int ALEV3:1; /**< \brief [19:19] Alarm Event (rwh) */
|
||||
unsigned int reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_EVFLAG_Bits;
|
||||
|
||||
/** \brief Event Flag Clear Register */
|
||||
typedef struct _Ifx_DSADC_EVFLAGCLR_Bits
|
||||
{
|
||||
unsigned int RESEC0:1; /**< \brief [0:0] Result Event Clear (w) */
|
||||
unsigned int reserved_1:1; /**< \brief \internal Reserved */
|
||||
unsigned int RESEC2:1; /**< \brief [2:2] Result Event Clear (w) */
|
||||
unsigned int RESEC3:1; /**< \brief [3:3] Result Event Clear (w) */
|
||||
unsigned int reserved_4:12; /**< \brief \internal Reserved */
|
||||
unsigned int ALEC0:1; /**< \brief [16:16] Alarm Event Clear (w) */
|
||||
unsigned int reserved_17:1; /**< \brief \internal Reserved */
|
||||
unsigned int ALEC2:1; /**< \brief [18:18] Alarm Event Clear (w) */
|
||||
unsigned int ALEC3:1; /**< \brief [19:19] Alarm Event Clear (w) */
|
||||
unsigned int reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_EVFLAGCLR_Bits;
|
||||
|
||||
/** \brief Global Configuration Register */
|
||||
typedef struct _Ifx_DSADC_GLOBCFG_Bits
|
||||
{
|
||||
unsigned int MCSEL:3; /**< \brief [2:0] Modulator Clock Select (rw) */
|
||||
unsigned int reserved_3:8; /**< \brief \internal Reserved */
|
||||
unsigned int IRM0:1; /**< \brief [11:11] Internal Resistance Measurement Control (rw) */
|
||||
unsigned int reserved_12:4; /**< \brief \internal Reserved */
|
||||
unsigned int IBSEL:4; /**< \brief [19:16] Bias Current Select (rw) */
|
||||
unsigned int LOSUP:1; /**< \brief [20:20] Low Power Supply Voltage Select (rw) */
|
||||
unsigned int reserved_21:1; /**< \brief \internal Reserved */
|
||||
unsigned int ICT:1; /**< \brief [22:22] Internal Channel Test (rw) */
|
||||
unsigned int PSWC:1; /**< \brief [23:23] Write Control for Power Supply Parameters (w) */
|
||||
unsigned int reserved_24:8; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_GLOBCFG_Bits;
|
||||
|
||||
/** \brief Global Run Control Register */
|
||||
typedef struct _Ifx_DSADC_GLOBRC_Bits
|
||||
{
|
||||
unsigned int CH0RUN:1; /**< \brief [0:0] Channel 0 Run Control (rw) */
|
||||
unsigned int reserved_1:1; /**< \brief \internal Reserved */
|
||||
unsigned int CH2RUN:1; /**< \brief [2:2] Channel 2 Run Control (rw) */
|
||||
unsigned int CH3RUN:1; /**< \brief [3:3] Channel 3 Run Control (rw) */
|
||||
unsigned int reserved_4:12; /**< \brief \internal Reserved */
|
||||
unsigned int M0RUN:1; /**< \brief [16:16] Modulator 0 Run Control (rw) */
|
||||
unsigned int reserved_17:1; /**< \brief \internal Reserved */
|
||||
unsigned int M2RUN:1; /**< \brief [18:18] Modulator 2 Run Control (rw) */
|
||||
unsigned int M3RUN:1; /**< \brief [19:19] Modulator 3 Run Control (rw) */
|
||||
unsigned int reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_GLOBRC_Bits;
|
||||
|
||||
/** \brief Common Mode Hold Voltage Register 0 */
|
||||
typedef struct _Ifx_DSADC_GLOBVCMH0_Bits
|
||||
{
|
||||
unsigned int IN0PVC0:1; /**< \brief [0:0] Voltage Control of Positive Inputs 0-1 of CH0 (rw) */
|
||||
unsigned int IN0PVC1:1; /**< \brief [1:1] Voltage Control of Positive Inputs 0-1 of CH0 (rw) */
|
||||
unsigned int reserved_2:2; /**< \brief \internal Reserved */
|
||||
unsigned int IN0NVC0:1; /**< \brief [4:4] Voltage Control of Negative Inputs 0-1 of CH0 (rw) */
|
||||
unsigned int IN0NVC1:1; /**< \brief [5:5] Voltage Control of Negative Inputs 0-1 of CH0 (rw) */
|
||||
unsigned int reserved_6:10; /**< \brief \internal Reserved */
|
||||
unsigned int IN2PVC0:1; /**< \brief [16:16] Voltage Control of Positive Input 0 of CH2 (rw) */
|
||||
unsigned int reserved_17:3; /**< \brief \internal Reserved */
|
||||
unsigned int IN2NVC0:1; /**< \brief [20:20] Voltage Control of Negative Input 0 of CH2 (rw) */
|
||||
unsigned int reserved_21:3; /**< \brief \internal Reserved */
|
||||
unsigned int IN3PVC0:1; /**< \brief [24:24] Voltage Control of Positive Inputs 0-3 of CH3 (rw) */
|
||||
unsigned int IN3PVC1:1; /**< \brief [25:25] Voltage Control of Positive Inputs 0-3 of CH3 (rw) */
|
||||
unsigned int IN3PVC2:1; /**< \brief [26:26] Voltage Control of Positive Inputs 0-3 of CH3 (rw) */
|
||||
unsigned int IN3PVC3:1; /**< \brief [27:27] Voltage Control of Positive Inputs 0-3 of CH3 (rw) */
|
||||
unsigned int IN3NVC0:1; /**< \brief [28:28] Voltage Control of Negative Inputs 0-3 of CH3 (rw) */
|
||||
unsigned int IN3NVC1:1; /**< \brief [29:29] Voltage Control of Negative Inputs 0-3 of CH3 (rw) */
|
||||
unsigned int IN3NVC2:1; /**< \brief [30:30] Voltage Control of Negative Inputs 0-3 of CH3 (rw) */
|
||||
unsigned int IN3NVC3:1; /**< \brief [31:31] Voltage Control of Negative Inputs 0-3 of CH3 (rw) */
|
||||
} Ifx_DSADC_GLOBVCMH0_Bits;
|
||||
|
||||
/** \brief Common Mode Hold Voltage Register 2 */
|
||||
typedef struct _Ifx_DSADC_GLOBVCMH2_Bits
|
||||
{
|
||||
unsigned int reserved_0:29; /**< \brief \internal Reserved */
|
||||
unsigned int VHON:1; /**< \brief [29:29] Common Mode Hold Voltage On (rw) */
|
||||
unsigned int VCMHS:2; /**< \brief [31:30] Common Mode Hold Voltage Selection (rw) */
|
||||
} Ifx_DSADC_GLOBVCMH2_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_DSADC_ID_Bits
|
||||
{
|
||||
unsigned int MODREV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
unsigned int MODTYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
unsigned int MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_DSADC_ID_Bits;
|
||||
|
||||
/** \brief Initial Global Config. Register */
|
||||
typedef struct _Ifx_DSADC_IGCFG_Bits
|
||||
{
|
||||
unsigned int DITRIM:3; /**< \brief [2:0] Trimming Value for the Dithering Function (rw) */
|
||||
unsigned int reserved_3:13; /**< \brief \internal Reserved */
|
||||
unsigned int GLOBSP:10; /**< \brief [25:16] Global Setup Parameters for the MultiADC (rw) */
|
||||
unsigned int reserved_26:5; /**< \brief \internal Reserved */
|
||||
unsigned int WREN:1; /**< \brief [31:31] Write Enable (rw) */
|
||||
} Ifx_DSADC_IGCFG_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef struct _Ifx_DSADC_KRST0_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int RSTSTAT:1; /**< \brief [1:1] Kernel Reset Status (rh) */
|
||||
unsigned int reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_KRST0_Bits;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef struct _Ifx_DSADC_KRST1_Bits
|
||||
{
|
||||
unsigned int RST:1; /**< \brief [0:0] Kernel Reset (rwh) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_KRST1_Bits;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef struct _Ifx_DSADC_KRSTCLR_Bits
|
||||
{
|
||||
unsigned int CLR:1; /**< \brief [0:0] Kernel Reset Status Clear (w) */
|
||||
unsigned int reserved_1:31; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_KRSTCLR_Bits;
|
||||
|
||||
/** \brief OCDS Control and Status Register */
|
||||
typedef struct _Ifx_DSADC_OCS_Bits
|
||||
{
|
||||
unsigned int reserved_0:24; /**< \brief \internal Reserved */
|
||||
unsigned int SUS:4; /**< \brief [27:24] OCDS Suspend Control (rw) */
|
||||
unsigned int SUS_P:1; /**< \brief [28:28] SUS Write Protection (w) */
|
||||
unsigned int SUSSTA:1; /**< \brief [29:29] Suspend State (rh) */
|
||||
unsigned int reserved_30:2; /**< \brief \internal Reserved */
|
||||
} Ifx_DSADC_OCS_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Dsadc_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_ACCEN0;
|
||||
|
||||
/** \brief Access Protection Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_ACCPROT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_ACCPROT;
|
||||
|
||||
/** \brief Carrier Generator Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CGCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CGCFG;
|
||||
|
||||
/** \brief Boundary Select Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_BOUNDSEL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_BOUNDSEL;
|
||||
|
||||
/** \brief Carrier Generator Synchronization Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_CGSYNC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_CGSYNC;
|
||||
|
||||
/** \brief Demodulator Input Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_DICFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_DICFG;
|
||||
|
||||
/** \brief Filter Configuration Register, Auxiliary Filter */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_FCFGA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_FCFGA;
|
||||
|
||||
/** \brief Filter Configuration Register, Main CIC Filter */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_FCFGC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_FCFGC;
|
||||
|
||||
/** \brief Filter Configuration Register, Main Filter Chain */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_FCFGM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_FCFGM;
|
||||
|
||||
/** \brief Initial Channel Config. Reg. 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_ICCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_ICCFG;
|
||||
|
||||
/** \brief Integration Window Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_IWCTR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_IWCTR;
|
||||
|
||||
/** \brief Modulator Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_MODCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_MODCFG;
|
||||
|
||||
/** \brief Offset Register Main Filter */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_OFFM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_OFFM;
|
||||
|
||||
/** \brief Rectification Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_RECTCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_RECTCFG;
|
||||
|
||||
/** \brief Result Register Auxiliary Filter */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_RESA_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_RESA;
|
||||
|
||||
/** \brief Result Register Main Filter */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_RESM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_RESM;
|
||||
|
||||
/** \brief Time-Stamp Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CH_TSTMP_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CH_TSTMP;
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_CLC;
|
||||
|
||||
/** \brief Event Flag Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_EVFLAG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_EVFLAG;
|
||||
|
||||
/** \brief Event Flag Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_EVFLAGCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_EVFLAGCLR;
|
||||
|
||||
/** \brief Global Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_GLOBCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_GLOBCFG;
|
||||
|
||||
/** \brief Global Run Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_GLOBRC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_GLOBRC;
|
||||
|
||||
/** \brief Common Mode Hold Voltage Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_GLOBVCMH0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_GLOBVCMH0;
|
||||
|
||||
/** \brief Common Mode Hold Voltage Register 2 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_GLOBVCMH2_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_GLOBVCMH2;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_ID;
|
||||
|
||||
/** \brief Initial Global Config. Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_IGCFG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_IGCFG;
|
||||
|
||||
/** \brief Kernel Reset Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_KRST0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_KRST0;
|
||||
|
||||
/** \brief Kernel Reset Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_KRST1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_KRST1;
|
||||
|
||||
/** \brief Kernel Reset Status Clear Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_KRSTCLR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_KRSTCLR;
|
||||
|
||||
/** \brief OCDS Control and Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_DSADC_OCS_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_DSADC_OCS;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Dsadc_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L1
|
||||
* \{ */
|
||||
|
||||
/** \brief Channel objects */
|
||||
typedef volatile struct _Ifx_DSADC_CH
|
||||
{
|
||||
Ifx_DSADC_CH_MODCFG MODCFG; /**< \brief 0, Modulator Configuration Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_DSADC_CH_DICFG DICFG; /**< \brief 8, Demodulator Input Configuration Register */
|
||||
unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
|
||||
Ifx_DSADC_CH_FCFGM FCFGM; /**< \brief 10, Filter Configuration Register, Main Filter Chain */
|
||||
Ifx_DSADC_CH_FCFGC FCFGC; /**< \brief 14, Filter Configuration Register, Main CIC Filter */
|
||||
Ifx_DSADC_CH_FCFGA FCFGA; /**< \brief 18, Filter Configuration Register, Auxiliary Filter */
|
||||
unsigned char reserved_1C[4]; /**< \brief 1C, \internal Reserved */
|
||||
Ifx_DSADC_CH_IWCTR IWCTR; /**< \brief 20, Integration Window Control Register */
|
||||
unsigned char reserved_24[4]; /**< \brief 24, \internal Reserved */
|
||||
Ifx_DSADC_CH_BOUNDSEL BOUNDSEL; /**< \brief 28, Boundary Select Register */
|
||||
unsigned char reserved_2C[4]; /**< \brief 2C, \internal Reserved */
|
||||
Ifx_DSADC_CH_RESM RESM; /**< \brief 30, Result Register Main Filter */
|
||||
unsigned char reserved_34[4]; /**< \brief 34, \internal Reserved */
|
||||
Ifx_DSADC_CH_OFFM OFFM; /**< \brief 38, Offset Register Main Filter */
|
||||
unsigned char reserved_3C[4]; /**< \brief 3C, \internal Reserved */
|
||||
Ifx_DSADC_CH_RESA RESA; /**< \brief 40, Result Register Auxiliary Filter */
|
||||
unsigned char reserved_44[12]; /**< \brief 44, \internal Reserved */
|
||||
Ifx_DSADC_CH_TSTMP TSTMP; /**< \brief 50, Time-Stamp Register */
|
||||
unsigned char reserved_54[76]; /**< \brief 54, \internal Reserved */
|
||||
Ifx_DSADC_CH_CGSYNC CGSYNC; /**< \brief A0, Carrier Generator Synchronization Register */
|
||||
unsigned char reserved_A4[4]; /**< \brief A4, \internal Reserved */
|
||||
Ifx_DSADC_CH_RECTCFG RECTCFG; /**< \brief A8, Rectification Configuration Register */
|
||||
unsigned char reserved_AC[36]; /**< \brief AC, \internal Reserved */
|
||||
Ifx_DSADC_CH_ICCFG ICCFG; /**< \brief D0, Initial Channel Config. Reg. 0 */
|
||||
unsigned char reserved_D4[44]; /**< \brief D4, \internal Reserved */
|
||||
} Ifx_DSADC_CH;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Dsadc_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief DSADC object */
|
||||
typedef volatile struct _Ifx_DSADC
|
||||
{
|
||||
Ifx_DSADC_CLC CLC; /**< \brief 0, Clock Control Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_DSADC_ID ID; /**< \brief 8, Module Identification Register */
|
||||
unsigned char reserved_C[28]; /**< \brief C, \internal Reserved */
|
||||
Ifx_DSADC_OCS OCS; /**< \brief 28, OCDS Control and Status Register */
|
||||
Ifx_DSADC_KRSTCLR KRSTCLR; /**< \brief 2C, Kernel Reset Status Clear Register */
|
||||
Ifx_DSADC_KRST1 KRST1; /**< \brief 30, Kernel Reset Register 1 */
|
||||
Ifx_DSADC_KRST0 KRST0; /**< \brief 34, Kernel Reset Register 0 */
|
||||
unsigned char reserved_38[4]; /**< \brief 38, \internal Reserved */
|
||||
Ifx_DSADC_ACCEN0 ACCEN0; /**< \brief 3C, Access Enable Register 0 */
|
||||
unsigned char reserved_40[64]; /**< \brief 40, \internal Reserved */
|
||||
Ifx_DSADC_GLOBCFG GLOBCFG; /**< \brief 80, Global Configuration Register */
|
||||
unsigned char reserved_84[4]; /**< \brief 84, \internal Reserved */
|
||||
Ifx_DSADC_GLOBRC GLOBRC; /**< \brief 88, Global Run Control Register */
|
||||
unsigned char reserved_8C[4]; /**< \brief 8C, \internal Reserved */
|
||||
Ifx_DSADC_ACCPROT ACCPROT; /**< \brief 90, Access Protection Register */
|
||||
unsigned char reserved_94[12]; /**< \brief 94, \internal Reserved */
|
||||
Ifx_DSADC_CGCFG CGCFG; /**< \brief A0, Carrier Generator Configuration Register */
|
||||
unsigned char reserved_A4[12]; /**< \brief A4, \internal Reserved */
|
||||
Ifx_DSADC_GLOBVCMH0 GLOBVCMH0; /**< \brief B0, Common Mode Hold Voltage Register 0 */
|
||||
unsigned char reserved_B4[4]; /**< \brief B4, \internal Reserved */
|
||||
Ifx_DSADC_GLOBVCMH2 GLOBVCMH2; /**< \brief B8, Common Mode Hold Voltage Register 2 */
|
||||
unsigned char reserved_BC[20]; /**< \brief BC, \internal Reserved */
|
||||
Ifx_DSADC_IGCFG IGCFG; /**< \brief D0, Initial Global Config. Register */
|
||||
unsigned char reserved_D4[12]; /**< \brief D4, \internal Reserved */
|
||||
Ifx_DSADC_EVFLAG EVFLAG; /**< \brief E0, Event Flag Register */
|
||||
Ifx_DSADC_EVFLAGCLR EVFLAGCLR; /**< \brief E4, Event Flag Clear Register */
|
||||
unsigned char reserved_E8[24]; /**< \brief E8, \internal Reserved */
|
||||
Ifx_DSADC_CH CH[4]; /**< \brief 100, Channel objects */
|
||||
unsigned char reserved_500[2816]; /**< \brief 500, \internal Reserved */
|
||||
} Ifx_DSADC;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXDSADC_REGDEF_H */
|
||||
@@ -0,0 +1,621 @@
|
||||
/**
|
||||
* \file IfxEbcu_bf.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC2XXED_TS_V1.0.R2
|
||||
* Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu_BitfieldsMask Bitfields mask and offset
|
||||
* \ingroup IfxLld_Ebcu
|
||||
*
|
||||
*/
|
||||
#ifndef IFXEBCU_BF_H
|
||||
#define IFXEBCU_BF_H 1
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ebcu_BitfieldsMask
|
||||
* \{ */
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN0 */
|
||||
#define IFX_EBCU_ACCEN0_EN0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN0 */
|
||||
#define IFX_EBCU_ACCEN0_EN0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN0 */
|
||||
#define IFX_EBCU_ACCEN0_EN0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN10 */
|
||||
#define IFX_EBCU_ACCEN0_EN10_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN10 */
|
||||
#define IFX_EBCU_ACCEN0_EN10_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN10 */
|
||||
#define IFX_EBCU_ACCEN0_EN10_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN11 */
|
||||
#define IFX_EBCU_ACCEN0_EN11_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN11 */
|
||||
#define IFX_EBCU_ACCEN0_EN11_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN11 */
|
||||
#define IFX_EBCU_ACCEN0_EN11_OFF (11u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN12 */
|
||||
#define IFX_EBCU_ACCEN0_EN12_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN12 */
|
||||
#define IFX_EBCU_ACCEN0_EN12_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN12 */
|
||||
#define IFX_EBCU_ACCEN0_EN12_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN13 */
|
||||
#define IFX_EBCU_ACCEN0_EN13_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN13 */
|
||||
#define IFX_EBCU_ACCEN0_EN13_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN13 */
|
||||
#define IFX_EBCU_ACCEN0_EN13_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN14 */
|
||||
#define IFX_EBCU_ACCEN0_EN14_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN14 */
|
||||
#define IFX_EBCU_ACCEN0_EN14_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN14 */
|
||||
#define IFX_EBCU_ACCEN0_EN14_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN15 */
|
||||
#define IFX_EBCU_ACCEN0_EN15_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN15 */
|
||||
#define IFX_EBCU_ACCEN0_EN15_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN15 */
|
||||
#define IFX_EBCU_ACCEN0_EN15_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN16 */
|
||||
#define IFX_EBCU_ACCEN0_EN16_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN16 */
|
||||
#define IFX_EBCU_ACCEN0_EN16_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN16 */
|
||||
#define IFX_EBCU_ACCEN0_EN16_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN17 */
|
||||
#define IFX_EBCU_ACCEN0_EN17_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN17 */
|
||||
#define IFX_EBCU_ACCEN0_EN17_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN17 */
|
||||
#define IFX_EBCU_ACCEN0_EN17_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN18 */
|
||||
#define IFX_EBCU_ACCEN0_EN18_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN18 */
|
||||
#define IFX_EBCU_ACCEN0_EN18_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN18 */
|
||||
#define IFX_EBCU_ACCEN0_EN18_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN19 */
|
||||
#define IFX_EBCU_ACCEN0_EN19_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN19 */
|
||||
#define IFX_EBCU_ACCEN0_EN19_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN19 */
|
||||
#define IFX_EBCU_ACCEN0_EN19_OFF (19u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN1 */
|
||||
#define IFX_EBCU_ACCEN0_EN1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN1 */
|
||||
#define IFX_EBCU_ACCEN0_EN1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN1 */
|
||||
#define IFX_EBCU_ACCEN0_EN1_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN20 */
|
||||
#define IFX_EBCU_ACCEN0_EN20_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN20 */
|
||||
#define IFX_EBCU_ACCEN0_EN20_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN20 */
|
||||
#define IFX_EBCU_ACCEN0_EN20_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN21 */
|
||||
#define IFX_EBCU_ACCEN0_EN21_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN21 */
|
||||
#define IFX_EBCU_ACCEN0_EN21_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN21 */
|
||||
#define IFX_EBCU_ACCEN0_EN21_OFF (21u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN22 */
|
||||
#define IFX_EBCU_ACCEN0_EN22_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN22 */
|
||||
#define IFX_EBCU_ACCEN0_EN22_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN22 */
|
||||
#define IFX_EBCU_ACCEN0_EN22_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN23 */
|
||||
#define IFX_EBCU_ACCEN0_EN23_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN23 */
|
||||
#define IFX_EBCU_ACCEN0_EN23_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN23 */
|
||||
#define IFX_EBCU_ACCEN0_EN23_OFF (23u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN24 */
|
||||
#define IFX_EBCU_ACCEN0_EN24_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN24 */
|
||||
#define IFX_EBCU_ACCEN0_EN24_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN24 */
|
||||
#define IFX_EBCU_ACCEN0_EN24_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN25 */
|
||||
#define IFX_EBCU_ACCEN0_EN25_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN25 */
|
||||
#define IFX_EBCU_ACCEN0_EN25_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN25 */
|
||||
#define IFX_EBCU_ACCEN0_EN25_OFF (25u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN26 */
|
||||
#define IFX_EBCU_ACCEN0_EN26_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN26 */
|
||||
#define IFX_EBCU_ACCEN0_EN26_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN26 */
|
||||
#define IFX_EBCU_ACCEN0_EN26_OFF (26u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN27 */
|
||||
#define IFX_EBCU_ACCEN0_EN27_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN27 */
|
||||
#define IFX_EBCU_ACCEN0_EN27_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN27 */
|
||||
#define IFX_EBCU_ACCEN0_EN27_OFF (27u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN28 */
|
||||
#define IFX_EBCU_ACCEN0_EN28_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN28 */
|
||||
#define IFX_EBCU_ACCEN0_EN28_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN28 */
|
||||
#define IFX_EBCU_ACCEN0_EN28_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN29 */
|
||||
#define IFX_EBCU_ACCEN0_EN29_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN29 */
|
||||
#define IFX_EBCU_ACCEN0_EN29_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN29 */
|
||||
#define IFX_EBCU_ACCEN0_EN29_OFF (29u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN2 */
|
||||
#define IFX_EBCU_ACCEN0_EN2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN2 */
|
||||
#define IFX_EBCU_ACCEN0_EN2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN2 */
|
||||
#define IFX_EBCU_ACCEN0_EN2_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN30 */
|
||||
#define IFX_EBCU_ACCEN0_EN30_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN30 */
|
||||
#define IFX_EBCU_ACCEN0_EN30_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN30 */
|
||||
#define IFX_EBCU_ACCEN0_EN30_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN31 */
|
||||
#define IFX_EBCU_ACCEN0_EN31_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN31 */
|
||||
#define IFX_EBCU_ACCEN0_EN31_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN31 */
|
||||
#define IFX_EBCU_ACCEN0_EN31_OFF (31u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN3 */
|
||||
#define IFX_EBCU_ACCEN0_EN3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN3 */
|
||||
#define IFX_EBCU_ACCEN0_EN3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN3 */
|
||||
#define IFX_EBCU_ACCEN0_EN3_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN4 */
|
||||
#define IFX_EBCU_ACCEN0_EN4_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN4 */
|
||||
#define IFX_EBCU_ACCEN0_EN4_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN4 */
|
||||
#define IFX_EBCU_ACCEN0_EN4_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN5 */
|
||||
#define IFX_EBCU_ACCEN0_EN5_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN5 */
|
||||
#define IFX_EBCU_ACCEN0_EN5_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN5 */
|
||||
#define IFX_EBCU_ACCEN0_EN5_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN6 */
|
||||
#define IFX_EBCU_ACCEN0_EN6_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN6 */
|
||||
#define IFX_EBCU_ACCEN0_EN6_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN6 */
|
||||
#define IFX_EBCU_ACCEN0_EN6_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN7 */
|
||||
#define IFX_EBCU_ACCEN0_EN7_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN7 */
|
||||
#define IFX_EBCU_ACCEN0_EN7_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN7 */
|
||||
#define IFX_EBCU_ACCEN0_EN7_OFF (7u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN8 */
|
||||
#define IFX_EBCU_ACCEN0_EN8_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN8 */
|
||||
#define IFX_EBCU_ACCEN0_EN8_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN8 */
|
||||
#define IFX_EBCU_ACCEN0_EN8_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ACCEN0_Bits.EN9 */
|
||||
#define IFX_EBCU_ACCEN0_EN9_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ACCEN0_Bits.EN9 */
|
||||
#define IFX_EBCU_ACCEN0_EN9_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ACCEN0_Bits.EN9 */
|
||||
#define IFX_EBCU_ACCEN0_EN9_OFF (9u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_CON_Bits.DBG */
|
||||
#define IFX_EBCU_CON_DBG_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_CON_Bits.DBG */
|
||||
#define IFX_EBCU_CON_DBG_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_CON_Bits.DBG */
|
||||
#define IFX_EBCU_CON_DBG_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_CON_Bits.SPC */
|
||||
#define IFX_EBCU_CON_SPC_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_CON_Bits.SPC */
|
||||
#define IFX_EBCU_CON_SPC_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_CON_Bits.SPC */
|
||||
#define IFX_EBCU_CON_SPC_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_CON_Bits.TOUT */
|
||||
#define IFX_EBCU_CON_TOUT_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_CON_Bits.TOUT */
|
||||
#define IFX_EBCU_CON_TOUT_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_CON_Bits.TOUT */
|
||||
#define IFX_EBCU_CON_TOUT_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_EADD_Bits.FPIADR */
|
||||
#define IFX_EBCU_EADD_FPIADR_LEN (32u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_EADD_Bits.FPIADR */
|
||||
#define IFX_EBCU_EADD_FPIADR_MSK (0xffffffffu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_EADD_Bits.FPIADR */
|
||||
#define IFX_EBCU_EADD_FPIADR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.ABT */
|
||||
#define IFX_EBCU_ECON_ABT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.ABT */
|
||||
#define IFX_EBCU_ECON_ABT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.ABT */
|
||||
#define IFX_EBCU_ECON_ABT_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.ACK */
|
||||
#define IFX_EBCU_ECON_ACK_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.ACK */
|
||||
#define IFX_EBCU_ECON_ACK_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.ACK */
|
||||
#define IFX_EBCU_ECON_ACK_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.ERRCNT */
|
||||
#define IFX_EBCU_ECON_ERRCNT_LEN (14u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.ERRCNT */
|
||||
#define IFX_EBCU_ECON_ERRCNT_MSK (0x3fffu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.ERRCNT */
|
||||
#define IFX_EBCU_ECON_ERRCNT_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.OPC */
|
||||
#define IFX_EBCU_ECON_OPC_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.OPC */
|
||||
#define IFX_EBCU_ECON_OPC_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.OPC */
|
||||
#define IFX_EBCU_ECON_OPC_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.RDN */
|
||||
#define IFX_EBCU_ECON_RDN_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.RDN */
|
||||
#define IFX_EBCU_ECON_RDN_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.RDN */
|
||||
#define IFX_EBCU_ECON_RDN_OFF (21u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.RDY */
|
||||
#define IFX_EBCU_ECON_RDY_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.RDY */
|
||||
#define IFX_EBCU_ECON_RDY_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.RDY */
|
||||
#define IFX_EBCU_ECON_RDY_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.SVM */
|
||||
#define IFX_EBCU_ECON_SVM_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.SVM */
|
||||
#define IFX_EBCU_ECON_SVM_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.SVM */
|
||||
#define IFX_EBCU_ECON_SVM_OFF (19u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.TAG */
|
||||
#define IFX_EBCU_ECON_TAG_LEN (6u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.TAG */
|
||||
#define IFX_EBCU_ECON_TAG_MSK (0x3fu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.TAG */
|
||||
#define IFX_EBCU_ECON_TAG_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.TOUT */
|
||||
#define IFX_EBCU_ECON_TOUT_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.TOUT */
|
||||
#define IFX_EBCU_ECON_TOUT_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.TOUT */
|
||||
#define IFX_EBCU_ECON_TOUT_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ECON_Bits.WRN */
|
||||
#define IFX_EBCU_ECON_WRN_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ECON_Bits.WRN */
|
||||
#define IFX_EBCU_ECON_WRN_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ECON_Bits.WRN */
|
||||
#define IFX_EBCU_ECON_WRN_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_EDAT_Bits.FPIDAT */
|
||||
#define IFX_EBCU_EDAT_FPIDAT_LEN (32u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_EDAT_Bits.FPIDAT */
|
||||
#define IFX_EBCU_EDAT_FPIDAT_MSK (0xffffffffu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_EDAT_Bits.FPIDAT */
|
||||
#define IFX_EBCU_EDAT_FPIDAT_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ID_Bits.MOD_REV */
|
||||
#define IFX_EBCU_ID_MOD_REV_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ID_Bits.MOD_REV */
|
||||
#define IFX_EBCU_ID_MOD_REV_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ID_Bits.MOD_REV */
|
||||
#define IFX_EBCU_ID_MOD_REV_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_ID_Bits.MODNUMBER */
|
||||
#define IFX_EBCU_ID_MODNUMBER_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_ID_Bits.MODNUMBER */
|
||||
#define IFX_EBCU_ID_MODNUMBER_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_ID_Bits.MODNUMBER */
|
||||
#define IFX_EBCU_ID_MODNUMBER_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER10 */
|
||||
#define IFX_EBCU_PRIOH_MASTER10_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER10 */
|
||||
#define IFX_EBCU_PRIOH_MASTER10_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER10 */
|
||||
#define IFX_EBCU_PRIOH_MASTER10_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER11 */
|
||||
#define IFX_EBCU_PRIOH_MASTER11_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER11 */
|
||||
#define IFX_EBCU_PRIOH_MASTER11_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER11 */
|
||||
#define IFX_EBCU_PRIOH_MASTER11_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER12 */
|
||||
#define IFX_EBCU_PRIOH_MASTER12_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER12 */
|
||||
#define IFX_EBCU_PRIOH_MASTER12_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER12 */
|
||||
#define IFX_EBCU_PRIOH_MASTER12_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER13 */
|
||||
#define IFX_EBCU_PRIOH_MASTER13_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER13 */
|
||||
#define IFX_EBCU_PRIOH_MASTER13_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER13 */
|
||||
#define IFX_EBCU_PRIOH_MASTER13_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER14 */
|
||||
#define IFX_EBCU_PRIOH_MASTER14_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER14 */
|
||||
#define IFX_EBCU_PRIOH_MASTER14_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER14 */
|
||||
#define IFX_EBCU_PRIOH_MASTER14_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER15 */
|
||||
#define IFX_EBCU_PRIOH_MASTER15_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER15 */
|
||||
#define IFX_EBCU_PRIOH_MASTER15_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER15 */
|
||||
#define IFX_EBCU_PRIOH_MASTER15_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER8 */
|
||||
#define IFX_EBCU_PRIOH_MASTER8_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER8 */
|
||||
#define IFX_EBCU_PRIOH_MASTER8_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER8 */
|
||||
#define IFX_EBCU_PRIOH_MASTER8_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOH_Bits.MASTER9 */
|
||||
#define IFX_EBCU_PRIOH_MASTER9_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOH_Bits.MASTER9 */
|
||||
#define IFX_EBCU_PRIOH_MASTER9_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOH_Bits.MASTER9 */
|
||||
#define IFX_EBCU_PRIOH_MASTER9_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER0 */
|
||||
#define IFX_EBCU_PRIOL_MASTER0_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER0 */
|
||||
#define IFX_EBCU_PRIOL_MASTER0_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER0 */
|
||||
#define IFX_EBCU_PRIOL_MASTER0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER1 */
|
||||
#define IFX_EBCU_PRIOL_MASTER1_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER1 */
|
||||
#define IFX_EBCU_PRIOL_MASTER1_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER1 */
|
||||
#define IFX_EBCU_PRIOL_MASTER1_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER2 */
|
||||
#define IFX_EBCU_PRIOL_MASTER2_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER2 */
|
||||
#define IFX_EBCU_PRIOL_MASTER2_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER2 */
|
||||
#define IFX_EBCU_PRIOL_MASTER2_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER3 */
|
||||
#define IFX_EBCU_PRIOL_MASTER3_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER3 */
|
||||
#define IFX_EBCU_PRIOL_MASTER3_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER3 */
|
||||
#define IFX_EBCU_PRIOL_MASTER3_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER4 */
|
||||
#define IFX_EBCU_PRIOL_MASTER4_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER4 */
|
||||
#define IFX_EBCU_PRIOL_MASTER4_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER4 */
|
||||
#define IFX_EBCU_PRIOL_MASTER4_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER5 */
|
||||
#define IFX_EBCU_PRIOL_MASTER5_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER5 */
|
||||
#define IFX_EBCU_PRIOL_MASTER5_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER5 */
|
||||
#define IFX_EBCU_PRIOL_MASTER5_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER6 */
|
||||
#define IFX_EBCU_PRIOL_MASTER6_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER6 */
|
||||
#define IFX_EBCU_PRIOL_MASTER6_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER6 */
|
||||
#define IFX_EBCU_PRIOL_MASTER6_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_EBCU_PRIOL_Bits.MASTER7 */
|
||||
#define IFX_EBCU_PRIOL_MASTER7_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EBCU_PRIOL_Bits.MASTER7 */
|
||||
#define IFX_EBCU_PRIOL_MASTER7_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EBCU_PRIOL_Bits.MASTER7 */
|
||||
#define IFX_EBCU_PRIOL_MASTER7_OFF (28u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXEBCU_BF_H */
|
||||
@@ -0,0 +1,123 @@
|
||||
/**
|
||||
* \file IfxEbcu_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC2XXED_TS_V1.0.R2
|
||||
* Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu_Cfg Ebcu address
|
||||
* \ingroup IfxLld_Ebcu
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Ebcu_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu_Cfg_Ebcu0 2-EBCU0
|
||||
* \ingroup IfxLld_Ebcu_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXEBCU_REG_H
|
||||
#define IFXEBCU_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxEbcu_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ebcu_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief EBCU object */
|
||||
#define MODULE_EBCU0 /*lint --e(923)*/ (*(Ifx_EBCU*)0xF90E0100u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ebcu_Cfg_Ebcu0
|
||||
* \{ */
|
||||
|
||||
/** \brief FC, Access Enable Register 0 */
|
||||
#define EBCU0_ACCEN0 /*lint --e(923)*/ (*(volatile Ifx_EBCU_ACCEN0*)0xF90E01FCu)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_ACCEN0.
|
||||
* To use register names with standard convension, please use EBCU0_ACCEN0.
|
||||
*/
|
||||
#define EBCU_ACCEN0 (EBCU0_ACCEN0)
|
||||
|
||||
/** \brief F8, Access Enable Register 1 */
|
||||
#define EBCU0_ACCEN1 /*lint --e(923)*/ (*(volatile Ifx_EBCU_ACCEN1*)0xF90E01F8u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_ACCEN1.
|
||||
* To use register names with standard convension, please use EBCU0_ACCEN1.
|
||||
*/
|
||||
#define EBCU_ACCEN1 (EBCU0_ACCEN1)
|
||||
|
||||
/** \brief 10, EBCU Control Register */
|
||||
#define EBCU0_CON /*lint --e(923)*/ (*(volatile Ifx_EBCU_CON*)0xF90E0110u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_CON.
|
||||
* To use register names with standard convension, please use EBCU0_CON.
|
||||
*/
|
||||
#define EBCU_CON (EBCU0_CON)
|
||||
|
||||
/** \brief 24, Error Address Capture Register */
|
||||
#define EBCU0_EADD /*lint --e(923)*/ (*(volatile Ifx_EBCU_EADD*)0xF90E0124u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_EADD.
|
||||
* To use register names with standard convension, please use EBCU0_EADD.
|
||||
*/
|
||||
#define EBCU_EADD (EBCU0_EADD)
|
||||
|
||||
/** \brief 20, Error Control Capture Register */
|
||||
#define EBCU0_ECON /*lint --e(923)*/ (*(volatile Ifx_EBCU_ECON*)0xF90E0120u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_ECON.
|
||||
* To use register names with standard convension, please use EBCU0_ECON.
|
||||
*/
|
||||
#define EBCU_ECON (EBCU0_ECON)
|
||||
|
||||
/** \brief 28, Error Data Capture Register */
|
||||
#define EBCU0_EDAT /*lint --e(923)*/ (*(volatile Ifx_EBCU_EDAT*)0xF90E0128u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_EDAT.
|
||||
* To use register names with standard convension, please use EBCU0_EDAT.
|
||||
*/
|
||||
#define EBCU_EDAT (EBCU0_EDAT)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define EBCU0_ID /*lint --e(923)*/ (*(volatile Ifx_EBCU_ID*)0xF90E0108u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_ID.
|
||||
* To use register names with standard convension, please use EBCU0_ID.
|
||||
*/
|
||||
#define EBCU_ID (EBCU0_ID)
|
||||
|
||||
/** \brief 14, Arbiter Priority Register */
|
||||
#define EBCU0_PRIOH /*lint --e(923)*/ (*(volatile Ifx_EBCU_PRIOH*)0xF90E0114u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_PRIOH.
|
||||
* To use register names with standard convension, please use EBCU0_PRIOH.
|
||||
*/
|
||||
#define EBCU_PRIOH (EBCU0_PRIOH)
|
||||
|
||||
/** \brief 18, Arbiter Priority Register */
|
||||
#define EBCU0_PRIOL /*lint --e(923)*/ (*(volatile Ifx_EBCU_PRIOL*)0xF90E0118u)
|
||||
|
||||
/** Alias (User Manual Name) for EBCU0_PRIOL.
|
||||
* To use register names with standard convension, please use EBCU0_PRIOL.
|
||||
*/
|
||||
#define EBCU_PRIOL (EBCU0_PRIOL)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXEBCU_REG_H */
|
||||
@@ -0,0 +1,264 @@
|
||||
/**
|
||||
* \file IfxEbcu_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC2XXED_TS_V1.0.R2
|
||||
* Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu Ebcu
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Ebcu
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu_union Union
|
||||
* \ingroup IfxLld_Ebcu
|
||||
*
|
||||
* \defgroup IfxLld_Ebcu_struct Struct
|
||||
* \ingroup IfxLld_Ebcu
|
||||
*
|
||||
*/
|
||||
#ifndef IFXEBCU_REGDEF_H
|
||||
#define IFXEBCU_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ebcu_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef struct _Ifx_EBCU_ACCEN0_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit EN0:1; /**< \brief [0:0] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN1:1; /**< \brief [1:1] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN2:1; /**< \brief [2:2] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN3:1; /**< \brief [3:3] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN4:1; /**< \brief [4:4] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN5:1; /**< \brief [5:5] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN6:1; /**< \brief [6:6] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN7:1; /**< \brief [7:7] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN8:1; /**< \brief [8:8] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN9:1; /**< \brief [9:9] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN10:1; /**< \brief [10:10] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN11:1; /**< \brief [11:11] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN12:1; /**< \brief [12:12] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN13:1; /**< \brief [13:13] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN14:1; /**< \brief [14:14] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN15:1; /**< \brief [15:15] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN16:1; /**< \brief [16:16] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN17:1; /**< \brief [17:17] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN18:1; /**< \brief [18:18] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN19:1; /**< \brief [19:19] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN20:1; /**< \brief [20:20] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN21:1; /**< \brief [21:21] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN22:1; /**< \brief [22:22] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN23:1; /**< \brief [23:23] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN24:1; /**< \brief [24:24] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN25:1; /**< \brief [25:25] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN26:1; /**< \brief [26:26] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN27:1; /**< \brief [27:27] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN28:1; /**< \brief [28:28] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN29:1; /**< \brief [29:29] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN30:1; /**< \brief [30:30] Access Enable for Master TAG ID x (rw) */
|
||||
Ifx_Strict_32Bit EN31:1; /**< \brief [31:31] Access Enable for Master TAG ID x (rw) */
|
||||
} Ifx_EBCU_ACCEN0_Bits;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef struct _Ifx_EBCU_ACCEN1_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit reserved_0:32; /**< \brief \internal Reserved */
|
||||
} Ifx_EBCU_ACCEN1_Bits;
|
||||
|
||||
/** \brief EBCU Control Register */
|
||||
typedef struct _Ifx_EBCU_CON_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit TOUT:16; /**< \brief [15:0] Bus Time-Out Value (rw) */
|
||||
Ifx_Strict_32Bit DBG:1; /**< \brief [16:16] Debug Trace Enable (rw) */
|
||||
Ifx_Strict_32Bit reserved_17:7; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit SPC:8; /**< \brief [31:24] Starvation Period Control (rw) */
|
||||
} Ifx_EBCU_CON_Bits;
|
||||
|
||||
/** \brief Error Address Capture Register */
|
||||
typedef struct _Ifx_EBCU_EADD_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit FPIADR:32; /**< \brief [31:0] Captured FPI Bus Address (rwh) */
|
||||
} Ifx_EBCU_EADD_Bits;
|
||||
|
||||
/** \brief Error Control Capture Register */
|
||||
typedef struct _Ifx_EBCU_ECON_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit ERRCNT:14; /**< \brief [13:0] FPI Bus Error Counter (rwh) */
|
||||
Ifx_Strict_32Bit TOUT:1; /**< \brief [14:14] State of FPI Bus Time-Out Signal (rwh) */
|
||||
Ifx_Strict_32Bit RDY:1; /**< \brief [15:15] State of FPI Bus Ready Signal (rwh) */
|
||||
Ifx_Strict_32Bit ABT:1; /**< \brief [16:16] State of FPI Bus Abort Signal (rwh) */
|
||||
Ifx_Strict_32Bit ACK:2; /**< \brief [18:17] State of FPI Bus Acknowledge Signals (rwh) */
|
||||
Ifx_Strict_32Bit SVM:1; /**< \brief [19:19] State of FPI Bus Supervisor Mode Signal (rwh) */
|
||||
Ifx_Strict_32Bit WRN:1; /**< \brief [20:20] State of FPI Bus Write Signal (rwh) */
|
||||
Ifx_Strict_32Bit RDN:1; /**< \brief [21:21] State of FPI Bus Read Signal (rwh) */
|
||||
Ifx_Strict_32Bit TAG:6; /**< \brief [27:22] FPI Bus Master Tag Number Signals (rwh) */
|
||||
Ifx_Strict_32Bit OPC:4; /**< \brief [31:28] FPI Bus Operation Code Signals (rwh) */
|
||||
} Ifx_EBCU_ECON_Bits;
|
||||
|
||||
/** \brief Error Data Capture Register */
|
||||
typedef struct _Ifx_EBCU_EDAT_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit FPIDAT:32; /**< \brief [31:0] Captured FPI Bus Address (rwh) */
|
||||
} Ifx_EBCU_EDAT_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_EBCU_ID_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit MOD_REV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
Ifx_Strict_32Bit MODNUMBER:8; /**< \brief [15:8] Module Number Value (r) */
|
||||
Ifx_Strict_32Bit reserved_16:16; /**< \brief \internal Reserved */
|
||||
} Ifx_EBCU_ID_Bits;
|
||||
|
||||
/** \brief Arbiter Priority Register */
|
||||
typedef struct _Ifx_EBCU_PRIOH_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit MASTER8:4; /**< \brief [3:0] Master 8 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER9:4; /**< \brief [7:4] Master 9 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER10:4; /**< \brief [11:8] Master 10 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER11:4; /**< \brief [15:12] Master 11 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER12:4; /**< \brief [19:16] Master 12 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER13:4; /**< \brief [23:20] Master 13 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER14:4; /**< \brief [27:24] Master 14 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER15:4; /**< \brief [31:28] Master 15 Priority (rw) */
|
||||
} Ifx_EBCU_PRIOH_Bits;
|
||||
|
||||
/** \brief Arbiter Priority Register */
|
||||
typedef struct _Ifx_EBCU_PRIOL_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit MASTER0:4; /**< \brief [3:0] Master 0 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER1:4; /**< \brief [7:4] Master 1 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER2:4; /**< \brief [11:8] Master 2 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER3:4; /**< \brief [15:12] Master 3 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER4:4; /**< \brief [19:16] Master 4 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER5:4; /**< \brief [23:20] Master 5 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER6:4; /**< \brief [27:24] Master 6 Priority (rw) */
|
||||
Ifx_Strict_32Bit MASTER7:4; /**< \brief [31:28] Master 7 Priority (rw) */
|
||||
} Ifx_EBCU_PRIOL_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ebcu_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Access Enable Register 0 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_ACCEN0_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_ACCEN0;
|
||||
|
||||
/** \brief Access Enable Register 1 */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_ACCEN1_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_ACCEN1;
|
||||
|
||||
/** \brief EBCU Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_CON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_CON;
|
||||
|
||||
/** \brief Error Address Capture Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_EADD_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_EADD;
|
||||
|
||||
/** \brief Error Control Capture Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_ECON_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_ECON;
|
||||
|
||||
/** \brief Error Data Capture Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_EDAT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_EDAT;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_ID;
|
||||
|
||||
/** \brief Arbiter Priority Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_PRIOH_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_PRIOH;
|
||||
|
||||
/** \brief Arbiter Priority Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EBCU_PRIOL_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EBCU_PRIOL;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Ebcu_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief EBCU object */
|
||||
typedef volatile struct _Ifx_EBCU
|
||||
{
|
||||
unsigned char reserved_0[8]; /**< \brief 0, \internal Reserved */
|
||||
Ifx_EBCU_ID ID; /**< \brief 8, Module Identification Register */
|
||||
unsigned char reserved_C[4]; /**< \brief C, \internal Reserved */
|
||||
Ifx_EBCU_CON CON; /**< \brief 10, EBCU Control Register */
|
||||
Ifx_EBCU_PRIOH PRIOH; /**< \brief 14, Arbiter Priority Register */
|
||||
Ifx_EBCU_PRIOL PRIOL; /**< \brief 18, Arbiter Priority Register */
|
||||
unsigned char reserved_1C[4]; /**< \brief 1C, \internal Reserved */
|
||||
Ifx_EBCU_ECON ECON; /**< \brief 20, Error Control Capture Register */
|
||||
Ifx_EBCU_EADD EADD; /**< \brief 24, Error Address Capture Register */
|
||||
Ifx_EBCU_EDAT EDAT; /**< \brief 28, Error Data Capture Register */
|
||||
unsigned char reserved_2C[204]; /**< \brief 2C, \internal Reserved */
|
||||
Ifx_EBCU_ACCEN1 ACCEN1; /**< \brief F8, Access Enable Register 1 */
|
||||
Ifx_EBCU_ACCEN0 ACCEN0; /**< \brief FC, Access Enable Register 0 */
|
||||
} Ifx_EBCU;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXEBCU_REGDEF_H */
|
||||
@@ -0,0 +1,954 @@
|
||||
/**
|
||||
* \file IfxEmem_bf.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC2XXED_TS_V1.0.R2
|
||||
* Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Emem_BitfieldsMask Bitfields mask and offset
|
||||
* \ingroup IfxLld_Emem
|
||||
*
|
||||
*/
|
||||
#ifndef IFXEMEM_BF_H
|
||||
#define IFXEMEM_BF_H 1
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Emem_BitfieldsMask
|
||||
* \{ */
|
||||
|
||||
/** \brief Length for Ifx_EMEM_CLC_Bits.DISR */
|
||||
#define IFX_EMEM_CLC_DISR_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_CLC_Bits.DISR */
|
||||
#define IFX_EMEM_CLC_DISR_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_CLC_Bits.DISR */
|
||||
#define IFX_EMEM_CLC_DISR_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_CLC_Bits.DISS */
|
||||
#define IFX_EMEM_CLC_DISS_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_CLC_Bits.DISS */
|
||||
#define IFX_EMEM_CLC_DISS_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_CLC_Bits.DISS */
|
||||
#define IFX_EMEM_CLC_DISS_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_ID_Bits.MOD_REV */
|
||||
#define IFX_EMEM_ID_MOD_REV_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_ID_Bits.MOD_REV */
|
||||
#define IFX_EMEM_ID_MOD_REV_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_ID_Bits.MOD_REV */
|
||||
#define IFX_EMEM_ID_MOD_REV_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_ID_Bits.MOD_TYPE */
|
||||
#define IFX_EMEM_ID_MOD_TYPE_LEN (8u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_ID_Bits.MOD_TYPE */
|
||||
#define IFX_EMEM_ID_MOD_TYPE_MSK (0xffu)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_ID_Bits.MOD_TYPE */
|
||||
#define IFX_EMEM_ID_MOD_TYPE_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_ID_Bits.MODNUMBER */
|
||||
#define IFX_EMEM_ID_MODNUMBER_LEN (16u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_ID_Bits.MODNUMBER */
|
||||
#define IFX_EMEM_ID_MODNUMBER_MSK (0xffffu)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_ID_Bits.MODNUMBER */
|
||||
#define IFX_EMEM_ID_MODNUMBER_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGEN */
|
||||
#define IFX_EMEM_SBRCTR_ACGEN_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGEN */
|
||||
#define IFX_EMEM_SBRCTR_ACGEN_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGEN */
|
||||
#define IFX_EMEM_SBRCTR_ACGEN_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST0_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST10 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST10_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST10 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST10_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST10 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST10_OFF (26u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST11 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST11_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST11 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST11_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST11 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST11_OFF (27u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST12 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST12_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST12 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST12_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST12 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST12_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST13 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST13_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST13 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST13_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST13 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST13_OFF (29u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST14 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST14_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST14 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST14_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST14 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST14_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST15 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST15_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST15 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST15_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST15 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST15_OFF (31u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST1 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST1 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST1 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST1_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST2 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST2 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST2 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST2_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST3 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST3 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST3 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST3_OFF (19u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST4 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST4_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST4 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST4_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST4 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST4_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST5 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST5_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST5 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST5_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST5 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST5_OFF (21u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST6 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST6_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST6 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST6_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST6 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST6_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST7 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST7_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST7 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST7_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST7 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST7_OFF (23u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST8 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST8_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST8 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST8_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST8 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST8_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGST9 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST9_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGST9 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST9_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGST9 */
|
||||
#define IFX_EMEM_SBRCTR_ACGST9_OFF (25u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGSXCM0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXCM0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGSXCM0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXCM0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGSXCM0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXCM0_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGSXTM0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXTM0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGSXTM0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXTM0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGSXTM0 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXTM0_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.ACGSXTM1 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXTM1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.ACGSXTM1 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXTM1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.ACGSXTM1 */
|
||||
#define IFX_EMEM_SBRCTR_ACGSXTM1_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.STBLOCK */
|
||||
#define IFX_EMEM_SBRCTR_STBLOCK_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.STBLOCK */
|
||||
#define IFX_EMEM_SBRCTR_STBLOCK_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.STBLOCK */
|
||||
#define IFX_EMEM_SBRCTR_STBLOCK_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.STBSLK */
|
||||
#define IFX_EMEM_SBRCTR_STBSLK_LEN (4u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.STBSLK */
|
||||
#define IFX_EMEM_SBRCTR_STBSLK_MSK (0xfu)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.STBSLK */
|
||||
#define IFX_EMEM_SBRCTR_STBSLK_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_SBRCTR_Bits.STBULK */
|
||||
#define IFX_EMEM_SBRCTR_STBULK_LEN (3u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_SBRCTR_Bits.STBULK */
|
||||
#define IFX_EMEM_SBRCTR_STBULK_MSK (0x7u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_SBRCTR_Bits.STBULK */
|
||||
#define IFX_EMEM_SBRCTR_STBULK_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T0 */
|
||||
#define IFX_EMEM_TILECC_T0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T0 */
|
||||
#define IFX_EMEM_TILECC_T0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T0 */
|
||||
#define IFX_EMEM_TILECC_T0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T10 */
|
||||
#define IFX_EMEM_TILECC_T10_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T10 */
|
||||
#define IFX_EMEM_TILECC_T10_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T10 */
|
||||
#define IFX_EMEM_TILECC_T10_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T11 */
|
||||
#define IFX_EMEM_TILECC_T11_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T11 */
|
||||
#define IFX_EMEM_TILECC_T11_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T11 */
|
||||
#define IFX_EMEM_TILECC_T11_OFF (11u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T12 */
|
||||
#define IFX_EMEM_TILECC_T12_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T12 */
|
||||
#define IFX_EMEM_TILECC_T12_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T12 */
|
||||
#define IFX_EMEM_TILECC_T12_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T13 */
|
||||
#define IFX_EMEM_TILECC_T13_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T13 */
|
||||
#define IFX_EMEM_TILECC_T13_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T13 */
|
||||
#define IFX_EMEM_TILECC_T13_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T14 */
|
||||
#define IFX_EMEM_TILECC_T14_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T14 */
|
||||
#define IFX_EMEM_TILECC_T14_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T14 */
|
||||
#define IFX_EMEM_TILECC_T14_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T15 */
|
||||
#define IFX_EMEM_TILECC_T15_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T15 */
|
||||
#define IFX_EMEM_TILECC_T15_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T15 */
|
||||
#define IFX_EMEM_TILECC_T15_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T1 */
|
||||
#define IFX_EMEM_TILECC_T1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T1 */
|
||||
#define IFX_EMEM_TILECC_T1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T1 */
|
||||
#define IFX_EMEM_TILECC_T1_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T2 */
|
||||
#define IFX_EMEM_TILECC_T2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T2 */
|
||||
#define IFX_EMEM_TILECC_T2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T2 */
|
||||
#define IFX_EMEM_TILECC_T2_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T3 */
|
||||
#define IFX_EMEM_TILECC_T3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T3 */
|
||||
#define IFX_EMEM_TILECC_T3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T3 */
|
||||
#define IFX_EMEM_TILECC_T3_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T4 */
|
||||
#define IFX_EMEM_TILECC_T4_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T4 */
|
||||
#define IFX_EMEM_TILECC_T4_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T4 */
|
||||
#define IFX_EMEM_TILECC_T4_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T5 */
|
||||
#define IFX_EMEM_TILECC_T5_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T5 */
|
||||
#define IFX_EMEM_TILECC_T5_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T5 */
|
||||
#define IFX_EMEM_TILECC_T5_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T6 */
|
||||
#define IFX_EMEM_TILECC_T6_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T6 */
|
||||
#define IFX_EMEM_TILECC_T6_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T6 */
|
||||
#define IFX_EMEM_TILECC_T6_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T7 */
|
||||
#define IFX_EMEM_TILECC_T7_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T7 */
|
||||
#define IFX_EMEM_TILECC_T7_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T7 */
|
||||
#define IFX_EMEM_TILECC_T7_OFF (7u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T8 */
|
||||
#define IFX_EMEM_TILECC_T8_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T8 */
|
||||
#define IFX_EMEM_TILECC_T8_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T8 */
|
||||
#define IFX_EMEM_TILECC_T8_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.T9 */
|
||||
#define IFX_EMEM_TILECC_T9_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.T9 */
|
||||
#define IFX_EMEM_TILECC_T9_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.T9 */
|
||||
#define IFX_EMEM_TILECC_T9_OFF (9u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECC_XTM0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECC_XTM0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECC_XTM0_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECC_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECC_XTM1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECC_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECC_XTM1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECC_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECC_XTM1_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T0 */
|
||||
#define IFX_EMEM_TILECONFIG_T0_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T0 */
|
||||
#define IFX_EMEM_TILECONFIG_T0_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T0 */
|
||||
#define IFX_EMEM_TILECONFIG_T0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T10 */
|
||||
#define IFX_EMEM_TILECONFIG_T10_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T10 */
|
||||
#define IFX_EMEM_TILECONFIG_T10_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T10 */
|
||||
#define IFX_EMEM_TILECONFIG_T10_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T11 */
|
||||
#define IFX_EMEM_TILECONFIG_T11_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T11 */
|
||||
#define IFX_EMEM_TILECONFIG_T11_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T11 */
|
||||
#define IFX_EMEM_TILECONFIG_T11_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T12 */
|
||||
#define IFX_EMEM_TILECONFIG_T12_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T12 */
|
||||
#define IFX_EMEM_TILECONFIG_T12_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T12 */
|
||||
#define IFX_EMEM_TILECONFIG_T12_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T13 */
|
||||
#define IFX_EMEM_TILECONFIG_T13_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T13 */
|
||||
#define IFX_EMEM_TILECONFIG_T13_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T13 */
|
||||
#define IFX_EMEM_TILECONFIG_T13_OFF (26u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T14 */
|
||||
#define IFX_EMEM_TILECONFIG_T14_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T14 */
|
||||
#define IFX_EMEM_TILECONFIG_T14_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T14 */
|
||||
#define IFX_EMEM_TILECONFIG_T14_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T15 */
|
||||
#define IFX_EMEM_TILECONFIG_T15_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T15 */
|
||||
#define IFX_EMEM_TILECONFIG_T15_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T15 */
|
||||
#define IFX_EMEM_TILECONFIG_T15_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T1 */
|
||||
#define IFX_EMEM_TILECONFIG_T1_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T1 */
|
||||
#define IFX_EMEM_TILECONFIG_T1_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T1 */
|
||||
#define IFX_EMEM_TILECONFIG_T1_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T2 */
|
||||
#define IFX_EMEM_TILECONFIG_T2_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T2 */
|
||||
#define IFX_EMEM_TILECONFIG_T2_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T2 */
|
||||
#define IFX_EMEM_TILECONFIG_T2_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T3 */
|
||||
#define IFX_EMEM_TILECONFIG_T3_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T3 */
|
||||
#define IFX_EMEM_TILECONFIG_T3_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T3 */
|
||||
#define IFX_EMEM_TILECONFIG_T3_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T4 */
|
||||
#define IFX_EMEM_TILECONFIG_T4_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T4 */
|
||||
#define IFX_EMEM_TILECONFIG_T4_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T4 */
|
||||
#define IFX_EMEM_TILECONFIG_T4_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T5 */
|
||||
#define IFX_EMEM_TILECONFIG_T5_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T5 */
|
||||
#define IFX_EMEM_TILECONFIG_T5_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T5 */
|
||||
#define IFX_EMEM_TILECONFIG_T5_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T6 */
|
||||
#define IFX_EMEM_TILECONFIG_T6_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T6 */
|
||||
#define IFX_EMEM_TILECONFIG_T6_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T6 */
|
||||
#define IFX_EMEM_TILECONFIG_T6_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T7 */
|
||||
#define IFX_EMEM_TILECONFIG_T7_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T7 */
|
||||
#define IFX_EMEM_TILECONFIG_T7_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T7 */
|
||||
#define IFX_EMEM_TILECONFIG_T7_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T8 */
|
||||
#define IFX_EMEM_TILECONFIG_T8_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T8 */
|
||||
#define IFX_EMEM_TILECONFIG_T8_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T8 */
|
||||
#define IFX_EMEM_TILECONFIG_T8_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIG_Bits.T9 */
|
||||
#define IFX_EMEM_TILECONFIG_T9_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIG_Bits.T9 */
|
||||
#define IFX_EMEM_TILECONFIG_T9_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIG_Bits.T9 */
|
||||
#define IFX_EMEM_TILECONFIG_T9_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIGXM_Bits.XCM0 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XCM0_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIGXM_Bits.XCM0 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XCM0_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIGXM_Bits.XCM0 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XCM0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIGXM_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XTM0_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIGXM_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XTM0_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIGXM_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XTM0_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECONFIGXM_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XTM1_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECONFIGXM_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XTM1_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECONFIGXM_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECONFIGXM_XTM1_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T0 */
|
||||
#define IFX_EMEM_TILECT_T0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T0 */
|
||||
#define IFX_EMEM_TILECT_T0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T0 */
|
||||
#define IFX_EMEM_TILECT_T0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T10 */
|
||||
#define IFX_EMEM_TILECT_T10_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T10 */
|
||||
#define IFX_EMEM_TILECT_T10_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T10 */
|
||||
#define IFX_EMEM_TILECT_T10_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T11 */
|
||||
#define IFX_EMEM_TILECT_T11_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T11 */
|
||||
#define IFX_EMEM_TILECT_T11_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T11 */
|
||||
#define IFX_EMEM_TILECT_T11_OFF (11u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T12 */
|
||||
#define IFX_EMEM_TILECT_T12_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T12 */
|
||||
#define IFX_EMEM_TILECT_T12_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T12 */
|
||||
#define IFX_EMEM_TILECT_T12_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T13 */
|
||||
#define IFX_EMEM_TILECT_T13_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T13 */
|
||||
#define IFX_EMEM_TILECT_T13_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T13 */
|
||||
#define IFX_EMEM_TILECT_T13_OFF (13u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T14 */
|
||||
#define IFX_EMEM_TILECT_T14_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T14 */
|
||||
#define IFX_EMEM_TILECT_T14_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T14 */
|
||||
#define IFX_EMEM_TILECT_T14_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T15 */
|
||||
#define IFX_EMEM_TILECT_T15_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T15 */
|
||||
#define IFX_EMEM_TILECT_T15_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T15 */
|
||||
#define IFX_EMEM_TILECT_T15_OFF (15u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T1 */
|
||||
#define IFX_EMEM_TILECT_T1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T1 */
|
||||
#define IFX_EMEM_TILECT_T1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T1 */
|
||||
#define IFX_EMEM_TILECT_T1_OFF (1u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T2 */
|
||||
#define IFX_EMEM_TILECT_T2_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T2 */
|
||||
#define IFX_EMEM_TILECT_T2_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T2 */
|
||||
#define IFX_EMEM_TILECT_T2_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T3 */
|
||||
#define IFX_EMEM_TILECT_T3_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T3 */
|
||||
#define IFX_EMEM_TILECT_T3_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T3 */
|
||||
#define IFX_EMEM_TILECT_T3_OFF (3u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T4 */
|
||||
#define IFX_EMEM_TILECT_T4_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T4 */
|
||||
#define IFX_EMEM_TILECT_T4_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T4 */
|
||||
#define IFX_EMEM_TILECT_T4_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T5 */
|
||||
#define IFX_EMEM_TILECT_T5_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T5 */
|
||||
#define IFX_EMEM_TILECT_T5_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T5 */
|
||||
#define IFX_EMEM_TILECT_T5_OFF (5u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T6 */
|
||||
#define IFX_EMEM_TILECT_T6_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T6 */
|
||||
#define IFX_EMEM_TILECT_T6_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T6 */
|
||||
#define IFX_EMEM_TILECT_T6_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T7 */
|
||||
#define IFX_EMEM_TILECT_T7_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T7 */
|
||||
#define IFX_EMEM_TILECT_T7_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T7 */
|
||||
#define IFX_EMEM_TILECT_T7_OFF (7u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T8 */
|
||||
#define IFX_EMEM_TILECT_T8_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T8 */
|
||||
#define IFX_EMEM_TILECT_T8_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T8 */
|
||||
#define IFX_EMEM_TILECT_T8_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.T9 */
|
||||
#define IFX_EMEM_TILECT_T9_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.T9 */
|
||||
#define IFX_EMEM_TILECT_T9_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.T9 */
|
||||
#define IFX_EMEM_TILECT_T9_OFF (9u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECT_XTM0_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECT_XTM0_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILECT_XTM0_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILECT_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECT_XTM1_LEN (1u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILECT_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECT_XTM1_MSK (0x1u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILECT_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILECT_XTM1_OFF (17u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE0 */
|
||||
#define IFX_EMEM_TILESTATE_TILE0_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE0 */
|
||||
#define IFX_EMEM_TILESTATE_TILE0_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE0 */
|
||||
#define IFX_EMEM_TILESTATE_TILE0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE10 */
|
||||
#define IFX_EMEM_TILESTATE_TILE10_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE10 */
|
||||
#define IFX_EMEM_TILESTATE_TILE10_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE10 */
|
||||
#define IFX_EMEM_TILESTATE_TILE10_OFF (20u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE11 */
|
||||
#define IFX_EMEM_TILESTATE_TILE11_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE11 */
|
||||
#define IFX_EMEM_TILESTATE_TILE11_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE11 */
|
||||
#define IFX_EMEM_TILESTATE_TILE11_OFF (22u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE12 */
|
||||
#define IFX_EMEM_TILESTATE_TILE12_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE12 */
|
||||
#define IFX_EMEM_TILESTATE_TILE12_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE12 */
|
||||
#define IFX_EMEM_TILESTATE_TILE12_OFF (24u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE13 */
|
||||
#define IFX_EMEM_TILESTATE_TILE13_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE13 */
|
||||
#define IFX_EMEM_TILESTATE_TILE13_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE13 */
|
||||
#define IFX_EMEM_TILESTATE_TILE13_OFF (26u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE14 */
|
||||
#define IFX_EMEM_TILESTATE_TILE14_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE14 */
|
||||
#define IFX_EMEM_TILESTATE_TILE14_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE14 */
|
||||
#define IFX_EMEM_TILESTATE_TILE14_OFF (28u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE15 */
|
||||
#define IFX_EMEM_TILESTATE_TILE15_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE15 */
|
||||
#define IFX_EMEM_TILESTATE_TILE15_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE15 */
|
||||
#define IFX_EMEM_TILESTATE_TILE15_OFF (30u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE1 */
|
||||
#define IFX_EMEM_TILESTATE_TILE1_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE1 */
|
||||
#define IFX_EMEM_TILESTATE_TILE1_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE1 */
|
||||
#define IFX_EMEM_TILESTATE_TILE1_OFF (2u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE2 */
|
||||
#define IFX_EMEM_TILESTATE_TILE2_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE2 */
|
||||
#define IFX_EMEM_TILESTATE_TILE2_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE2 */
|
||||
#define IFX_EMEM_TILESTATE_TILE2_OFF (4u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE3 */
|
||||
#define IFX_EMEM_TILESTATE_TILE3_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE3 */
|
||||
#define IFX_EMEM_TILESTATE_TILE3_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE3 */
|
||||
#define IFX_EMEM_TILESTATE_TILE3_OFF (6u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE4 */
|
||||
#define IFX_EMEM_TILESTATE_TILE4_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE4 */
|
||||
#define IFX_EMEM_TILESTATE_TILE4_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE4 */
|
||||
#define IFX_EMEM_TILESTATE_TILE4_OFF (8u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE5 */
|
||||
#define IFX_EMEM_TILESTATE_TILE5_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE5 */
|
||||
#define IFX_EMEM_TILESTATE_TILE5_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE5 */
|
||||
#define IFX_EMEM_TILESTATE_TILE5_OFF (10u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE6 */
|
||||
#define IFX_EMEM_TILESTATE_TILE6_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE6 */
|
||||
#define IFX_EMEM_TILESTATE_TILE6_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE6 */
|
||||
#define IFX_EMEM_TILESTATE_TILE6_OFF (12u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE7 */
|
||||
#define IFX_EMEM_TILESTATE_TILE7_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE7 */
|
||||
#define IFX_EMEM_TILESTATE_TILE7_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE7 */
|
||||
#define IFX_EMEM_TILESTATE_TILE7_OFF (14u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE8 */
|
||||
#define IFX_EMEM_TILESTATE_TILE8_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE8 */
|
||||
#define IFX_EMEM_TILESTATE_TILE8_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE8 */
|
||||
#define IFX_EMEM_TILESTATE_TILE8_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATE_Bits.TILE9 */
|
||||
#define IFX_EMEM_TILESTATE_TILE9_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATE_Bits.TILE9 */
|
||||
#define IFX_EMEM_TILESTATE_TILE9_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATE_Bits.TILE9 */
|
||||
#define IFX_EMEM_TILESTATE_TILE9_OFF (18u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATEXM_Bits.XCM0 */
|
||||
#define IFX_EMEM_TILESTATEXM_XCM0_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATEXM_Bits.XCM0 */
|
||||
#define IFX_EMEM_TILESTATEXM_XCM0_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATEXM_Bits.XCM0 */
|
||||
#define IFX_EMEM_TILESTATEXM_XCM0_OFF (0u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATEXM_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILESTATEXM_XTM0_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATEXM_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILESTATEXM_XTM0_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATEXM_Bits.XTM0 */
|
||||
#define IFX_EMEM_TILESTATEXM_XTM0_OFF (16u)
|
||||
|
||||
/** \brief Length for Ifx_EMEM_TILESTATEXM_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILESTATEXM_XTM1_LEN (2u)
|
||||
|
||||
/** \brief Mask for Ifx_EMEM_TILESTATEXM_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILESTATEXM_XTM1_MSK (0x3u)
|
||||
|
||||
/** \brief Offset for Ifx_EMEM_TILESTATEXM_Bits.XTM1 */
|
||||
#define IFX_EMEM_TILESTATEXM_XTM1_OFF (18u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXEMEM_BF_H */
|
||||
@@ -0,0 +1,78 @@
|
||||
/**
|
||||
* \file IfxEmem_reg.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC2XXED_TS_V1.0.R2
|
||||
* Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Emem_Cfg Emem address
|
||||
* \ingroup IfxLld_Emem
|
||||
*
|
||||
* \defgroup IfxLld_Emem_Cfg_BaseAddress Base address
|
||||
* \ingroup IfxLld_Emem_Cfg
|
||||
*
|
||||
* \defgroup IfxLld_Emem_Cfg_Emem 2-EMEM
|
||||
* \ingroup IfxLld_Emem_Cfg
|
||||
*
|
||||
*/
|
||||
#ifndef IFXEMEM_REG_H
|
||||
#define IFXEMEM_REG_H 1
|
||||
/******************************************************************************/
|
||||
#include "IfxEmem_regdef.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Emem_Cfg_BaseAddress
|
||||
* \{ */
|
||||
|
||||
/** \brief EMEM object */
|
||||
#define MODULE_EMEM /*lint --e(923)*/ (*(Ifx_EMEM*)0xF90E6000u)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Emem_Cfg_Emem
|
||||
* \{ */
|
||||
|
||||
/** \brief 0, Clock Control Register */
|
||||
#define EMEM_CLC /*lint --e(923)*/ (*(volatile Ifx_EMEM_CLC*)0xF90E6000u)
|
||||
|
||||
/** \brief 8, Module Identification Register */
|
||||
#define EMEM_ID /*lint --e(923)*/ (*(volatile Ifx_EMEM_ID*)0xF90E6008u)
|
||||
|
||||
/** \brief 34, Standby RAM Control Register */
|
||||
#define EMEM_SBRCTR /*lint --e(923)*/ (*(volatile Ifx_EMEM_SBRCTR*)0xF90E6034u)
|
||||
|
||||
/** \brief 24, Calibration Tile Control Register */
|
||||
#define EMEM_TILECC /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILECC*)0xF90E6024u)
|
||||
|
||||
/** \brief 20, Tile Configuration Register */
|
||||
#define EMEM_TILECONFIG /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILECONFIG*)0xF90E6020u)
|
||||
|
||||
/** \brief 40, Extended Tile Configuration Register */
|
||||
#define EMEM_TILECONFIGXM /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILECONFIGXM*)0xF90E6040u)
|
||||
|
||||
/** \brief 28, Trace Tile Control Register */
|
||||
#define EMEM_TILECT /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILECT*)0xF90E6028u)
|
||||
|
||||
/** \brief 2C, Tile Status Register */
|
||||
#define EMEM_TILESTATE /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILESTATE*)0xF90E602Cu)
|
||||
|
||||
/** \brief 4C, Extended Tile Status Register */
|
||||
#define EMEM_TILESTATEXM /*lint --e(923)*/ (*(volatile Ifx_EMEM_TILESTATEXM*)0xF90E604Cu)
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXEMEM_REG_H */
|
||||
@@ -0,0 +1,309 @@
|
||||
/**
|
||||
* \file IfxEmem_regdef.h
|
||||
* \brief
|
||||
* \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
* Version: TC2XXED_TS_V1.0.R2
|
||||
* Specification: AurixED_TS_V1.0_CPU_VIEW_SFR.xml (Revision: V1.0)
|
||||
* MAY BE CHANGED BY USER [yes/no]: No
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
* \defgroup IfxLld_Emem Emem
|
||||
* \ingroup IfxLld
|
||||
*
|
||||
* \defgroup IfxLld_Emem_Bitfields Bitfields
|
||||
* \ingroup IfxLld_Emem
|
||||
*
|
||||
* \defgroup IfxLld_Emem_union Union
|
||||
* \ingroup IfxLld_Emem
|
||||
*
|
||||
* \defgroup IfxLld_Emem_struct Struct
|
||||
* \ingroup IfxLld_Emem
|
||||
*
|
||||
*/
|
||||
#ifndef IFXEMEM_REGDEF_H
|
||||
#define IFXEMEM_REGDEF_H 1
|
||||
/******************************************************************************/
|
||||
#include "Ifx_TypesReg.h"
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Emem_Bitfields
|
||||
* \{ */
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef struct _Ifx_EMEM_CLC_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit DISR:1; /**< \brief [0:0] Module Disable Request Bit (rw) */
|
||||
Ifx_Strict_32Bit DISS:1; /**< \brief [1:1] Module Disable Status Bit (rh) */
|
||||
Ifx_Strict_32Bit reserved_2:30; /**< \brief \internal Reserved */
|
||||
} Ifx_EMEM_CLC_Bits;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef struct _Ifx_EMEM_ID_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit MOD_REV:8; /**< \brief [7:0] Module Revision Number (r) */
|
||||
Ifx_Strict_32Bit MOD_TYPE:8; /**< \brief [15:8] Module Type (r) */
|
||||
Ifx_Strict_32Bit MODNUMBER:16; /**< \brief [31:16] Module Number Value (r) */
|
||||
} Ifx_EMEM_ID_Bits;
|
||||
|
||||
/** \brief Standby RAM Control Register */
|
||||
typedef struct _Ifx_EMEM_SBRCTR_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit STBLOCK:1; /**< \brief [0:0] Standby Lock Flag (rh) */
|
||||
Ifx_Strict_32Bit STBULK:3; /**< \brief [3:1] Unlock Standby Lock Flag (w) */
|
||||
Ifx_Strict_32Bit STBSLK:4; /**< \brief [7:4] Set Standby Lock Flag (w) */
|
||||
Ifx_Strict_32Bit ACGSXCM0:1; /**< \brief [8:8] Automatic Clock Gating Status of XCM0 (rh) */
|
||||
Ifx_Strict_32Bit reserved_9:3; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit ACGEN:1; /**< \brief [12:12] Automatic Clock Gating Enabling (rw) */
|
||||
Ifx_Strict_32Bit ACGSXTM0:1; /**< \brief [13:13] Automatic Clock Gating Status of XTM0 (rh) */
|
||||
Ifx_Strict_32Bit ACGSXTM1:1; /**< \brief [14:14] Automatic Clock Gating Status of XTM1 (rh) */
|
||||
Ifx_Strict_32Bit reserved_15:1; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit ACGST0:1; /**< \brief [16:16] Automatic Clock Gating Status of Tile 0 (rh) */
|
||||
Ifx_Strict_32Bit ACGST1:1; /**< \brief [17:17] Automatic Clock Gating Status of Tile 1 (rh) */
|
||||
Ifx_Strict_32Bit ACGST2:1; /**< \brief [18:18] Automatic Clock Gating Status of Tile 2 (rh) */
|
||||
Ifx_Strict_32Bit ACGST3:1; /**< \brief [19:19] Automatic Clock Gating Status of Tile 3 (rh) */
|
||||
Ifx_Strict_32Bit ACGST4:1; /**< \brief [20:20] Automatic Clock Gating Status of Tile 4 (rh) */
|
||||
Ifx_Strict_32Bit ACGST5:1; /**< \brief [21:21] Automatic Clock Gating Status of Tile 5 (rh) */
|
||||
Ifx_Strict_32Bit ACGST6:1; /**< \brief [22:22] Automatic Clock Gating Status of Tile 6 (rh) */
|
||||
Ifx_Strict_32Bit ACGST7:1; /**< \brief [23:23] Automatic Clock Gating Status of Tile 7 (rh) */
|
||||
Ifx_Strict_32Bit ACGST8:1; /**< \brief [24:24] Automatic Clock Gating Status of Tile 8 (rh) */
|
||||
Ifx_Strict_32Bit ACGST9:1; /**< \brief [25:25] Automatic Clock Gating Status of Tile 9 (rh) */
|
||||
Ifx_Strict_32Bit ACGST10:1; /**< \brief [26:26] Automatic Clock Gating Status of Tile 10 (rh) */
|
||||
Ifx_Strict_32Bit ACGST11:1; /**< \brief [27:27] Automatic Clock Gating Status of Tile 11 (rh) */
|
||||
Ifx_Strict_32Bit ACGST12:1; /**< \brief [28:28] Automatic Clock Gating Status of Tile 12 (rh) */
|
||||
Ifx_Strict_32Bit ACGST13:1; /**< \brief [29:29] Automatic Clock Gating Status of Tile 13 (rh) */
|
||||
Ifx_Strict_32Bit ACGST14:1; /**< \brief [30:30] Automatic Clock Gating Status of Tile 14 (rh) */
|
||||
Ifx_Strict_32Bit ACGST15:1; /**< \brief [31:31] Automatic Clock Gating Status of Tile 15 (rh) */
|
||||
} Ifx_EMEM_SBRCTR_Bits;
|
||||
|
||||
/** \brief Calibration Tile Control Register */
|
||||
typedef struct _Ifx_EMEM_TILECC_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit T0:1; /**< \brief [0:0] Calibration Tile 0 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T1:1; /**< \brief [1:1] Calibration Tile 1 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T2:1; /**< \brief [2:2] Calibration Tile 2 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T3:1; /**< \brief [3:3] Calibration Tile 3 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T4:1; /**< \brief [4:4] Calibration Tile 4 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T5:1; /**< \brief [5:5] Calibration Tile 5 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T6:1; /**< \brief [6:6] Calibration Tile 6 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T7:1; /**< \brief [7:7] Calibration Tile 7 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T8:1; /**< \brief [8:8] Calibration Tile 8 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T9:1; /**< \brief [9:9] Calibration Tile 9 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T10:1; /**< \brief [10:10] Calibration Tile 10 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T11:1; /**< \brief [11:11] Calibration Tile 11 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T12:1; /**< \brief [12:12] Calibration Tile 12 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T13:1; /**< \brief [13:13] Calibration Tile 13 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T14:1; /**< \brief [14:14] Calibration Tile 14 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T15:1; /**< \brief [15:15] Calibration Tile 15 Control Bit (w) */
|
||||
Ifx_Strict_32Bit XTM0:1; /**< \brief [16:16] Calibration XTM0 Tile Control Bit (w) */
|
||||
Ifx_Strict_32Bit XTM1:1; /**< \brief [17:17] Calibration XTM1 Tile Control Bit (w) */
|
||||
Ifx_Strict_32Bit reserved_18:14; /**< \brief \internal Reserved */
|
||||
} Ifx_EMEM_TILECC_Bits;
|
||||
|
||||
/** \brief Tile Configuration Register */
|
||||
typedef struct _Ifx_EMEM_TILECONFIG_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit T0:2; /**< \brief [1:0] Tile 0 Allocation (w) */
|
||||
Ifx_Strict_32Bit T1:2; /**< \brief [3:2] Tile 1 Allocation (w) */
|
||||
Ifx_Strict_32Bit T2:2; /**< \brief [5:4] Tile 2 Allocation (w) */
|
||||
Ifx_Strict_32Bit T3:2; /**< \brief [7:6] Tile 3 Allocation (w) */
|
||||
Ifx_Strict_32Bit T4:2; /**< \brief [9:8] Tile 4 Allocation (w) */
|
||||
Ifx_Strict_32Bit T5:2; /**< \brief [11:10] Tile 5 Allocation (w) */
|
||||
Ifx_Strict_32Bit T6:2; /**< \brief [13:12] Tile 6 Allocation (w) */
|
||||
Ifx_Strict_32Bit T7:2; /**< \brief [15:14] Tile 7 Allocation (w) */
|
||||
Ifx_Strict_32Bit T8:2; /**< \brief [17:16] Tile 8 Allocation (w) */
|
||||
Ifx_Strict_32Bit T9:2; /**< \brief [19:18] Tile 9 Allocation (w) */
|
||||
Ifx_Strict_32Bit T10:2; /**< \brief [21:20] Tile 10 Allocation (w) */
|
||||
Ifx_Strict_32Bit T11:2; /**< \brief [23:22] Tile 11 Allocation (w) */
|
||||
Ifx_Strict_32Bit T12:2; /**< \brief [25:24] Tile 12 Allocation (w) */
|
||||
Ifx_Strict_32Bit T13:2; /**< \brief [27:26] Tile 13 Allocation (w) */
|
||||
Ifx_Strict_32Bit T14:2; /**< \brief [29:28] Tile 14 Allocation (w) */
|
||||
Ifx_Strict_32Bit T15:2; /**< \brief [31:30] Tile 15 Allocation (w) */
|
||||
} Ifx_EMEM_TILECONFIG_Bits;
|
||||
|
||||
/** \brief Extended Tile Configuration Register */
|
||||
typedef struct _Ifx_EMEM_TILECONFIGXM_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit XCM0:2; /**< \brief [1:0] XCM0 Tile Allocation (w) */
|
||||
Ifx_Strict_32Bit reserved_2:14; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit XTM0:2; /**< \brief [17:16] XTM0 Tile Allocation (w) */
|
||||
Ifx_Strict_32Bit XTM1:2; /**< \brief [19:18] XTM1 Tile Allocation (w) */
|
||||
Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_EMEM_TILECONFIGXM_Bits;
|
||||
|
||||
/** \brief Trace Tile Control Register */
|
||||
typedef struct _Ifx_EMEM_TILECT_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit T0:1; /**< \brief [0:0] Trace Tile 0 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T1:1; /**< \brief [1:1] Trace Tile 1 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T2:1; /**< \brief [2:2] Trace Tile 2 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T3:1; /**< \brief [3:3] Trace Tile 3 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T4:1; /**< \brief [4:4] Trace Tile 4 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T5:1; /**< \brief [5:5] Trace Tile 5 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T6:1; /**< \brief [6:6] Trace Tile 6 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T7:1; /**< \brief [7:7] Trace Tile 7 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T8:1; /**< \brief [8:8] Trace Tile 8 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T9:1; /**< \brief [9:9] Trace Tile 9 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T10:1; /**< \brief [10:10] Trace Tile 10 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T11:1; /**< \brief [11:11] Trace Tile 11 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T12:1; /**< \brief [12:12] Trace Tile 12 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T13:1; /**< \brief [13:13] Trace Tile 13 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T14:1; /**< \brief [14:14] Trace Tile 14 Control Bit (w) */
|
||||
Ifx_Strict_32Bit T15:1; /**< \brief [15:15] Trace Tile 15 Control Bit (w) */
|
||||
Ifx_Strict_32Bit XTM0:1; /**< \brief [16:16] Trace XTM0 Tile Control Bit (w) */
|
||||
Ifx_Strict_32Bit XTM1:1; /**< \brief [17:17] Trace XTM1 Tile Control Bit (w) */
|
||||
Ifx_Strict_32Bit reserved_18:14; /**< \brief \internal Reserved */
|
||||
} Ifx_EMEM_TILECT_Bits;
|
||||
|
||||
/** \brief Tile Status Register */
|
||||
typedef struct _Ifx_EMEM_TILESTATE_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit TILE0:2; /**< \brief [1:0] Usage of Tile 0 (rh) */
|
||||
Ifx_Strict_32Bit TILE1:2; /**< \brief [3:2] Usage of Tile 1 (rh) */
|
||||
Ifx_Strict_32Bit TILE2:2; /**< \brief [5:4] Usage of Tile 2 (rh) */
|
||||
Ifx_Strict_32Bit TILE3:2; /**< \brief [7:6] Usage of Tile 3 (rh) */
|
||||
Ifx_Strict_32Bit TILE4:2; /**< \brief [9:8] Usage of Tile 4 (rh) */
|
||||
Ifx_Strict_32Bit TILE5:2; /**< \brief [11:10] Usage of Tile 5 (rh) */
|
||||
Ifx_Strict_32Bit TILE6:2; /**< \brief [13:12] Usage of Tile 6 (rh) */
|
||||
Ifx_Strict_32Bit TILE7:2; /**< \brief [15:14] Usage of Tile 7 (rh) */
|
||||
Ifx_Strict_32Bit TILE8:2; /**< \brief [17:16] Usage of Tile 8 (rh) */
|
||||
Ifx_Strict_32Bit TILE9:2; /**< \brief [19:18] Usage of Tile 9 (rh) */
|
||||
Ifx_Strict_32Bit TILE10:2; /**< \brief [21:20] Usage of Tile 10 (rh) */
|
||||
Ifx_Strict_32Bit TILE11:2; /**< \brief [23:22] Usage of Tile 11 (rh) */
|
||||
Ifx_Strict_32Bit TILE12:2; /**< \brief [25:24] Usage of Tile 12 (rh) */
|
||||
Ifx_Strict_32Bit TILE13:2; /**< \brief [27:26] Usage of Tile 13 (rh) */
|
||||
Ifx_Strict_32Bit TILE14:2; /**< \brief [29:28] Usage of Tile 14 (rh) */
|
||||
Ifx_Strict_32Bit TILE15:2; /**< \brief [31:30] Usage of Tile 15 (rh) */
|
||||
} Ifx_EMEM_TILESTATE_Bits;
|
||||
|
||||
/** \brief Extended Tile Status Register */
|
||||
typedef struct _Ifx_EMEM_TILESTATEXM_Bits
|
||||
{
|
||||
Ifx_Strict_32Bit XCM0:2; /**< \brief [1:0] Usage of XCM0 Tile (rh) */
|
||||
Ifx_Strict_32Bit reserved_2:14; /**< \brief \internal Reserved */
|
||||
Ifx_Strict_32Bit XTM0:2; /**< \brief [17:16] Usage of XTM0 Tile (rh) */
|
||||
Ifx_Strict_32Bit XTM1:2; /**< \brief [19:18] Usage of XTM1 Tile (rh) */
|
||||
Ifx_Strict_32Bit reserved_20:12; /**< \brief \internal Reserved */
|
||||
} Ifx_EMEM_TILESTATEXM_Bits;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Emem_union
|
||||
* \{ */
|
||||
|
||||
/** \brief Clock Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_CLC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_CLC;
|
||||
|
||||
/** \brief Module Identification Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_ID_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_ID;
|
||||
|
||||
/** \brief Standby RAM Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_SBRCTR_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_SBRCTR;
|
||||
|
||||
/** \brief Calibration Tile Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_TILECC_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_TILECC;
|
||||
|
||||
/** \brief Tile Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_TILECONFIG_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_TILECONFIG;
|
||||
|
||||
/** \brief Extended Tile Configuration Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_TILECONFIGXM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_TILECONFIGXM;
|
||||
|
||||
/** \brief Trace Tile Control Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_TILECT_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_TILECT;
|
||||
|
||||
/** \brief Tile Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_TILESTATE_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_TILESTATE;
|
||||
|
||||
/** \brief Extended Tile Status Register */
|
||||
typedef union
|
||||
{
|
||||
unsigned int U; /**< \brief Unsigned access */
|
||||
signed int I; /**< \brief Signed access */
|
||||
Ifx_EMEM_TILESTATEXM_Bits B; /**< \brief Bitfield access */
|
||||
} Ifx_EMEM_TILESTATEXM;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
/** \addtogroup IfxLld_Emem_struct
|
||||
* \{ */
|
||||
/******************************************************************************/
|
||||
/** \name Object L0
|
||||
* \{ */
|
||||
|
||||
/** \brief EMEM object */
|
||||
typedef volatile struct _Ifx_EMEM
|
||||
{
|
||||
Ifx_EMEM_CLC CLC; /**< \brief 0, Clock Control Register */
|
||||
unsigned char reserved_4[4]; /**< \brief 4, \internal Reserved */
|
||||
Ifx_EMEM_ID ID; /**< \brief 8, Module Identification Register */
|
||||
unsigned char reserved_C[20]; /**< \brief C, \internal Reserved */
|
||||
Ifx_EMEM_TILECONFIG TILECONFIG; /**< \brief 20, Tile Configuration Register */
|
||||
Ifx_EMEM_TILECC TILECC; /**< \brief 24, Calibration Tile Control Register */
|
||||
Ifx_EMEM_TILECT TILECT; /**< \brief 28, Trace Tile Control Register */
|
||||
Ifx_EMEM_TILESTATE TILESTATE; /**< \brief 2C, Tile Status Register */
|
||||
unsigned char reserved_30[4]; /**< \brief 30, \internal Reserved */
|
||||
Ifx_EMEM_SBRCTR SBRCTR; /**< \brief 34, Standby RAM Control Register */
|
||||
unsigned char reserved_38[8]; /**< \brief 38, \internal Reserved */
|
||||
Ifx_EMEM_TILECONFIGXM TILECONFIGXM; /**< \brief 40, Extended Tile Configuration Register */
|
||||
unsigned char reserved_44[8]; /**< \brief 44, \internal Reserved */
|
||||
Ifx_EMEM_TILESTATEXM TILESTATEXM; /**< \brief 4C, Extended Tile Status Register */
|
||||
unsigned char reserved_50[176]; /**< \brief 50, \internal Reserved */
|
||||
} Ifx_EMEM;
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/** \} */
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
#endif /* IFXEMEM_REGDEF_H */
|
||||
10179
Example/13-FFT_Demo/Libraries/BaseSw/Infra/Sfr/TC26B/_Reg/IfxEray_bf.h
Normal file
10179
Example/13-FFT_Demo/Libraries/BaseSw/Infra/Sfr/TC26B/_Reg/IfxEray_bf.h
Normal file
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Load Diff
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Reference in New Issue
Block a user