mirror of
https://gitee.com/seekfree/TC264_Library.git
synced 2026-06-04 03:32:56 +00:00
V1.1.8
将isr_config.h中 INT_SERVICE设置改为使用枚举值进行设置
更改illd文件夹名称为infineon_libraries
在TC264配置文件中，增加频率设置选项
增加main等待，等待所有核心初始化完毕才开始运行
修改CLK_FREQ宏定义名称为CMU_CLK_FREQ
DMA所需的数组地址通过指针进行传递，这样可以避免在不调用摄像头的时候，相关的数组不会占用RAM
将总钻风pclk改为下降沿触发
将无线转串口的RTS引脚配置参数修改为下拉
This commit is contained in:
SEEKFREE_Kang
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43
Seekfree_TC264_Opensource_Library/Debug/USER/subdir.mk
Normal file
43
Seekfree_TC264_Opensource_Library/Debug/USER/subdir.mk
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158
Seekfree_TC264_Opensource_Library/Debug/makefile
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158
Seekfree_TC264_Opensource_Library/Debug/makefile
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@@ -0,0 +1,158 @@
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||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
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||||
|
||||
-include ../makefile.init
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||||
|
||||
RM := rm -rf
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||||
|
||||
# All of the sources participating in the build are defined here
|
||||
-include sources.mk
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-include USER/subdir.mk
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-include Libraries/seekfree_peripheral/subdir.mk
|
||||
-include Libraries/seekfree_libraries/common/subdir.mk
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-include Libraries/seekfree_libraries/subdir.mk
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-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap/subdir.mk
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-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/_Lib/InternalMux/subdir.mk
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||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/_Lib/DataHandling/subdir.mk
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-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/_Impl/subdir.mk
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-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Vadc/Std/subdir.mk
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||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Vadc/Adc/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Stm/Timer/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Stm/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Src/Std/subdir.mk
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||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Smu/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Sent/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Sent/Sent/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Scu/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Qspi/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Qspi/SpiSlave/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Qspi/SpiMaster/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Psi5s/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Psi5s/Psi5s/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Psi5/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Psi5/Psi5/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Port/Std/subdir.mk
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||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Port/Io/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Multican/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Multican/Can/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Mtu/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Msc/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Msc/Msc/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Iom/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Iom/Driver/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/I2c/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/I2c/I2c/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Hssl/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Hssl/Hssl/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Trig/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Tom/Timer/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Tom/PwmHl/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Tom/Pwm/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Tim/In/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Atom/Timer/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Atom/PwmHl/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Atom/Pwm/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gpt12/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gpt12/IncrEnc/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Flash/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Fft/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Fft/Fft/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Fce/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Fce/Crc/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Eth/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Eth/Phy_Pef7071/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Eray/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Eray/Eray/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Emem/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Dts/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Dts/Dts/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Dsadc/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Dsadc/Rdc/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Dsadc/Dsadc/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Dma/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Dma/Dma/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Cpu/Trap/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Cpu/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Cpu/Irq/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Cpu/CStart/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Cif/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Cif/Cam/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Ccu6/TimerWithTrigger/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Ccu6/Timer/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Ccu6/TPwm/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Ccu6/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Ccu6/PwmHl/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Ccu6/PwmBc/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Ccu6/Icu/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Asclin/Std/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Asclin/Spi/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Asclin/Lin/subdir.mk
|
||||
-include Libraries/infineon_libraries/iLLD/TC26B/Tricore/Asclin/Asc/subdir.mk
|
||||
-include Libraries/infineon_libraries/Service/CpuGeneric/SysSe/Time/subdir.mk
|
||||
-include Libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math/subdir.mk
|
||||
-include Libraries/infineon_libraries/Service/CpuGeneric/SysSe/General/subdir.mk
|
||||
-include Libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm/subdir.mk
|
||||
-include Libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp/subdir.mk
|
||||
-include Libraries/infineon_libraries/Service/CpuGeneric/StdIf/subdir.mk
|
||||
-include Libraries/infineon_libraries/Service/CpuGeneric/If/subdir.mk
|
||||
-include Libraries/infineon_libraries/Infra/Platform/Tricore/Compilers/subdir.mk
|
||||
-include subdir.mk
|
||||
-include objects.mk
|
||||
|
||||
ifneq ($(MAKECMDGOALS),clean)
|
||||
ifneq ($(strip $(CC_DEPS)),)
|
||||
-include $(CC_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C++_DEPS)),)
|
||||
-include $(C++_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C_UPPER_DEPS)),)
|
||||
-include $(C_UPPER_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(CXX_DEPS)),)
|
||||
-include $(CXX_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(CPP_DEPS)),)
|
||||
-include $(CPP_DEPS)
|
||||
endif
|
||||
ifneq ($(strip $(C_DEPS)),)
|
||||
-include $(C_DEPS)
|
||||
endif
|
||||
endif
|
||||
|
||||
-include ../makefile.defs
|
||||
|
||||
# Add inputs and outputs from these tool invocations to the build variables
|
||||
SECONDARY_SIZE += \
|
||||
Seekfree_TC264_Opensource_Library.siz \
|
||||
|
||||
|
||||
# All Target
|
||||
all: Seekfree_TC264_Opensource_Library.elf secondary-outputs
|
||||
|
||||
# Tool invocations
|
||||
Seekfree_TC264_Opensource_Library.elf: $(OBJS)
|
||||
@echo 'Building target: $@'
|
||||
@echo 'Invoking: TASKING Linker'
|
||||
cctc -lrt -lfp_fpu -lcs_fpu -Wl-Oc -Wl-OL -Wl-Ot -Wl-Ox -Wl-Oy -Wl--map-file="Seekfree_TC264_Opensource_Library.map" -Wl-mc -Wl-mf -Wl-mi -Wl-mk -Wl-ml -Wl-mm -Wl-md -Wl-mr -Wl-mu --no-warnings= -Wl--error-limit=42 --strict --anachronisms --force-c++ -Ctc26xb -o"Seekfree_TC264_Opensource_Library.elf" -Wl-o"Seekfree_TC264_Opensource_Library.hex:IHEX" --lsl-core=vtc --lsl-file=../Lcf_Tasking_Tricore_Tc.lsl $(OBJS)
|
||||
@echo 'Finished building target: $@'
|
||||
@echo ' '
|
||||
|
||||
Seekfree_TC264_Opensource_Library.siz: Seekfree_TC264_Opensource_Library.elf
|
||||
@echo 'Invoking: Print Size'
|
||||
elfsize "Seekfree_TC264_Opensource_Library.elf"
|
||||
@echo 'Finished building: $@'
|
||||
@echo ' '
|
||||
|
||||
# Other Targets
|
||||
clean:
|
||||
find . ! -name "*.mk" ! -name "makefile" ! -name "." -type f -delete
|
||||
-@echo ' '
|
||||
|
||||
secondary-outputs: $(SECONDARY_SIZE)
|
||||
|
||||
.PHONY: all clean dependents
|
||||
|
||||
-include ../makefile.targets
|
||||
8
Seekfree_TC264_Opensource_Library/Debug/objects.mk
Normal file
8
Seekfree_TC264_Opensource_Library/Debug/objects.mk
Normal file
@@ -0,0 +1,8 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
USER_OBJS :=
|
||||
|
||||
LIBS :=
|
||||
|
||||
117
Seekfree_TC264_Opensource_Library/Debug/sources.mk
Normal file
117
Seekfree_TC264_Opensource_Library/Debug/sources.mk
Normal file
@@ -0,0 +1,117 @@
|
||||
################################################################################
|
||||
# Automatically-generated file. Do not edit!
|
||||
################################################################################
|
||||
|
||||
C_UPPER_SRCS :=
|
||||
CXX_SRCS :=
|
||||
C++_SRCS :=
|
||||
OBJ_SRCS :=
|
||||
CC_SRCS :=
|
||||
SRC_SRCS :=
|
||||
CPP_SRCS :=
|
||||
C_SRCS :=
|
||||
O_SRCS :=
|
||||
CC_DEPS :=
|
||||
C++_DEPS :=
|
||||
EXECUTABLES :=
|
||||
C_UPPER_DEPS :=
|
||||
CXX_DEPS :=
|
||||
OBJS :=
|
||||
SECONDARY_SIZE :=
|
||||
COMPILED_SRCS :=
|
||||
CPP_DEPS :=
|
||||
C_DEPS :=
|
||||
|
||||
# Every subdirectory with source files must be described here
|
||||
SUBDIRS := \
|
||||
Libraries/infineon_libraries/Infra/Platform/Tricore/Compilers \
|
||||
Libraries/infineon_libraries/Service/CpuGeneric/If \
|
||||
Libraries/infineon_libraries/Service/CpuGeneric/StdIf \
|
||||
Libraries/infineon_libraries/Service/CpuGeneric/SysSe/Bsp \
|
||||
Libraries/infineon_libraries/Service/CpuGeneric/SysSe/Comm \
|
||||
Libraries/infineon_libraries/Service/CpuGeneric/SysSe/General \
|
||||
Libraries/infineon_libraries/Service/CpuGeneric/SysSe/Math \
|
||||
Libraries/infineon_libraries/Service/CpuGeneric/SysSe/Time \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Asclin/Asc \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Asclin/Lin \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Asclin/Spi \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Asclin/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Ccu6/Icu \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Ccu6/PwmBc \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Ccu6/PwmHl \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Ccu6/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Ccu6/TPwm \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Ccu6/Timer \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Ccu6/TimerWithTrigger \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Cif/Cam \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Cif/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Cpu/CStart \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Cpu/Irq \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Cpu/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Cpu/Trap \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Dma/Dma \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Dma/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Dsadc/Dsadc \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Dsadc/Rdc \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Dsadc/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Dts/Dts \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Dts/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Emem/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Eray/Eray \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Eray/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Eth/Phy_Pef7071 \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Eth/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Fce/Crc \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Fce/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Fft/Fft \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Fft/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Flash/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gpt12/IncrEnc \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gpt12/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Atom/Pwm \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Atom/PwmHl \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Atom/Timer \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Tim/In \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Tom/Pwm \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Tom/PwmHl \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Tom/Timer \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Gtm/Trig \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Hssl/Hssl \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Hssl/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/I2c/I2c \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/I2c/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Iom/Driver \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Iom/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Msc/Msc \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Msc/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Mtu/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Multican/Can \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Multican/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Port/Io \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Port/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Psi5/Psi5 \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Psi5/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Psi5s/Psi5s \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Psi5s/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Qspi/SpiMaster \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Qspi/SpiSlave \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Qspi/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Scu/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Sent/Sent \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Sent/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Smu/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Src/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Stm/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Stm/Timer \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Vadc/Adc \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/Vadc/Std \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/_Impl \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/_Lib/DataHandling \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/_Lib/InternalMux \
|
||||
Libraries/infineon_libraries/iLLD/TC26B/Tricore/_PinMap \
|
||||
Libraries/seekfree_libraries/common \
|
||||
Libraries/seekfree_libraries \
|
||||
Libraries/seekfree_peripheral \
|
||||
USER \
|
||||
|
||||
@@ -1,70 +1,74 @@
|
||||
/**
|
||||
/**********************************************************************************************************************
|
||||
* \file Lcf_Tasking_Tricore_Tc.lsl
|
||||
* \brief Linker command file for Tasking compiler.
|
||||
*
|
||||
* \copyright Copyright (c) 2018 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Infineon Technologies AG (Infineon) is supplying this file for use
|
||||
* exclusively with Infineon's microcontroller products. This file can be freely
|
||||
* distributed within development tools that are supporting such microcontroller
|
||||
* products.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
|
||||
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
*/
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
#define LCF_CSA0_SIZE 8k
|
||||
#define LCF_USTACK0_SIZE 2k
|
||||
#define LCF_ISTACK0_SIZE 1k
|
||||
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
#define LCF_CSA1_SIZE 8k
|
||||
#define LCF_USTACK1_SIZE 2k
|
||||
#define LCF_ISTACK1_SIZE 1k
|
||||
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
#define LCF_HEAP_SIZE 2k
|
||||
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
#define LCF_CPU0 0
|
||||
#define LCF_CPU1 1
|
||||
|
||||
/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
/*#define LCF_DEFAULT_HOST LCF_CPU0*/
|
||||
#define LCF_DEFAULT_HOST LCF_CPU1
|
||||
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
#define LCF_DSPR1_START 0x60000000
|
||||
#define LCF_DSPR1_SIZE 120k
|
||||
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
#define LCF_DSPR0_START 0x70000000
|
||||
#define LCF_DSPR0_SIZE 72k
|
||||
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE)
|
||||
#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE)
|
||||
#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE)
|
||||
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE)
|
||||
#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE)
|
||||
#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE)
|
||||
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE)
|
||||
#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE)
|
||||
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
#define LCF_INTVEC0_START 0x800F4000
|
||||
#define LCF_TRAPVEC0_START 0x80000100
|
||||
#define LCF_TRAPVEC1_START 0x800F6000
|
||||
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
#define INTTAB0 (LCF_INTVEC0_START)
|
||||
#define TRAPTAB0 (LCF_TRAPVEC0_START)
|
||||
#define TRAPTAB1 (LCF_TRAPVEC1_START)
|
||||
|
||||
#define RESET 0x80000020
|
||||
#define RESET 0x80000020
|
||||
|
||||
#include "tc1v1_6_x.lsl"
|
||||
|
||||
@@ -72,398 +76,366 @@
|
||||
|
||||
processor mpe
|
||||
{
|
||||
derivative = tc26;
|
||||
derivative = tc26B;
|
||||
}
|
||||
|
||||
derivative tc26
|
||||
derivative tc26B
|
||||
{
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory lmuram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
priority = 2;
|
||||
map cached (dest=bus:sri, dest_offset=0x90000000, size=32k);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=32k);
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=1M);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=1M);
|
||||
}
|
||||
core tc0
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 100; // add 100 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core tc1 // core 1 TC16E
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
space_id_offset = 200; // add 200 to all space IDs in the architecture definition
|
||||
copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections
|
||||
}
|
||||
|
||||
core vtc
|
||||
{
|
||||
architecture = TC1V1.6.X;
|
||||
import tc0; // add all address spaces of core tc0 to core vtc for linking and locating
|
||||
import tc1; // tc1
|
||||
}
|
||||
|
||||
bus sri
|
||||
{
|
||||
mau = 8;
|
||||
width = 32;
|
||||
|
||||
// map shared addresses one-to-one to real cores and virtual cores
|
||||
map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000);
|
||||
}
|
||||
|
||||
memory dsram1 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 120k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=120k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60000000, size=120k);
|
||||
}
|
||||
|
||||
memory psram1 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 32k;
|
||||
type = ram;
|
||||
map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=32k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x60100000, size=32k);
|
||||
}
|
||||
|
||||
memory dsram0 // Data Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 72k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=72k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70000000, size=72k);
|
||||
}
|
||||
|
||||
memory psram0 // Program Scratch Pad Ram
|
||||
{
|
||||
mau = 8;
|
||||
size = 16k;
|
||||
type = ram;
|
||||
map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=16k, priority=8);
|
||||
map (dest=bus:sri, dest_offset=0x70100000, size=16k);
|
||||
}
|
||||
|
||||
memory pfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1M;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80000000, size=1M);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=1M);
|
||||
}
|
||||
|
||||
memory pfls1
|
||||
{
|
||||
mau = 8;
|
||||
size = 1536K;
|
||||
type = rom;
|
||||
map cached (dest=bus:sri, dest_offset=0x80100000, size=1536K);
|
||||
map not_cached (dest=bus:sri, dest_offset=0xa0100000, reserved, size=1536K);
|
||||
}
|
||||
|
||||
memory dfls0
|
||||
{
|
||||
mau = 8;
|
||||
size = 1m+16k;
|
||||
type = reserved nvram;
|
||||
map (dest=bus:sri, dest_offset=0xaf000000, size=1040k );
|
||||
}
|
||||
|
||||
memory edmem
|
||||
{
|
||||
mau = 8;
|
||||
size = 512K;
|
||||
type = ram;
|
||||
map (dest=bus:sri, dest_offset=0x9f000000, size=512K);
|
||||
map (dest=bus:sri, dest_offset=0xbf000000, reserved, size=512K);
|
||||
}
|
||||
|
||||
#if (__VERSION__ >= 6003)
|
||||
#if (__VERSION__ >= 6003)
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
heap "heap" (min_size = (1k), fixed, align = 8);
|
||||
}
|
||||
#endif
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
start_address
|
||||
(
|
||||
symbol = "_START"
|
||||
);
|
||||
}
|
||||
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
stack "ustack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc0" (min_size = 1k, fixed, align = 8);
|
||||
stack "ustack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
stack "istack_tc1" (min_size = 1k, fixed, align = 8);
|
||||
}
|
||||
|
||||
/*Section setup for the copy table*/
|
||||
section_setup :vtc:linear
|
||||
{
|
||||
copytable
|
||||
(
|
||||
align = 4,
|
||||
dest = linear,
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc0";
|
||||
space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa;
|
||||
},
|
||||
table
|
||||
{
|
||||
symbol = "_lc_ub_table_tc1";
|
||||
space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa;
|
||||
}
|
||||
);
|
||||
}
|
||||
|
||||
/*Near data sections*/
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1*)";
|
||||
select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0*)";
|
||||
select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.zdata|.zdata*)";
|
||||
select "(.zbss|.zbss*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
/*Small data sections, No option given for CPU specific user sections to make generated code portable across Cpus*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.sdata |.sdata*)";
|
||||
select "(.sbss |.sbss*)";
|
||||
}
|
||||
"_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) + 32k : addressof(group:a0) & 0xF0000000 + 32k;
|
||||
|
||||
/*Far data sections*/
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
select ".bss.cpu1_dsram";
|
||||
select ".data.cpu1_dsram";
|
||||
select ".zdata.cpu1_dsram";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
select ".bss.cpu0_dsram";
|
||||
select ".data.cpu0_dsram";
|
||||
select ".zdata.cpu0_dsram";
|
||||
|
||||
}
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:edmem)
|
||||
{
|
||||
select "(.data.edmemdata|.data.edmemdata*)";
|
||||
select "(.bss.edmembss|.bss.edmembss*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram1)
|
||||
{
|
||||
select "(.data.data_cpu1|.data.data_cpu1*)";
|
||||
select "(.bss.bss_cpu1|.bss.bss_cpu1*)";
|
||||
}
|
||||
|
||||
group (ordered, contiguous, align = 4, run_addr = mem:dsram0)
|
||||
{
|
||||
select "(.data.data_cpu0|.data.data_cpu0*)";
|
||||
select "(.bss.bss_cpu0|.bss.bss_cpu0*)";
|
||||
}
|
||||
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1)
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0)
|
||||
# endif
|
||||
{
|
||||
select "(.data|.data*)";
|
||||
select "(.bss|.bss*)";
|
||||
}
|
||||
|
||||
/*Heap sections*/
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU1
|
||||
group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET])
|
||||
# endif
|
||||
# if LCF_DEFAULT_HOST == LCF_CPU0
|
||||
group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET])
|
||||
# endif
|
||||
{
|
||||
heap "heap" (size = LCF_HEAP_SIZE);
|
||||
}
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET])
|
||||
{
|
||||
stack "ustack_tc1" (size = LCF_USTACK1_SIZE);
|
||||
}
|
||||
"__USTACK1":= "_lc_ue_ustack_tc1";
|
||||
"__USTACK1_END":= "_lc_ub_ustack_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET])
|
||||
{
|
||||
stack "istack_tc1" (size = LCF_ISTACK1_SIZE);
|
||||
}
|
||||
"__ISTACK1":= "_lc_ue_istack_tc1";
|
||||
"__ISTACK1_END":= "_lc_ub_istack_tc1";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET])
|
||||
reserved "csa_tc1" (size = LCF_CSA1_SIZE);
|
||||
"__CSA1":= "_lc_ub_csa_tc1";
|
||||
"__CSA1_END":= "_lc_ue_csa_tc1";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET])
|
||||
{
|
||||
stack "ustack_tc0" (size = LCF_USTACK0_SIZE);
|
||||
}
|
||||
"__USTACK0":= "_lc_ue_ustack_tc0";
|
||||
"__USTACK0_END":= "_lc_ub_ustack_tc0";
|
||||
|
||||
group (ordered, align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET])
|
||||
{
|
||||
stack "istack_tc0" (size = LCF_ISTACK0_SIZE);
|
||||
}
|
||||
"__ISTACK0":= "_lc_ue_istack_tc0";
|
||||
"__ISTACK0_END":= "_lc_ub_istack_tc0";
|
||||
|
||||
group (ordered, align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET])
|
||||
reserved "csa_tc0" (size = LCF_CSA0_SIZE);
|
||||
"__CSA0":= "_lc_ub_csa_tc0";
|
||||
"__CSA0_END":= "_lc_ue_csa_tc0";
|
||||
}
|
||||
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
"_lc_u_int_tab" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU0" = (LCF_INTVEC0_START);
|
||||
"__INTTAB_CPU1" = (LCF_INTVEC0_START);
|
||||
|
||||
// interrupt vector tables for tc0, tc1, tc2
|
||||
group int_tab_tc0 (ordered)
|
||||
{
|
||||
# include "inttab0.lsl"
|
||||
}
|
||||
|
||||
group trapvec_tc0 (ordered, run_addr=LCF_TRAPVEC0_START)
|
||||
{
|
||||
select "(.text.traptab_cpu0*)";
|
||||
}
|
||||
|
||||
group trapvec_tc1 (ordered, run_addr=LCF_TRAPVEC1_START)
|
||||
{
|
||||
select "(.text.traptab_cpu1*)";
|
||||
}
|
||||
|
||||
group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0)
|
||||
{
|
||||
select "(.text.psram_cpu0*)";
|
||||
select "(.text.cpu0_psram*)";
|
||||
}
|
||||
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.zdata_lmu|.zdata_lmu*)";
|
||||
select "(.zbss_lmu|.zbss_lmu*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
|
||||
group a9 (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.sdata_lmu|.sdata_lmu*)";
|
||||
select "(.sbss_lmu|.sbss_lmu*)";
|
||||
}
|
||||
"_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) + 32k : addressof(group:a9) & 0xF0000000 + 32k;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:lmuram)
|
||||
{
|
||||
select "(.data_lmu|.data_lmu*)";
|
||||
select "(.bss_lmu|.bss_lmu*)";
|
||||
select "(.lmu_data|.lmu_data*)";
|
||||
select "(.lmu_bss|.lmu_bss*)";
|
||||
select "(.data_a9|.data_a9*)";
|
||||
select "(.bss_a9|.bss_a9*)";
|
||||
}
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1)
|
||||
{
|
||||
select "(.text.psram_cpu1*)";
|
||||
select "(.text.cpu1_psram*)";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:abs18
|
||||
{
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".zrodata*";
|
||||
}
|
||||
}
|
||||
|
||||
section_layout :vtc:linear
|
||||
{
|
||||
group bmh_0 (ordered, run_addr=0x80000000)
|
||||
{
|
||||
select "*.bmhd_0";
|
||||
}
|
||||
group bmh_1 (ordered, run_addr=0x80020000)
|
||||
{
|
||||
select "*.bmhd_1";
|
||||
}
|
||||
group reset (ordered, run_addr=0x80000020)
|
||||
{
|
||||
select "*.start";
|
||||
}
|
||||
group interface_const (ordered, run_addr=0x80000040)
|
||||
{
|
||||
select "*.interface_const";
|
||||
}
|
||||
"__IF_CONST" := addressof(group:ainterface_const);
|
||||
group a1 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".srodata*";
|
||||
select ".ldata*";
|
||||
}
|
||||
"_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) + 32k : addressof(group:a1) & 0xF0000000 + 32k;
|
||||
"_A1_MEM" = "_LITERAL_DATA_";
|
||||
"_A9_DATA_" := 0x00000000;
|
||||
"_A9_MEM" = "_A9_DATA_";
|
||||
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".rodata*";
|
||||
}
|
||||
group (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select ".text*";
|
||||
}
|
||||
group a8 (ordered, run_addr=mem:pfls0)
|
||||
{
|
||||
select "(.rodata_a8|.rodata_a8*)";
|
||||
}
|
||||
"_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) + 32k : addressof(group:a8) & 0xF0000000 + 32k;
|
||||
"_A8_MEM" := "_A8_DATA_";
|
||||
|
||||
"__TRAPTAB_CPU0" := TRAPTAB0;
|
||||
"__TRAPTAB_CPU1" := TRAPTAB1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,72 +0,0 @@
|
||||
/**
|
||||
* \file Ifx_Cfg.h
|
||||
* \brief Configuration.
|
||||
*
|
||||
* \version iLLD_Demos_1_0_1_11_0
|
||||
* \copyright Copyright (c) 2014 Infineon Technologies AG. All rights reserved.
|
||||
*
|
||||
*
|
||||
* IMPORTANT NOTICE
|
||||
*
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or
|
||||
* the company in which ordinary course of business you are acting and (ii)
|
||||
* Infineon Technologies AG or its licensees. If and as long as no such
|
||||
* terms of use are agreed, use of this file is subject to following:
|
||||
|
||||
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
|
||||
* Permission is hereby granted, free of charge, to any person or
|
||||
* organization obtaining a copy of the software and accompanying
|
||||
* documentation covered by this license (the "Software") to use, reproduce,
|
||||
* display, distribute, execute, and transmit the Software, and to prepare
|
||||
* derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
|
||||
* The copyright notices in the Software and this entire statement, including
|
||||
* the above license grant, this restriction and the following disclaimer, must
|
||||
* be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are
|
||||
* solely in the form of machine-executable object code generated by a source
|
||||
* language processor.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
|
||||
*
|
||||
*
|
||||
*
|
||||
* \defgroup IfxLld_Demo_StmDemo_SrcDoc_IlldConfig iLLD configuration
|
||||
* \ingroup IfxLld_Demo_StmDemo_SrcDoc
|
||||
*/
|
||||
|
||||
#ifndef IFX_CFG_H
|
||||
#define IFX_CFG_H
|
||||
|
||||
/******************************************************************************/
|
||||
/*-----------------------------------Macros-----------------------------------*/
|
||||
/******************************************************************************/
|
||||
|
||||
/** \addtogroup IfxLld_Demo_StmDemo_SrcDoc_IlldConfig
|
||||
* \{ */
|
||||
|
||||
/*______________________________________________________________________________
|
||||
** Configuration for IfxScu_cfg.h
|
||||
**____________________________________________________________________________*/
|
||||
/**
|
||||
* \name Frequency configuration
|
||||
* \{
|
||||
*/
|
||||
#define IFX_CFG_SCU_XTAL_FREQUENCY (20000000) /**< \copydoc IFX_CFG_SCU_XTAL_FREQUENCY */
|
||||
|
||||
/** \} */
|
||||
|
||||
/** \} */
|
||||
|
||||
#endif /* IFX_CFG_H */
|
||||
@@ -1,99 +1,110 @@
|
||||
V1.0.0
|
||||
<09><>ʼ<EFBFBD>汾
|
||||
|
||||
|
||||
V1.0.1
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
<09><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
|
||||
<09><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.2
|
||||
<09><EFBFBD>ģ<EFBFBD><C4A3>IICĬ<43><C4AC><EFBFBD><EFBFBD>ʱʱ<CAB1><CAB1>Ϊ20
|
||||
<09><><EFBFBD><EFBFBD> <20><>Ҫ<EFBFBD>ر<EFBFBD>ע<EFBFBD><D7A2>P20_2<5F>Dz<EFBFBD><C7B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĺ<EFBFBD><C4B9><EFBFBD> ע<><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ɼ<EFBFBD>DMA<4D><41>Ϊlink<6E><6B><EFBFBD>䣬<EFBFBD><E4A3AC><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>DMA<4D>жϴ<D0B6><CFB4><EFBFBD>
|
||||
<09><EFBFBD>Ĭ<EFBFBD>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD>IIC<49><43><EFBFBD>Ŷ<EFBFBD><C5B6><EFBFBD>
|
||||
<09><>6050<35><30> <20><>Ҫ<EFBFBD>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ģ<EFBFBD>飬<EFBFBD>ڳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD>ϵ<EFBFBD><CFB5><EFBFBD>ģ<EFBFBD><C4A3>IIC<49><43>ʼ<EFBFBD><CABC>
|
||||
<09><><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.3
|
||||
<09><>spi<70><69>uart<72><74>pit<69>в<EFBFBD><D0B2>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>volatile<6C><65><EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.4
|
||||
Ĭ<>Ϲ<EFBFBD>ѡ<EFBFBD><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HEX<45>Ĺ<EFBFBD><C4B9><EFBFBD>
|
||||
<09><>Cpu1_Main.c<>е<EFBFBD>core1_main<69><6E><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϵĺ<CFB5><C4BA><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>CPU1<55><EFBFBD><DEB7><EFBFBD>Ӧ<EFBFBD>жϵ<D0B6><CFB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
ɾ<><C9BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>еİ<D0B5><C4B0><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD>Ϣ
|
||||
<09><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD>ֱ<EFBFBD>ֻ<EFBFBD>ɼ<EFBFBD>һ<EFBFBD>ε<EFBFBD><CEB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><><EFBFBD><EFBFBD>RDA5807 FMģ<4D><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>LSL<53>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>#pragma <20><>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߳<EFBFBD><DFB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>RAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ο<EFBFBD><CEBF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Specifies_Variable_Or_Code_Location_Demo
|
||||
//ʹ<><CAB9>#pragma section all "cpu0_dsram" <20><> #pragma section all restore<72><65><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram
|
||||
//<2F><><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>仰<EFBFBD>м伴<D0BC>ɣ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
#pragma section all "cpu0_dsram"
|
||||
uint8 test_arry[5]; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D>Ϊcpu1_dsram <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu1_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>CPUִ<55>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>õı<C3B5><C4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu1_dsram<61><6D><EFBFBD><EFBFBD>
|
||||
#pragma section all restore
|
||||
|
||||
//ʹ<><CAB9>#pragma section all "cpu0_psram" <20><> #pragma section all restore<72><65><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu0_psram
|
||||
//<2F><><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>仰<EFBFBD>м伴<D0BC>ɣ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
#pragma section all "cpu0_psram"
|
||||
void delay_tset(void) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu0_psram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4>
|
||||
{
|
||||
int i;
|
||||
i = 999;
|
||||
while(i--);
|
||||
}
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_psram<61><6D>Ϊcpu1_psram <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu1_psram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>CPUִ<55>У<EFBFBD><D0A3><EFBFBD><F2BDABBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>£<EFBFBD><C2A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ǵ<EFBFBD>flash<73><68><EFBFBD>ز<EFBFBD>ִ<EFBFBD><D6B4>
|
||||
//ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAM<41><4D><EFBFBD>У<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD>еij<D0B5><C4B3><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cache<68><EFBFBD><F3A3ACBB><EFBFBD><EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD>ٶȽ<D9B6><C8BD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ǾͿ<C7BE><CDBF>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAMִ<4D>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٶ<EFBFBD>
|
||||
#pragma section all restore
|
||||
|
||||
V1.0.5
|
||||
ȡ<><C8A1>HEX<45><58><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.6
|
||||
<09><><EFBFBD><EFBFBD>ADC<44><43><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD>õĺ궨<C4BA>壬ADC_SAMPLE_FREQUENCY<43><59><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ10Mhz<68><7A><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC><EFBFBD>µ<EFBFBD><C2B5>ٶ<EFBFBD><D9B6>нϴ<D0BD><CFB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.7
|
||||
<09><EFBFBD>ʹ<EFBFBD><CAB9>systick_getval<61><6C>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱʱ<CAB1>䳬<EFBFBD><E4B3AC>4<EFBFBD><34><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>⡣
|
||||
<09>Բ<EFBFBD><D4B2>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>#pragma warning<6E><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ż<EFBFBD><C5BB>ȼ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>־<EFBFBD><D6BE><EFBFBD>
|
||||
<09><EFBFBD>1.8<EFBFBD><EFBFBD>TFT<EFBFBD><EFBFBD>Ļ<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD>й<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD>ֵĴ<EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.8
|
||||
<09><EFBFBD>CCU61 ͨ<><CDA8>1<EFBFBD>ж<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ô<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><EFBFBD>CCU6<55><36><EFBFBD>ߵ<EFBFBD><DFB5>Ե<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD>ֹͣ<CDA3><D6B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߵ<EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><>CCU6<55><36><EFBFBD><EFBFBD>pit_close<73><65>pit_start<72><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڿ<EFBFBD><DABF>ƶ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>Ŀ<EFBFBD>ʼ<EFBFBD><CABC>ֹͣ
|
||||
<09><>CCU6<55><36><EFBFBD><EFBFBD>pit_disable_interrupt<70><74>pit_enable_interrupt<70><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڿ<EFBFBD><DABF><EFBFBD><EFBFBD>жϿ<D0B6><CFBF><EFBFBD>
|
||||
|
||||
V1.0.9
|
||||
<09><EFBFBD>RDA5807<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><EFBFBD>֤<EFBFBD>ϵ<EFBFBD><EFBFBD><EFBFBD>1S<EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD>FMģ<EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.0
|
||||
<09><>ISR<53>ļ<EFBFBD><C4BC>ڵ<EFBFBD><DAB5>жϺ<D0B6><CFBA><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>enableInterrupts(); <20><>ʵ<EFBFBD><CAB5><EFBFBD>ж<EFBFBD>Ƕ<EFBFBD>Ĺ<EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><><EFBFBD><EFBFBD>RDA5807<30><37>ȡRSSI<53><49><EFBFBD>ܺ<EFBFBD><EFBFBD><EFBFBD>
|
||||
<09><>DMA<4D><41><EFBFBD>Ӵ<EFBFBD><D3B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD><C3B5>ı<EFBFBD><C4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ERU_DMA_INT_SERVICE<43><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD>Ӧ<EFBFBD><D3A6>CPU<50><55>
|
||||
|
||||
V1.1.1
|
||||
<09><EFBFBD>uart_getchar<61><72><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD>ס<EFBFBD><D7A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.2
|
||||
<09><EFBFBD>ATOM_PWM<57><4D><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD><D5B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>쳣<EFBFBD><ECB3A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.3
|
||||
<09><EFBFBD>SPI spi_mosi<73><69><EFBFBD><EFBFBD><EFBFBD>ڽ<EFBFBD><DABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>յ<EFBFBD>ʱ<EFBFBD><EFBFBD><F2A3ACB3><EFBFBD><EFBFBD>쳣
|
||||
|
||||
V1.1.4
|
||||
<09><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>ע<EFBFBD>ͱ<EFBFBD><CDB1><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>µ<EFBFBD>һ<EFBFBD><D2BB>ע<EFBFBD>ͱ<EFBFBD><CDB1>Զ<EFBFBD><D4B6>۵<EFBFBD><DBB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
V1.1.8
|
||||
<20><>isr_config.h<><68> INT_SERVICE<43><45><EFBFBD>ø<EFBFBD>Ϊʹ<CEAA><CAB9>ö<EFBFBD><C3B6>ֵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD>illd<6C>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊinfineon_libraries
|
||||
<20><>TC264<36><34><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC>У<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD>main<69>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD>к<EFBFBD><D0BA>ij<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD>ϲſ<CFB2>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD>
|
||||
<20><EFBFBD>CLK_FREQ<45>궨<EFBFBD><EAB6A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΪCMU_CLK_FREQ
|
||||
DMA<4D><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַͨ<D6B7><CDA8>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4>ݣ<EFBFBD><DDA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ա<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD><EFBFBD><EFBFBD><EFBFBD>鲻<EFBFBD><EFBFBD>ռ<EFBFBD><EFBFBD>RAM
|
||||
<20><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>pclk<EFBFBD><EFBFBD>Ϊ<EFBFBD>½<EFBFBD><EFBFBD>ش<EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA><EFBFBD>ڵ<EFBFBD>RTS<54><53><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.7
|
||||
<20><><EFBFBD>Ӵ<EFBFBD><D3B4>ڰ汾<DAB0><E6B1BE>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><EFBFBD><EFBFBD>ͱ<EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><EFBFBD>ö<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.6
|
||||
<20><>printf<74><EFBFBD>Ϊͨ<CEAA><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD>ΪADS<44>Ĺ<EFBFBD><C4B9>̣<EFBFBD>ADSֱ<53>ӵ<EFBFBD><D3B5>뼴<EFBFBD>ɱ<EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.5
|
||||
DMA_LINK<4E>ṹ<EFBFBD><E1B9B9>linked_list<73><74>Աȡ<D4B1><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>ɶ<EFBFBD><C9B6><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ָ<EFBFBD><D6B8>
|
||||
dma_link_list<73>ṹ<EFBFBD>嶨<EFBFBD><E5B6A8><EFBFBD><EFBFBD><EFBFBD>Ӷ<EFBFBD><D3B6><EFBFBD>
|
||||
|
||||
V1.1.4
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>ע<EFBFBD>ͱ<EFBFBD><CDB1><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>µ<EFBFBD>һ<EFBFBD><D2BB>ע<EFBFBD>ͱ<EFBFBD><CDB1>Զ<EFBFBD><D4B6>۵<EFBFBD><DBB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.6
|
||||
<20><EFBFBD>printf<EFBFBD><EFBFBD>Ϊͨ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>л<EFBFBD>ΪADS<44>Ĺ<EFBFBD><C4B9>̣<EFBFBD>ADSֱ<53>ӵ<EFBFBD><D3B5>뼴<EFBFBD>ɱ<EFBFBD><C9B1><EFBFBD>
|
||||
V1.1.3
|
||||
<20><EFBFBD>SPI spi_mosi<73><69><EFBFBD><EFBFBD><EFBFBD>ڽ<EFBFBD><DABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>յ<EFBFBD>ʱ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>쳣
|
||||
|
||||
V1.1.7
|
||||
<20><EFBFBD><EFBFBD>Ӵ<EFBFBD><EFBFBD>ڰ汾<EFBFBD><EFBFBD>С<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD>ͱ<EFBFBD><CDB1><EFBFBD>ͨ<EFBFBD><CDA8>ö<EFBFBD><C3B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6><EFBFBD>
|
||||
V1.1.2
|
||||
<20><EFBFBD>ATOM_PWM<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>쳣<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.1
|
||||
<20><EFBFBD>uart_getchar<61><72><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD>ס<EFBFBD><D7A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.1.0
|
||||
<20><>ISR<53>ļ<EFBFBD><C4BC>ڵ<EFBFBD><DAB5>жϺ<D0B6><CFBA><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>enableInterrupts(); <20><>ʵ<EFBFBD><CAB5><EFBFBD>ж<EFBFBD>Ƕ<EFBFBD>Ĺ<D7B5><C4B9><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD>RDA5807<30><37>ȡRSSI<53><49><EFBFBD>ܺ<EFBFBD><DCBA><EFBFBD>
|
||||
<20><>DMA<4D><41><EFBFBD>Ӵ<EFBFBD><D3B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>õ<EFBFBD><C3B5>ı<EFBFBD><C4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ERU_DMA_INT_SERVICE<43><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ŵ<EFBFBD><C5B5><EFBFBD>Ӧ<EFBFBD><D3A6>CPU<50><55>
|
||||
|
||||
V1.0.9
|
||||
<20><EFBFBD>RDA5807<30><37><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA>֤<EFBFBD>ϵ<EFBFBD><CFB5><EFBFBD>1S<31>ڲ<EFBFBD><DAB2><EFBFBD>FMģ<4D><C4A3>
|
||||
|
||||
V1.0.8
|
||||
<20><EFBFBD>CCU61 ͨ<><CDA8>1<EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>ô<EFBFBD><C3B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><EFBFBD>CCU6<55><36><EFBFBD>ߵ<EFBFBD><DFB5>Ե<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD>ֹͣ<CDA3><D6B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߵ<EFBFBD><DFB5><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϵ<D0B6><CFB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><>CCU6<55><36><EFBFBD><EFBFBD>pit_close<73><65>pit_start<72><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڿ<EFBFBD><DABF>ƶ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>Ŀ<EFBFBD>ʼ<EFBFBD><CABC>ֹͣ
|
||||
<20><>CCU6<55><36><EFBFBD><EFBFBD>pit_disable_interrupt<70><74>pit_enable_interrupt<70><74><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڿ<EFBFBD><DABF><EFBFBD><EFBFBD>жϿ<D0B6><CFBF><EFBFBD>
|
||||
|
||||
V1.0.7
|
||||
<20><EFBFBD>ʹ<EFBFBD><CAB9>systick_getval<61><6C>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱʱ<CAB1>䳬<EFBFBD><E4B3AC>4<EFBFBD><34><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>⡣
|
||||
<20>Բ<EFBFBD><D4B2>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>#pragma warning<6E><67><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ż<EFBFBD><C5BB>ȼ<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>־<EFBFBD><D6BE><EFBFBD>
|
||||
<20><EFBFBD>1.8<EFBFBD><EFBFBD>TFT<EFBFBD><EFBFBD>Ļ<EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD><EFBFBD>й<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ļ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD>ֵĴ<EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.6
|
||||
<20><><EFBFBD><EFBFBD>ADC<44><43><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD>õĺ궨<C4BA>壬ADC_SAMPLE_FREQUENCY<43><59><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ10Mhz<68><7A><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC><EFBFBD>µ<EFBFBD><C2B5>ٶ<EFBFBD><D9B6>нϴ<D0BD><CFB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.5
|
||||
ȡ<><C8A1>HEX<45><58><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.4
|
||||
Ĭ<>Ϲ<EFBFBD>ѡ<EFBFBD><D1A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HEX<45>Ĺ<EFBFBD><C4B9><EFBFBD>
|
||||
<20><>Cpu1_Main.c<>е<EFBFBD>core1_main<69><6E><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϵĺ<CFB5><C4BA><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><EFBFBD>CPU1<55><EFBFBD><DEB7><EFBFBD>Ӧ<EFBFBD>жϵ<D0B6><CFB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
ɾ<><C9BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>еİ<D0B5><C4B0><EFBFBD>·<EFBFBD><C2B7><EFBFBD><EFBFBD>Ϣ
|
||||
<20><EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD>ֱ<EFBFBD>ֻ<EFBFBD>ɼ<EFBFBD>һ<EFBFBD>ε<EFBFBD><CEB5><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD>RDA5807 FMģ<4D><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><EFBFBD>LSL<53>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8>#pragma <20><>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߳<EFBFBD><DFB3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>RAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD>ο<EFBFBD><CEBF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Specifies_Variable_Or_Code_Location_Demo
|
||||
//ʹ<><CAB9>#pragma section all "cpu0_dsram" <20><> #pragma section all restore<72><65><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram
|
||||
//<2F><><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>仰<EFBFBD>м伴<D0BC>ɣ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
#pragma section all "cpu0_dsram"
|
||||
uint8 test_arry[5]; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_dsram<61><6D>Ϊcpu1_dsram <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu1_dsram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>CPUִ<55>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʹ<EFBFBD>õı<C3B5><C4B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>±<EFBFBD><C2B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu1_dsram<61><6D><EFBFBD><EFBFBD>
|
||||
#pragma section all restore
|
||||
|
||||
//ʹ<><CAB9>#pragma section all "cpu0_psram" <20><> #pragma section all restore<72><65><EFBFBD>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu0_psram
|
||||
//<2F><><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>仰<EFBFBD>м伴<D0BC>ɣ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
#pragma section all "cpu0_psram"
|
||||
void delay_tset(void) //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu0_psram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4>
|
||||
{
|
||||
int i;
|
||||
i = 999;
|
||||
while(i--);
|
||||
}
|
||||
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cpu0_psram<61><6D>Ϊcpu1_psram <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD>cpu1_psram<61><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
//<2F><><EFBFBD>ǽ<EFBFBD><C7BD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ĸ<EFBFBD>CPUִ<55>У<EFBFBD><D0A3><EFBFBD><F2BDABBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD>ĸ<EFBFBD><C4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڣ<EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>£<EFBFBD><C2A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ǵ<EFBFBD>flash<73><68><EFBFBD>ز<EFBFBD>ִ<EFBFBD><D6B4>
|
||||
//ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD>Ƕ<EFBFBD><C7B6><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAM<41><4D><EFBFBD>У<EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD>еij<D0B5><C4B3><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>cache<68><EFBFBD><F3A3ACBB><EFBFBD><EFBFBD>ֳ<EFBFBD><D6B3><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD>ٶȽ<D9B6><C8BD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ǾͿ<C7BE><CDBF>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAMִ<4D>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٶ<EFBFBD>
|
||||
#pragma section all restore
|
||||
|
||||
V1.0.3
|
||||
<20><>spi<70><69>uart<72><74>pit<69>в<EFBFBD><D0B2>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>volatile<6C><65><EFBFBD>Σ<EFBFBD><CEA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.2
|
||||
<20><EFBFBD>ģ<EFBFBD><C4A3>IICĬ<43><C4AC><EFBFBD><EFBFBD>ʱʱ<CAB1><CAB1>Ϊ20
|
||||
<20><><EFBFBD><EFBFBD> <20><>Ҫ<EFBFBD>ر<EFBFBD>ע<EFBFBD><D7A2>P20_2<5F>Dz<EFBFBD><C7B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĺ<EFBFBD><C4B9><EFBFBD> ע<><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ɼ<EFBFBD>DMA<4D><41>Ϊlink<6E><6B><EFBFBD>䣬<EFBFBD><E4A3AC><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>DMA<4D>жϴ<D0B6><CFB4><EFBFBD>
|
||||
<20><EFBFBD>Ĭ<EFBFBD>ϵ<EFBFBD><CFB5><EFBFBD><EFBFBD><EFBFBD>IIC<49><43><EFBFBD>Ŷ<EFBFBD><C5B6><EFBFBD>
|
||||
<20><>6050<35><30> <20><>Ҫ<EFBFBD>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD>IIC<49><43>ģ<EFBFBD>飬<EFBFBD>ڳ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD>ϵ<EFBFBD><CFB5><EFBFBD>ģ<EFBFBD><C4A3>IIC<49><43>ʼ<EFBFBD><CABC>
|
||||
<20><><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.1
|
||||
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD>ij<EFBFBD><C4B3>жϽ<D0B6><CFBD><EFBFBD><EFBFBD>ģ<DEB8><C4A3>жϱ<D0B6>־λΪ0<CEAA>Ųɼ<C5B2><C9BC><EFBFBD>һ<EFBFBD><D2BB>ͼ<EFBFBD><EFBFBD><F1A3ACB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>ʳ<EFBFBD>ͻ
|
||||
<20><EFBFBD>SPI<50><49>ʼ<EFBFBD><CABC><EFBFBD>еĴ<D0B5><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˹̶<CBB9><CCB6><EFBFBD>SPI2<49><32><EFBFBD><EFBFBD>ַ
|
||||
<20><EFBFBD>STM<54><4D><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>STM1<4D><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
<20><EFBFBD>gtm pwm<77><6D><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ռ<EFBFBD>ձ<EFBFBD>ֻ<EFBFBD><D6BB>GTM_ATOM0_PWM_DUTY_MAX<41><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
|
||||
V1.0.0
|
||||
<20><>ʼ<EFBFBD>汾
|
||||
@@ -0,0 +1,53 @@
|
||||
/**********************************************************************************************************************
|
||||
* \file Ifx_Cfg.h
|
||||
* \brief Project configuration file.
|
||||
* \copyright Copyright (C) Infineon Technologies AG 2019
|
||||
*
|
||||
* Use of this file is subject to the terms of use agreed between (i) you or the company in which ordinary course of
|
||||
* business you are acting and (ii) Infineon Technologies AG or its licensees. If and as long as no such terms of use
|
||||
* are agreed, use of this file is subject to following:
|
||||
*
|
||||
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the software and
|
||||
* accompanying documentation covered by this license (the "Software") to use, reproduce, display, distribute, execute,
|
||||
* and transmit the Software, and to prepare derivative works of the Software, and to permit third-parties to whom the
|
||||
* Software is furnished to do so, all subject to the following:
|
||||
*
|
||||
* The copyright notices in the Software and this entire statement, including the above license grant, this restriction
|
||||
* and the following disclaimer, must be included in all copies of the Software, in whole or in part, and all
|
||||
* derivative works of the Software, unless such copies or derivative works are solely in the form of
|
||||
* machine-executable object code generated by a source language processor.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
|
||||
* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*********************************************************************************************************************/
|
||||
|
||||
#ifndef IFX_CFG_H
|
||||
#define IFX_CFG_H 1
|
||||
#include "TC264_config.h"
|
||||
|
||||
/*********************************************************************************************************************/
|
||||
/*------------------------------------------Configuration for IfxScu_cfg.h-------------------------------------------*/
|
||||
/*********************************************************************************************************************/
|
||||
/* External oscillator frequency in Hz */
|
||||
#define IFX_CFG_SCU_XTAL_FREQUENCY (20000000) /* Allowed values are: 16000000, 20000000 or 40000000 */
|
||||
/* PLL frequency in Hz */
|
||||
#define IFX_CFG_SCU_PLL_FREQUENCY (200000000) /* Allowed values are: 80000000, 133000000, 160000000
|
||||
* or 200000000 */
|
||||
|
||||
/*********************************************************************************************************************/
|
||||
/*-----------------------------------Configuration for Software managed interrupt------------------------------------*/
|
||||
/*********************************************************************************************************************/
|
||||
/* #define IFX_USE_SW_MANAGED_INT */ /* Decomment this line if the project needs to use Software managed interrupts */
|
||||
|
||||
/*********************************************************************************************************************/
|
||||
/*---------------------------------Configuration for Trap Hook Functions' Extensions---------------------------------*/
|
||||
/*********************************************************************************************************************/
|
||||
/* #define IFX_CFG_EXTEND_TRAP_HOOKS */ /* Decomment this line if the project needs to extend trap hook functions */
|
||||
|
||||
#endif /* IFX_CFG_H */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user