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V3.1.4

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增加DL1A测距模块相关驱动文件
This commit is contained in:
SEEKFREE_BUDING
2022-12-28 18:45:21 +08:00
parent 739d228755
commit a6bed10c3a
60 changed files with 14310 additions and 0 deletions
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2
Example/E03_adc_demo/libraries/doc/version.txt
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@@ -1,3 +1,5 @@
V3.1.4
<20><><EFBFBD><EFBFBD>DL1A<31><41><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD>
V3.1.3
<20>޸<EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD>ע<EFBFBD><D7A2><EFBFBD>Լ<EFBFBD>ʹ<EFBFBD><CAB9>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
V3.1.2

1
Example/E03_adc_demo/libraries/zf_common/zf_common_headfile.h
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@@ -83,6 +83,7 @@
#include "zf_device_bluetooth_ch9141.h"
#include "zf_device_gps_tau1201.h"
#include "zf_device_camera.h"
#include "zf_device_dl1a.h"
#include "zf_device_icm20602.h"
#include "zf_device_imu660ra.h"
#include "zf_device_imu963ra.h"

752
Example/E03_adc_demo/libraries/zf_device/zf_device_dl1a.c Normal file
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@@ -0,0 +1,752 @@
/*********************************************************************************************************************
* TC264 Opensourec Library <20><><EFBFBD><EFBFBD>TC264 <20><>Դ<EFBFBD>⣩<EFBFBD><E2A3A9>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ڹٷ<DAB9> SDK <20>ӿڵĵ<DAB5><C4B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>
* Copyright (c) 2022 SEEKFREE <20><><EFBFBD>ɿƼ<C9BF>
*
* <20><><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD> TC264 <20><>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>
*
* TC264 <20><>Դ<EFBFBD><D4B4> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <20><><EFBFBD><EFBFBD><EFBFBD>Ը<EFBFBD><D4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ᷢ<EFBFBD><E1B7A2><EFBFBD><EFBFBD> GPL<50><4C>GNU General Public License<73><65><EFBFBD><EFBFBD> GNUͨ<55>ù<EFBFBD><C3B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֤<EFBFBD><D6A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <20><> GPL <20>ĵ<EFBFBD>3<EFBFBD>棨<EFBFBD><E6A3A8> GPL3.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><EFBFBD>κκ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>İ汾<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<2F><><EFBFBD>޸<EFBFBD><DEB8><EFBFBD>
*
* <20><><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>ķ<EFBFBD><C4B7><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>ܷ<EFBFBD><DCB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3><EFBFBD><EFBFBD><EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>κεı<CEB5>֤
* <20><><EFBFBD><EFBFBD>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ի<EFBFBD><D4BB>ʺ<EFBFBD><CABA>ض<EFBFBD><D8B6><EFBFBD>;<EFBFBD>ı<EFBFBD>֤
* <20><><EFBFBD><EFBFBD>ϸ<EFBFBD><CFB8><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> GPL
*
* <20><>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>ͬʱ<CDAC>յ<EFBFBD>һ<EFBFBD><D2BB> GPL <20>ĸ<EFBFBD><C4B8><EFBFBD>
* <20><><EFBFBD><EFBFBD>û<EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><https://www.gnu.org/licenses/>
*
* <20><><EFBFBD><EFBFBD>ע<EFBFBD><D7A2><EFBFBD><EFBFBD>
* <20><><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>ʹ<EFBFBD><CAB9> GPL3.0 <20><>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>֤Э<D6A4><D0AD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD>İ汾
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӣ<EFBFBD>İ<EFBFBD><C4B0><EFBFBD> libraries/doc <20>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD>µ<EFBFBD> GPL3_permission_statement.txt <20>ļ<EFBFBD><C4BC><EFBFBD>
* <20><><EFBFBD><EFBFBD>֤<EFBFBD><D6A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD> libraries <20>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD>µ<EFBFBD> LICENSE <20>ļ<EFBFBD>
* <20><>ӭ<EFBFBD><D3AD>λʹ<CEBB>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>޸<EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>뱣<EFBFBD><EBB1A3><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC>İ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*
* <20>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD> zf_device_dl1a
* <20><>˾<EFBFBD><CBBE><EFBFBD><EFBFBD> <20>ɶ<EFBFBD><C9B6><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* <20>汾<EFBFBD><E6B1BE>Ϣ <20>鿴 libraries/doc <20>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD> version <20>ļ<EFBFBD> <20>汾˵<E6B1BE><CBB5>
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ADS v1.8.0
* <20><><EFBFBD><EFBFBD>ƽ̨ TC264D
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> https://seekfree.taobao.com/
*
* <20>޸ļ<DEB8>¼
* <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><>ע
* 2022-09-15 pudding first version
********************************************************************************************************************/
/*********************************************************************************************************************
* <20><><EFBFBD>߶<EFBFBD><DFB6>壺
* ------------------------------------
* ģ<><C4A3><EFBFBD>ܽ<EFBFBD> <20><>Ƭ<EFBFBD><C6AC><EFBFBD>ܽ<EFBFBD>
* SCL <20>鿴 zf_device_dl1a.h <20><> DL1A_SCL_PIN <20>궨<EFBFBD><EAB6A8>
* SDA <20>鿴 zf_device_dl1a.h <20><> DL1A_SDA_PIN <20>궨<EFBFBD><EAB6A8>
* VCC 5V <20><>Դ
* GND <20><>Դ<EFBFBD><D4B4>
* ------------------------------------
********************************************************************************************************************/
#include "zf_common_debug.h"
#include "zf_driver_delay.h"
#include "zf_driver_soft_iic.h"
#include "zf_device_dl1a.h"
uint8 dl1a_finsh_flag;
uint16 dl1a_distance_mm;
#if DL1A_USE_SOFT_IIC
static soft_iic_info_struct dl1a_iic_struct;
#define dl1a_write_array(data, len) (soft_iic_write_8bit_array(&dl1a_iic_struct, (data), (len)))
#define dl1a_write_register(reg, data) (soft_iic_write_8bit_register(&dl1a_iic_struct, (reg), (data)))
#define dl1a_read_register(reg) (soft_iic_read_8bit_register(&dl1a_iic_struct, (reg)))
#define dl1a_read_registers(reg, data, len) (soft_iic_read_8bit_registers(&dl1a_iic_struct, (reg), (data), (len)))
#else
#define dl1a_write_array(data, len) (iic_write_8bit_array(DL1A_IIC, DL1A_DEV_ADDR, (data), (len)))
#define dl1a_write_register(reg, data) (iic_write_8bit_register(DL1A_IIC, DL1A_DEV_ADDR, (reg), (data)))
#define dl1a_read_register(reg) (iic_read_8bit_register(DL1A_IIC, DL1A_DEV_ADDR, (reg)))
#define dl1a_read_registers(reg, data, len) (iic_read_8bit_registers(DL1A_IIC, DL1A_DEV_ADDR, (reg), (data), (len)))
#endif
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ʾ<EFBFBD><CABE>Ŀ<EFBFBD>귴<EFBFBD>䲢<EFBFBD><E4B2A2><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD>⵽<EFBFBD><E2B5BD><EFBFBD>źŵ<C5BA><C5B5><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD>ô<EFBFBD><C3B4><EFBFBD><EFBFBD>ƿ<EFBFBD><C6BF><EFBFBD>ȷ<EFBFBD><C8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD>ֵ
// <20><><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD>ϵ͵<CFB5><CDB5><EFBFBD><EFBFBD>ƿ<EFBFBD><C6BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӵ<EFBFBD><D3B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IJ<EFBFBD><C4B2><EFBFBD><EFBFBD><EFBFBD>Χ
// <20><><EFBFBD>ƺ<EFBFBD>Ҳ<EFBFBD><D2B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <<3C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IJ<EFBFBD><C4B2><EFBFBD>Ҫ<EFBFBD>ķ<EFBFBD><C4B7>䵼<EFBFBD><E4B5BC>> <20>õ<EFBFBD><C3B5><EFBFBD>׼ȷ<D7BC><C8B7><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD><EFBFBD><EFBFBD>
// Ĭ<><C4AC>Ϊ 0.25 MCPS <20><>Ԥ<EFBFBD>跶ΧΪ 0 - 511.99
#define DL1A_DEFAULT_RATE_LIMIT (0.25)
// <20>ӼĴ<D3BC><C4B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ݽ<EFBFBD><DDBD><EFBFBD> PCLKs <20><> VCSEL (vertical cavity surface emitting laser) <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define decode_vcsel_period(reg_val) (((reg_val) + 1) << 1)
// <20><> PCLK <20>е<EFBFBD> VCSEL <20><><EFBFBD>ڼ<EFBFBD><DABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (<28><> *<2A><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>λ)
// PLL_period_ps = 1655
// macro_period_vclks = 2304
#define calc_macro_period(vcsel_period_pclks) ((((uint32)2304 * (vcsel_period_pclks) * 1655) + 500) / 1000)
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ȡ<EFBFBD>豸 SPAD <20><>Ϣ
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> index <20><><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> type <20><><EFBFBD><EFBFBD>ֵ
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> uint8 <20>Ƿ<EFBFBD><C7B7>ɹ<EFBFBD> 0-<2D>ɹ<EFBFBD> 1-ʧ<><CAA7>
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dl1a_get_spad_info(index, type_is_aperture);
// <20><>ע<EFBFBD><D7A2>Ϣ
//-------------------------------------------------------------------------------------------------------------------
static uint8 dl1a_get_spad_info (uint8 *index, uint8 *type_is_aperture)
{
uint8 tmp = 0;
uint8 return_state = 0;
volatile uint16 loop_count = 0;
do
{
dl1a_write_register(0x80, 0x01);
dl1a_write_register(0xFF, 0x01);
dl1a_write_register(0x00, 0x00);
dl1a_write_register(0xFF, 0x06);
dl1a_read_registers(0x83, &tmp, 1);
dl1a_write_register(0x83, tmp | 0x04);
dl1a_write_register(0xFF, 0x07);
dl1a_write_register(0x81, 0x01);
dl1a_write_register(0x80, 0x01);
dl1a_write_register(0x94, 0x6b);
dl1a_write_register(0x83, 0x00);
tmp = 0x00;
while(tmp == 0x00 || tmp == 0xFF)
{
system_delay_ms(1);
dl1a_read_registers(0x83, &tmp, 1);
if(loop_count++ > DL1A_TIMEOUT_COUNT)
{
return_state = 1;
break;
}
}
if(return_state)
{
break;
}
dl1a_write_register(0x83, 0x01);
dl1a_read_registers(0x92, &tmp, 1);
*index = tmp & 0x7f;
*type_is_aperture = (tmp >> 7) & 0x01;
dl1a_write_register(0x81, 0x00);
dl1a_write_register(0xFF, 0x06);
dl1a_read_registers(0x83, &tmp, 1);
dl1a_write_register(0x83, tmp);
dl1a_write_register(0xFF, 0x01);
dl1a_write_register(0x00, 0x01);
dl1a_write_register(0xFF, 0x00);
dl1a_write_register(0x80, 0x00);
}while(0);
return return_state;
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ֵ<EFBFBD><D6B5> MCLKs ת<><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6> ms
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> timeout_period_mclks <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> MCLKs
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> vcsel_period_pclks PCLK ֵ
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> uint32 <20><><EFBFBD>س<EFBFBD>ʱ<EFBFBD><CAB1>ֵ
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dl1a_timeout_mclks_to_microseconds(timeout_period_mclks, vcsel_period_pclks);
// <20><>ע<EFBFBD><D7A2>Ϣ <20><><EFBFBD><EFBFBD><EFBFBD>в<EFBFBD><D0B2>賬ʱ<E8B3AC>Ӿ<EFBFBD><D3BE>и<EFBFBD><D0B8><EFBFBD> VCSEL <20><><EFBFBD>ڵ<EFBFBD> MCLK (<28><> PCLK Ϊ<><CEAA>λ)ת<><D7AA>Ϊ΢<CEAA><CEA2>
//-------------------------------------------------------------------------------------------------------------------
static uint32 dl1a_timeout_mclks_to_microseconds (uint16 timeout_period_mclks, uint8 vcsel_period_pclks)
{
uint32 macro_period_ns = calc_macro_period(vcsel_period_pclks);
return ((timeout_period_mclks * macro_period_ns) + (macro_period_ns / 2)) / 1000;
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ֵ<EFBFBD><D6B5> ms ת<><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6> MCLKs
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> timeout_period_us <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> ΢<>뵥λ
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> vcsel_period_pclks PCLK ֵ
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> uint32 <20><><EFBFBD>س<EFBFBD>ʱ<EFBFBD><CAB1>ֵ
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dl1a_timeout_microseconds_to_mclks(timeout_period_us, vcsel_period_pclks);
// <20><>ע<EFBFBD><D7A2>Ϣ <20><><EFBFBD><EFBFBD><EFBFBD>в<EFBFBD><D0B2>賬ʱ<E8B3AC><CAB1>΢<EFBFBD><CEA2>ת<EFBFBD><D7AA>Ϊ<EFBFBD><CEAA><EFBFBD>и<EFBFBD><D0B8><EFBFBD> VCSEL <20><><EFBFBD>ڵ<EFBFBD> MCLK (<28><> PCLK Ϊ<><CEAA>λ)
//-------------------------------------------------------------------------------------------------------------------
static uint32 dl1a_timeout_microseconds_to_mclks (uint32 timeout_period_us, uint8 vcsel_period_pclks)
{
uint32 macro_period_ns = calc_macro_period(vcsel_period_pclks);
return (((timeout_period_us * 1000) + (macro_period_ns / 2)) / macro_period_ns);
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>Գ<EFBFBD>ʱ<EFBFBD><CAB1>ֵ<EFBFBD><D6B5><EFBFBD>н<EFBFBD><D0BD><EFBFBD>
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> reg_val <20><>ʱʱ<CAB1><CAB1> <20>Ĵ<EFBFBD><C4B4><EFBFBD>ֵ
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> uint16 <20><><EFBFBD>س<EFBFBD>ʱ<EFBFBD><CAB1>ֵ
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dl1a_decode_timeout(reg_val);
// <20><>ע<EFBFBD><D7A2>Ϣ <20>ӼĴ<D3BC><C4B4><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD> MCLK <20>е<EFBFBD><D0B5><EFBFBD><EFBFBD>в<EFBFBD><D0B2>賬ʱ
//-------------------------------------------------------------------------------------------------------------------
static uint16 dl1a_decode_timeout (uint16 reg_val)
{
// <20><>ʽ: (LSByte * 2 ^ MSByte) + 1
return (uint16)((reg_val & 0x00FF) <<
(uint16)((reg_val & 0xFF00) >> 8)) + 1;
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>Գ<EFBFBD>ʱ<EFBFBD><CAB1>ֵ<EFBFBD><D6B5><EFBFBD>б<EFBFBD><D0B1><EFBFBD>
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> timeout_mclks <20><>ʱʱ<CAB1><CAB1> -MCLKs ֵ
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> uint16 <20><><EFBFBD>ر<EFBFBD><D8B1><EFBFBD>ֵ
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dl1a_encode_timeout(timeout_mclks);
// <20><>ע<EFBFBD><D7A2>Ϣ <20><> MCLK <20>жԳ<D0B6>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>в<EFBFBD><D0B2>賬ʱ<E8B3AC>Ĵ<EFBFBD><C4B4><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD>б<EFBFBD><D0B1><EFBFBD>
//-------------------------------------------------------------------------------------------------------------------
static uint16 dl1a_encode_timeout (uint16 timeout_mclks)
{
uint32 ls_byte = 0;
uint16 ms_byte = 0;
uint16 return_data = 0;
if (timeout_mclks > 0)
{
// <20><>ʽ: (LSByte * 2 ^ MSByte) + 1
ls_byte = timeout_mclks - 1;
while ((ls_byte & 0xFFFFFF00) > 0)
{
ls_byte >>= 1;
ms_byte++;
}
return_data = (ms_byte << 8) | ((uint16)ls_byte & 0xFF);
}
return return_data;
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ȡ<EFBFBD><C8A1><EFBFBD>в<EFBFBD><D0B2><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> enables <20><><EFBFBD><EFBFBD>ʹ<EFBFBD>ܲ<EFBFBD><DCB2><EFBFBD><EFBFBD>ṹ<EFBFBD><E1B9B9>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> void
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dl1a_get_sequence_step_enables(enables);
// <20><>ע<EFBFBD><D7A2>Ϣ
//-------------------------------------------------------------------------------------------------------------------
static void dl1a_get_sequence_step_enables(dl1a_sequence_enables_step_struct *enables)
{
uint8 sequence_config = 0;
dl1a_read_registers(DL1A_SYSTEM_SEQUENCE_CONFIG, &sequence_config, 1);
enables->tcc = (sequence_config >> 4) & 0x1;
enables->dss = (sequence_config >> 3) & 0x1;
enables->msrc = (sequence_config >> 2) & 0x1;
enables->pre_range = (sequence_config >> 6) & 0x1;
enables->final_range = (sequence_config >> 7) & 0x1;
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> type Ԥ<><D4A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> uint8 <20><><EFBFBD>ص<EFBFBD><D8B5><EFBFBD><EFBFBD><EFBFBD>ֵ
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dl1a_get_vcsel_pulse_period(DL1A_VCSEL_PERIOD_PER_RANGE);
// <20><>ע<EFBFBD><D7A2>Ϣ <20><> PCLKs <20>л<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD> VCSEL <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//-------------------------------------------------------------------------------------------------------------------
static uint8 dl1a_get_vcsel_pulse_period (dl1a_vcsel_period_type_enum type)
{
uint8 data_buffer = 0;
if (type == DL1A_VCSEL_PERIOD_PER_RANGE)
{
dl1a_read_registers(DL1A_PRE_RANGE_CONFIG_VCSEL_PERIOD, &data_buffer, 1);
data_buffer = decode_vcsel_period(data_buffer);
}
else if (type == DL1A_VCSEL_PERIOD_FINAL_RANGE)
{
dl1a_read_registers(DL1A_FINAL_RANGE_CONFIG_VCSEL_PERIOD, &data_buffer, 1);
data_buffer = decode_vcsel_period(data_buffer);
}
else
{
data_buffer = 255;
}
return data_buffer;
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ȡ<EFBFBD><C8A1><EFBFBD>в<EFBFBD><D0B2>賬ʱ<E8B3AC><CAB1><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> enables <20><><EFBFBD><EFBFBD>ʹ<EFBFBD>ܲ<EFBFBD><DCB2><EFBFBD><EFBFBD>ṹ<EFBFBD><E1B9B9>
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> timeouts <20><><EFBFBD>г<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ṹ<EFBFBD><E1B9B9>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> void
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dl1a_get_sequence_step_timeouts(enables, timeouts);
// <20><>ע<EFBFBD><D7A2>Ϣ <20><>ȡ<EFBFBD><C8A1><EFBFBD>г<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ij<EFBFBD>ʱ <20><><EFBFBD>һ<EFBFBD><D2BB>洢<EFBFBD>м<EFBFBD>ֵ
//-------------------------------------------------------------------------------------------------------------------
static void dl1a_get_sequence_step_timeouts (dl1a_sequence_enables_step_struct const *enables, dl1a_sequence_timeout_step_struct *timeouts)
{
uint8 reg_buffer[2];
uint16 reg16_buffer = 0;
timeouts->pre_range_vcsel_period_pclks = dl1a_get_vcsel_pulse_period(DL1A_VCSEL_PERIOD_PER_RANGE);
dl1a_read_registers(DL1A_MSRC_CONFIG_TIMEOUT_MACROP, reg_buffer, 1);
timeouts->msrc_dss_tcc_mclks = reg_buffer[0] + 1;
timeouts->msrc_dss_tcc_us = dl1a_timeout_mclks_to_microseconds(timeouts->msrc_dss_tcc_mclks, (uint8)timeouts->pre_range_vcsel_period_pclks);
dl1a_read_registers(DL1A_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI, reg_buffer, 2);
reg16_buffer = ((uint16) reg_buffer[0] << 8) | reg_buffer[1];
timeouts->pre_range_mclks = dl1a_decode_timeout(reg16_buffer);
timeouts->pre_range_us = dl1a_timeout_mclks_to_microseconds(timeouts->pre_range_mclks, (uint8)timeouts->pre_range_vcsel_period_pclks);
timeouts->final_range_vcsel_period_pclks = dl1a_get_vcsel_pulse_period(DL1A_VCSEL_PERIOD_FINAL_RANGE);
dl1a_read_registers(DL1A_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI, reg_buffer, 2);
reg16_buffer = ((uint16) reg_buffer[0] << 8) | reg_buffer[1];
timeouts->final_range_mclks = dl1a_decode_timeout(reg16_buffer);
if (enables->pre_range)
{
timeouts->final_range_mclks -= timeouts->pre_range_mclks;
}
timeouts->final_range_us = dl1a_timeout_mclks_to_microseconds(timeouts->final_range_mclks, (uint8)timeouts->final_range_vcsel_period_pclks);
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ִ<>е<EFBFBD><D0B5>βο<CEB2>У׼
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> vhv_init_byte Ԥ<><D4A4>У׼ֵ
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> uint8 <20><><EFBFBD><EFBFBD><EFBFBD>Ƿ<EFBFBD><C7B7>ɹ<EFBFBD> 0-<2D>ɹ<EFBFBD> 1-ʧ<><CAA7>
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dl1a_get_vcsel_pulse_period(DL1A_VCSEL_PERIOD_PER_RANGE);
// <20><>ע<EFBFBD><D7A2>Ϣ <20><> PCLKs <20>л<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>͵<EFBFBD> VCSEL <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//-------------------------------------------------------------------------------------------------------------------
static uint8 dl1a_perform_single_ref_calibration (uint8 vhv_init_byte)
{
uint8 return_state = 0;
uint8 data_buffer = 0;
volatile uint16 loop_count = 0;
do
{
dl1a_write_register(DL1A_SYSRANGE_START, 0x01 | vhv_init_byte);
dl1a_read_registers(DL1A_MSRC_CONFIG_TIMEOUT_MACROP, &data_buffer, 1);
while ((data_buffer & 0x07) == 0)
{
system_delay_ms(1);
dl1a_read_registers(DL1A_MSRC_CONFIG_TIMEOUT_MACROP, &data_buffer, 1);
if (loop_count ++ > DL1A_TIMEOUT_COUNT)
{
return_state = 1;
break;
}
}
if(return_state)
{
break;
}
dl1a_write_register(DL1A_SYSTEM_INTERRUPT_CLEAR, 0x01);
dl1a_write_register(DL1A_SYSRANGE_START, 0x00);
}while(0);
return return_state;
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD>ʱԤ<CAB1><D4A4> (<28><>΢<EFBFBD><CEA2>Ϊ<EFBFBD><CEAA>λ)
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> budget_us <20>趨<EFBFBD>IJ<EFBFBD><C4B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> uint8 <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0-<2D>ɹ<EFBFBD> 1-ʧ<><CAA7>
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dl1a_set_measurement_timing_budget(measurement_timing_budget_us);
// <20><>ע<EFBFBD><D7A2>Ϣ <20><><EFBFBD><EFBFBD>һ<EFBFBD>β<EFBFBD><CEB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
// <20><><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>е<EFBFBD><D0B5>Ӳ<EFBFBD><D3B2><EFBFBD>֮<EFBFBD><D6AE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ԥ<EFBFBD><D4A4>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ԥ<EFBFBD><D4A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD>IJ<EFBFBD><C4B2><EFBFBD>
// <20><><EFBFBD><EFBFBD>һ<EFBFBD><D2BB>N<EFBFBD><4E><EFBFBD><EFBFBD>Ԥ<EFBFBD><D4A4><EFBFBD><EFBFBD><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD>һ<EFBFBD><D2BB>sqrt(N)<29><><EFBFBD>ķ<EFBFBD>Χ<EFBFBD><CEA7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>׼ƫ<D7BC><C6AB>
// Ĭ<><C4AC>Ϊ33<33><33><EFBFBD><EFBFBD> <20><>СֵΪ20 ms
//-------------------------------------------------------------------------------------------------------------------
static uint8 dl1a_set_measurement_timing_budget (uint32 budget_us)
{
uint8 return_state = 0;
uint8 data_buffer[3];
uint16 data = 0;
dl1a_sequence_enables_step_struct enables;
dl1a_sequence_timeout_step_struct timeouts;
do
{
if (budget_us < DL1A_MIN_TIMING_BUDGET)
{
return_state = 1;
break;
}
uint32 used_budget_us = DL1A_SET_START_OVERHEAD + DL1A_END_OVERHEAD;
dl1a_get_sequence_step_enables(&enables);
dl1a_get_sequence_step_timeouts(&enables, &timeouts);
if (enables.tcc)
{
used_budget_us += (timeouts.msrc_dss_tcc_us + DL1A_TCC_OVERHEAD);
}
if (enables.dss)
{
used_budget_us += 2 * (timeouts.msrc_dss_tcc_us + DL1A_DSS_OVERHEAD);
}
else if (enables.msrc)
{
used_budget_us += (timeouts.msrc_dss_tcc_us + DL1A_MSRC_OVERHEAD);
}
if (enables.pre_range)
{
used_budget_us += (timeouts.pre_range_us + DL1A_PRERANGE_OVERHEAD);
}
if (enables.final_range)
{
// <20><>ע<EFBFBD><D7A2> <20><><EFBFBD>շ<EFBFBD>Χ<EFBFBD><CEA7>ʱ<EFBFBD>ɼ<EFBFBD>ʱԤ<CAB1><D4A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>ܺ;<DCBA><CDBE><EFBFBD>
// <20><><EFBFBD><EFBFBD>û<EFBFBD>пռ<D0BF><D5BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>շ<EFBFBD>Χ<EFBFBD><CEA7>ʱ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ô<EFBFBD><C3B4><EFBFBD>
// <20><><EFBFBD><EFBFBD> ʣ<><CAA3>ʱ<EFBFBD>佫Ӧ<E4BDAB><D3A6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>շ<EFBFBD>Χ
used_budget_us += DL1A_FINALlRANGE_OVERHEAD;
if (used_budget_us > budget_us)
{
// <20><><EFBFBD><EFBFBD><EFBFBD>ij<EFBFBD>ʱ̫<CAB1><CCAB>
return_state = 1;
break;
}
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ճ<EFBFBD>ʱ<EFBFBD><CAB1>Χ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ԥ<EFBFBD><D4A4><EFBFBD>̷<EFBFBD>Χ<EFBFBD><CEA7>ʱ
// Ϊ<><CEAA> <20><><EFBFBD>ճ<EFBFBD>ʱ<EFBFBD><CAB1>Ԥ<EFBFBD><D4A4><EFBFBD>̳<EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>Ժ<EFBFBD><D4BA><EFBFBD><EFBFBD><EFBFBD> MClks <20><>ʾ
// <20><>Ϊ<EFBFBD><CEAA><EFBFBD>Ǿ<EFBFBD><C7BE>в<EFBFBD>ͬ<EFBFBD><CDAC> VCSEL <20><><EFBFBD><EFBFBD>
uint32 final_range_timeout_us = budget_us - used_budget_us;
uint16 final_range_timeout_mclks =
(uint16)dl1a_timeout_microseconds_to_mclks(final_range_timeout_us,
(uint8)timeouts.final_range_vcsel_period_pclks);
if (enables.pre_range)
{
final_range_timeout_mclks += timeouts.pre_range_mclks;
}
data = dl1a_encode_timeout(final_range_timeout_mclks);
data_buffer[0] = DL1A_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI;
data_buffer[1] = ((data >> 8) & 0xFF);
data_buffer[2] = (data & 0xFF);
dl1a_write_array(data_buffer, 3);
}
}while(0);
return return_state;
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱԤ<CAB1><D4A4> (<28><>΢<EFBFBD><CEA2>Ϊ<EFBFBD><CEAA>λ)
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> void
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> uint32 <20><><EFBFBD>趨<EFBFBD>IJ<EFBFBD><C4B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dl1a_get_measurement_timing_budget();
// <20><>ע<EFBFBD><D7A2>Ϣ
//-------------------------------------------------------------------------------------------------------------------
static uint32 dl1a_get_measurement_timing_budget (void)
{
dl1a_sequence_enables_step_struct enables;
dl1a_sequence_timeout_step_struct timeouts;
// <20><>ʼ<EFBFBD>ͽ<EFBFBD><CDBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>ʼ<EFBFBD>մ<EFBFBD><D5B4><EFBFBD>
uint32 budget_us = DL1A_GET_START_OVERHEAD + DL1A_END_OVERHEAD;
dl1a_get_sequence_step_enables(&enables);
dl1a_get_sequence_step_timeouts(&enables, &timeouts);
if (enables.tcc)
{
budget_us += (timeouts.msrc_dss_tcc_us + DL1A_TCC_OVERHEAD);
}
if (enables.dss)
{
budget_us += 2 * (timeouts.msrc_dss_tcc_us + DL1A_DSS_OVERHEAD);
}
else if (enables.msrc)
{
budget_us += (timeouts.msrc_dss_tcc_us + DL1A_MSRC_OVERHEAD);
}
if (enables.pre_range)
{
budget_us += (timeouts.pre_range_us + DL1A_PRERANGE_OVERHEAD);
}
if (enables.final_range)
{
budget_us += (timeouts.final_range_us + DL1A_FINALlRANGE_OVERHEAD);
}
return budget_us;
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>÷<EFBFBD><C3B7><EFBFBD><EFBFBD>ź<EFBFBD><C5BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ֵ<EFBFBD><D6B5>λΪ MCPS (<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ÿ<EFBFBD><C3BF>)
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> limit_mcps <20><><EFBFBD>õ<EFBFBD><C3B5><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD>
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> void
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dl1a_set_signal_rate_limit(0.25);
// <20><>ע<EFBFBD><D7A2>Ϣ <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD>ʾ<EFBFBD><CABE>Ŀ<EFBFBD>귴<EFBFBD>䲢<EFBFBD><E4B2A2><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD>⵽<EFBFBD><E2B5BD><EFBFBD>źŵ<C5BA><C5B5><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD>ô<EFBFBD><C3B4><EFBFBD><EFBFBD>ƿ<EFBFBD><C6BF><EFBFBD>ȷ<EFBFBD><C8B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1><EFBFBD><EFBFBD>ֵ
// <20><><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD>ϵ͵<CFB5><CDB5><EFBFBD><EFBFBD>ƿ<EFBFBD><C6BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӵ<EFBFBD><D3B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IJ<EFBFBD><C4B2><EFBFBD><EFBFBD><EFBFBD>Χ
// <20><><EFBFBD>ƺ<EFBFBD>Ҳ<EFBFBD><D2B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <<3C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>IJ<EFBFBD><C4B2><EFBFBD>Ҫ<EFBFBD>ķ<EFBFBD><C4B7>䵼<EFBFBD><E4B5BC>> <20>õ<EFBFBD><C3B5><EFBFBD>׼ȷ<D7BC><C8B7><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD><EFBFBD><EFBFBD>
// Ĭ<><C4AC>Ϊ 0.25 MCPS <20><>Ԥ<EFBFBD>跶ΧΪ 0 - 511.99
//-------------------------------------------------------------------------------------------------------------------
static void dl1a_set_signal_rate_limit (float limit_mcps)
{
zf_assert(limit_mcps >= 0 || limit_mcps <= 511.99);
uint8 data_buffer[3];
uint16 limit_mcps_16bit = (limit_mcps * (1 << 7));
data_buffer[0] = DL1A_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT;
data_buffer[1] = ((limit_mcps_16bit >> 8) & 0xFF);
data_buffer[2] = (limit_mcps_16bit & 0xFF);
dl1a_write_array(data_buffer, 3);
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>Ժ<EFBFBD><D4BA><EFBFBD>Ϊ<EFBFBD><CEAA>λ<EFBFBD>ķ<EFBFBD>Χ<EFBFBD><CEA7><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> void
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> void
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dl1a_get_distance();
// <20><>ע<EFBFBD><D7A2>Ϣ <20>ڿ<EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>̲<EFBFBD><CCB2><EFBFBD><EFBFBD><EFBFBD>Ҳ<EFBFBD><D2B2><EFBFBD>ô˺<C3B4><CBBA><EFBFBD>
//-------------------------------------------------------------------------------------------------------------------
void dl1a_get_distance (void)
{
uint8 reg_databuffer[3];
dl1a_read_registers(DL1A_RESULT_INTERRUPT_STATUS, reg_databuffer, 1);
if((reg_databuffer[0] & 0x07) != 0)
{
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Զ<EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΪĬ<CEAA><C4AC>ֵ 1000 <20><>δ<EFBFBD><CEB4><EFBFBD>÷<EFBFBD><C3B7><EFBFBD><EFBFBD><EFBFBD>Χ
dl1a_read_registers(DL1A_RESULT_RANGE_STATUS + 10, reg_databuffer, 2);
dl1a_distance_mm = ((uint16_t)reg_databuffer[0] << 8);
dl1a_distance_mm |= reg_databuffer[1];
dl1a_write_register(DL1A_SYSTEM_INTERRUPT_CLEAR, 0x01);
dl1a_finsh_flag = 1;
}
if(reg_databuffer[0] & 0x10)
{
dl1a_read_registers(DL1A_RESULT_RANGE_STATUS + 10, reg_databuffer, 2);
dl1a_write_register(DL1A_SYSTEM_INTERRUPT_CLEAR, 0x01);
}
}
//-------------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ʼ<EFBFBD><CABC> DL1A
// <20><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5> void
// <20><><EFBFBD>ز<EFBFBD><D8B2><EFBFBD> uint8 1-<2D><>ʼ<EFBFBD><CABC>ʧ<EFBFBD><CAA7> 0-<2D><>ʼ<EFBFBD><CABC><EFBFBD>ɹ<EFBFBD>
// ʹ<><CAB9>ʾ<EFBFBD><CABE> dl1a_init();
// <20><>ע<EFBFBD><D7A2>Ϣ
//-------------------------------------------------------------------------------------------------------------------
uint8 dl1a_init (void)
{
uint32 measurement_timing_budget_us;
uint8 stop_variable;
uint8 return_state = 0;
uint8 reg_data_buffer ;
uint8 ref_spad_map[6];
uint8 data_buffer[7];
memset(ref_spad_map, 0, 6);
memset(data_buffer, 0, 7);
#if DL1A_USE_SOFT_IIC
soft_iic_init(&dl1a_iic_struct, DL1A_DEV_ADDR, DL1A_SOFT_IIC_DELAY, DL1A_SCL_PIN, DL1A_SDA_PIN);
#else
iic_init(DL1A_IIC, DL1A_DEV_ADDR, DL1A_IIC_SPEED, DL1A_SCL_PIN, DL1A_SDA_PIN);
#endif
gpio_init(DL1A_XSHUT_PIN, GPO, GPIO_HIGH, GPO_PUSH_PULL);
do
{
system_delay_ms(100);
gpio_low(DL1A_XSHUT_PIN);
system_delay_ms(50);
gpio_high(DL1A_XSHUT_PIN);
system_delay_ms(100);
// -------------------------------- DL1A <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC> --------------------------------
reg_data_buffer = dl1a_read_register(DL1A_IO_VOLTAGE_CONFIG); // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC> IO Ϊ 1.8V ģʽ
dl1a_write_register(DL1A_IO_VOLTAGE_CONFIG, reg_data_buffer | 0x01); // <20><><EFBFBD><EFBFBD> IO Ϊ 2.8V ģʽ
dl1a_write_register(0x88, 0x00); // <20><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>׼ IIC ģʽ
dl1a_write_register(0x80, 0x01);
dl1a_write_register(0xFF, 0x01);
dl1a_write_register(0x00, 0x00);
dl1a_read_registers(0x91, &stop_variable , 1);
dl1a_write_register(0x00, 0x01);
dl1a_write_register(0xFF, 0x00);
dl1a_write_register(0x80, 0x00);
// <20><><EFBFBD><EFBFBD> SIGNAL_RATE_MSRC(bit1) <20><> SIGNAL_RATE_PRE_RANGE(bit4) <20><><EFBFBD>Ƽ<EFBFBD><C6BC><EFBFBD>
reg_data_buffer = dl1a_read_register(DL1A_MSRC_CONFIG);
dl1a_write_register(DL1A_MSRC_CONFIG, reg_data_buffer | 0x12);
dl1a_set_signal_rate_limit(DL1A_DEFAULT_RATE_LIMIT); // <20><><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD><C5BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
dl1a_write_register(DL1A_SYSTEM_SEQUENCE_CONFIG, 0xFF);
// -------------------------------- DL1A <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC> --------------------------------
// -------------------------------- DL1A <20><><EFBFBD>ó<EFBFBD>ʼ<EFBFBD><CABC> --------------------------------
if (dl1a_get_spad_info(&data_buffer[0], &data_buffer[1]))
{
return_state = 1;
zf_log(0, "DL1A self check error.");
break;
}
// <20><> GLOBAL_CONFIG_SPAD_ENABLES_REF_[0-6] <20><>ȡ SPAD map (RefGoodSpadMap) <20><><EFBFBD><EFBFBD>
dl1a_read_registers(DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_0, ref_spad_map, 6);
dl1a_write_register(0xFF, 0x01);
dl1a_write_register(DL1A_DYNAMIC_SPAD_REF_EN_START_OFFSET, 0x00);
dl1a_write_register(DL1A_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD, 0x2C);
dl1a_write_register(0xFF, 0x00);
dl1a_write_register(DL1A_GLOBAL_CONFIG_REF_EN_START_SELECT, 0xB4);
data_buffer[2] = data_buffer[1] ? 12 : 0; // 12 is the first aperture spad
for (uint8 i = 0; i < 48; i++)
{
if (i < data_buffer[2] || data_buffer[3] == data_buffer[0])
{
// <20><>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD>õĵ<C3B5>һ<EFBFBD><D2BB>λ
// <20><><EFBFBD><EFBFBD> (eference_spad_count) λ<><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD>˴<EFBFBD>λΪ<CEBB><CEAA>
ref_spad_map[i / 8] &= ~(1 << (i % 8));
}
else if ((ref_spad_map[i / 8] >> (i % 8)) & 0x1)
{
data_buffer[3]++;
}
}
data_buffer[0] = DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_0;
for(uint8 i = 1; i < 7; i++)
{
data_buffer[1] = ref_spad_map[i-1];
}
dl1a_write_array(data_buffer, 7);
// Ĭ<><C4AC>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD> version 02/11/2015_v36
dl1a_write_register(0xFF, 0x01);
dl1a_write_register(0x00, 0x00);
dl1a_write_register(0xFF, 0x00);
dl1a_write_register(0x09, 0x00);
dl1a_write_register(0x10, 0x00);
dl1a_write_register(0x11, 0x00);
dl1a_write_register(0x24, 0x01);
dl1a_write_register(0x25, 0xFF);
dl1a_write_register(0x75, 0x00);
dl1a_write_register(0xFF, 0x01);
dl1a_write_register(0x4E, 0x2C);
dl1a_write_register(0x48, 0x00);
dl1a_write_register(0x30, 0x20);
dl1a_write_register(0xFF, 0x00);
dl1a_write_register(0x30, 0x09);
dl1a_write_register(0x54, 0x00);
dl1a_write_register(0x31, 0x04);
dl1a_write_register(0x32, 0x03);
dl1a_write_register(0x40, 0x83);
dl1a_write_register(0x46, 0x25);
dl1a_write_register(0x60, 0x00);
dl1a_write_register(0x27, 0x00);
dl1a_write_register(0x50, 0x06);
dl1a_write_register(0x51, 0x00);
dl1a_write_register(0x52, 0x96);
dl1a_write_register(0x56, 0x08);
dl1a_write_register(0x57, 0x30);
dl1a_write_register(0x61, 0x00);
dl1a_write_register(0x62, 0x00);
dl1a_write_register(0x64, 0x00);
dl1a_write_register(0x65, 0x00);
dl1a_write_register(0x66, 0xA0);
dl1a_write_register(0xFF, 0x01);
dl1a_write_register(0x22, 0x32);
dl1a_write_register(0x47, 0x14);
dl1a_write_register(0x49, 0xFF);
dl1a_write_register(0x4A, 0x00);
dl1a_write_register(0xFF, 0x00);
dl1a_write_register(0x7A, 0x0A);
dl1a_write_register(0x7B, 0x00);
dl1a_write_register(0x78, 0x21);
dl1a_write_register(0xFF, 0x01);
dl1a_write_register(0x23, 0x34);
dl1a_write_register(0x42, 0x00);
dl1a_write_register(0x44, 0xFF);
dl1a_write_register(0x45, 0x26);
dl1a_write_register(0x46, 0x05);
dl1a_write_register(0x40, 0x40);
dl1a_write_register(0x0E, 0x06);
dl1a_write_register(0x20, 0x1A);
dl1a_write_register(0x43, 0x40);
dl1a_write_register(0xFF, 0x00);
dl1a_write_register(0x34, 0x03);
dl1a_write_register(0x35, 0x44);
dl1a_write_register(0xFF, 0x01);
dl1a_write_register(0x31, 0x04);
dl1a_write_register(0x4B, 0x09);
dl1a_write_register(0x4C, 0x05);
dl1a_write_register(0x4D, 0x04);
dl1a_write_register(0xFF, 0x00);
dl1a_write_register(0x44, 0x00);
dl1a_write_register(0x45, 0x20);
dl1a_write_register(0x47, 0x08);
dl1a_write_register(0x48, 0x28);
dl1a_write_register(0x67, 0x00);
dl1a_write_register(0x70, 0x04);
dl1a_write_register(0x71, 0x01);
dl1a_write_register(0x72, 0xFE);
dl1a_write_register(0x76, 0x00);
dl1a_write_register(0x77, 0x00);
dl1a_write_register(0xFF, 0x01);
dl1a_write_register(0x0D, 0x01);
dl1a_write_register(0xFF, 0x00);
dl1a_write_register(0x80, 0x01);
dl1a_write_register(0x01, 0xF8);
dl1a_write_register(0xFF, 0x01);
dl1a_write_register(0x8E, 0x01);
dl1a_write_register(0x00, 0x01);
dl1a_write_register(0xFF, 0x00);
dl1a_write_register(0x80, 0x00);
// <20><><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>Ʒ<EFBFBD><C6B7><EFBFBD><EFBFBD>
dl1a_write_register(DL1A_SYSTEM_INTERRUPT_GPIO_CONFIG, 0x04);
reg_data_buffer = dl1a_read_register(DL1A_GPIO_HV_MUX_ACTIVE_HIGH);
dl1a_write_register(DL1A_GPIO_HV_MUX_ACTIVE_HIGH, reg_data_buffer & ~0x10);
dl1a_write_register(DL1A_SYSTEM_INTERRUPT_CLEAR, 0x01);
measurement_timing_budget_us = dl1a_get_measurement_timing_budget();
// Ĭ<><C4AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>½<EFBFBD><C2BD><EFBFBD> MSRC <20><> TCC
// MSRC = Minimum Signal Rate Check
// TCC = Target CentreCheck
dl1a_write_register(DL1A_SYSTEM_SEQUENCE_CONFIG, 0xE8);
dl1a_set_measurement_timing_budget(measurement_timing_budget_us); // <20><><EFBFBD>¼<EFBFBD><C2BC><EFBFBD>ʱ<EFBFBD><CAB1>Ԥ<EFBFBD><D4A4>
// -------------------------------- DL1A <20><><EFBFBD>ó<EFBFBD>ʼ<EFBFBD><CABC> --------------------------------
dl1a_write_register(DL1A_SYSTEM_SEQUENCE_CONFIG, 0x01);
if (dl1a_perform_single_ref_calibration(0x40))
{
return_state = 1;
zf_log(0, "DL1A perform single reference calibration error.");
break;
}
dl1a_write_register(DL1A_SYSTEM_SEQUENCE_CONFIG, 0x02);
if (dl1a_perform_single_ref_calibration(0x00))
{
return_state = 1;
zf_log(0, "DL1A perform single reference calibration error.");
break;
}
dl1a_write_register(DL1A_SYSTEM_SEQUENCE_CONFIG, 0xE8); // <20>ָ<EFBFBD><D6B8><EFBFBD>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
system_delay_ms(100);
dl1a_write_register(0x80, 0x01);
dl1a_write_register(0xFF, 0x01);
dl1a_write_register(0x00, 0x00);
dl1a_write_register(0x91, stop_variable);
dl1a_write_register(0x00, 0x01);
dl1a_write_register(0xFF, 0x00);
dl1a_write_register(0x80, 0x00);
dl1a_write_register(DL1A_SYSRANGE_START, 0x02);
}while(0);
return return_state;
}

199
Example/E03_adc_demo/libraries/zf_device/zf_device_dl1a.h Normal file
View File

@@ -0,0 +1,199 @@
/*********************************************************************************************************************
* TC264 Opensourec Library <20><><EFBFBD><EFBFBD>TC264 <20><>Դ<EFBFBD>⣩<EFBFBD><E2A3A9>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>ڹٷ<DAB9> SDK <20>ӿڵĵ<DAB5><C4B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>
* Copyright (c) 2022 SEEKFREE <20><><EFBFBD>ɿƼ<C9BF>
*
* <20><><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD> TC264 <20><>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>
*
* TC264 <20><>Դ<EFBFBD><D4B4> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <20><><EFBFBD><EFBFBD><EFBFBD>Ը<EFBFBD><D4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ᷢ<EFBFBD><E1B7A2><EFBFBD><EFBFBD> GPL<50><4C>GNU General Public License<73><65><EFBFBD><EFBFBD> GNUͨ<55>ù<EFBFBD><C3B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>֤<EFBFBD><D6A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* <20><> GPL <20>ĵ<EFBFBD>3<EFBFBD>棨<EFBFBD><E6A3A8> GPL3.0<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><EFBFBD>κκ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>İ汾<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<2F><><EFBFBD>޸<EFBFBD><DEB8><EFBFBD>
*
* <20><><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD>ķ<EFBFBD><C4B7><EFBFBD><EFBFBD><EFBFBD>ϣ<EFBFBD><CFA3><EFBFBD><EFBFBD><EFBFBD>ܷ<EFBFBD><DCB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3><EFBFBD><EFBFBD><EFBFBD>δ<EFBFBD><CEB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>κεı<CEB5>֤
* <20><><EFBFBD><EFBFBD>û<EFBFBD><C3BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ի<EFBFBD><D4BB>ʺ<EFBFBD><CABA>ض<EFBFBD><D8B6><EFBFBD>;<EFBFBD>ı<EFBFBD>֤
* <20><><EFBFBD><EFBFBD>ϸ<EFBFBD><CFB8><EFBFBD><EFBFBD><EFBFBD>μ<EFBFBD> GPL
*
* <20><>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD><EFBFBD>յ<EFBFBD><D5B5><EFBFBD><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>ͬʱ<CDAC>յ<EFBFBD>һ<EFBFBD><D2BB> GPL <20>ĸ<EFBFBD><C4B8><EFBFBD>
* <20><><EFBFBD><EFBFBD>û<EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><https://www.gnu.org/licenses/>
*
* <20><><EFBFBD><EFBFBD>ע<EFBFBD><D7A2><EFBFBD><EFBFBD>
* <20><><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>ʹ<EFBFBD><CAB9> GPL3.0 <20><>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD>֤Э<D6A4><D0AD> <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD>İ汾
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ӣ<EFBFBD>İ<EFBFBD><C4B0><EFBFBD> libraries/doc <20>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD>µ<EFBFBD> GPL3_permission_statement.txt <20>ļ<EFBFBD><C4BC><EFBFBD>
* <20><><EFBFBD><EFBFBD>֤<EFBFBD><D6A4><EFBFBD><EFBFBD><EFBFBD><EFBFBD> libraries <20>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD>µ<EFBFBD> LICENSE <20>ļ<EFBFBD>
* <20><>ӭ<EFBFBD><D3AD>λʹ<CEBB>ò<EFBFBD><C3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><><EFBFBD>޸<EFBFBD><DEB8><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>뱣<EFBFBD><EBB1A3><EFBFBD><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC>İ<EFBFBD>Ȩ<EFBFBD><C8A8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
*
* <20>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD> zf_device_dl1a
* <20><>˾<EFBFBD><CBBE><EFBFBD><EFBFBD> <20>ɶ<EFBFBD><C9B6><EFBFBD><EFBFBD>ɿƼ<C9BF><C6BC><EFBFBD><EFBFBD>޹<EFBFBD>˾
* <20>汾<EFBFBD><E6B1BE>Ϣ <20>鿴 libraries/doc <20>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD> version <20>ļ<EFBFBD> <20>汾˵<E6B1BE><CBB5>
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ADS v1.8.0
* <20><><EFBFBD><EFBFBD>ƽ̨ TC264D
* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> https://seekfree.taobao.com/
*
* <20>޸ļ<DEB8>¼
* <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> <20><>ע
* 2022-09-15 pudding first version
********************************************************************************************************************/
/*********************************************************************************************************************
* <20><><EFBFBD>߶<EFBFBD><DFB6>壺
* ------------------------------------
* ģ<><C4A3><EFBFBD>ܽ<EFBFBD> <20><>Ƭ<EFBFBD><C6AC><EFBFBD>ܽ<EFBFBD>
* SCL <20>鿴 zf_device_dl1a.h <20><> DL1A_SCL_PIN <20>궨<EFBFBD><EAB6A8>
* SDA <20>鿴 zf_device_dl1a.h <20><> DL1A_SDA_PIN <20>궨<EFBFBD><EAB6A8>
* VCC 5V <20><>Դ
* GND <20><>Դ<EFBFBD><D4B4>
* ------------------------------------
* ------------------------------------
********************************************************************************************************************/
#ifndef _ZF_DEVICE_DL1A_H_
#define _ZF_DEVICE_DL1A_H_
#include "zf_common_typedef.h"
// <20><>Ҫע<D2AA><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD> DL1A <20><><EFBFBD><EFBFBD>֧<EFBFBD><D6A7> 400KHz <20><> IIC ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <20><>Ҫע<D2AA><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD> DL1A <20><><EFBFBD><EFBFBD>֧<EFBFBD><D6A7> 400KHz <20><> IIC ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <20><>Ҫע<D2AA><D7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD> DL1A <20><><EFBFBD><EFBFBD>֧<EFBFBD><D6A7> 400KHz <20><> IIC ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define DL1A_USE_SOFT_IIC (1) // Ĭ<><C4AC>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD> IIC <20><>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9><EFBFBD><EFBFBD><EFBFBD><EFBFBD> IIC <20><>ʽ
#if DL1A_USE_SOFT_IIC // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20><>ɫ<EFBFBD><C9AB><EFBFBD><EFBFBD><EFBFBD>IJ<EFBFBD><C4B2><EFBFBD><EFBFBD><EFBFBD>ȷ<EFBFBD><C8B7> <20><>ɫ<EFBFBD>ҵľ<D2B5><C4BE><EFBFBD>û<EFBFBD><C3BB><EFBFBD>õ<EFBFBD>
//====================================================<3D><><EFBFBD><EFBFBD> IIC <20><><EFBFBD><EFBFBD>====================================================
#define DL1A_SOFT_IIC_DELAY (100) // <20><><EFBFBD><EFBFBD> IIC <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD> <20><>ֵԽС IIC ͨ<><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Խ<EFBFBD><D4BD>
#define DL1A_SCL_PIN (P33_4) // <20><><EFBFBD><EFBFBD> IIC SCL <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> VL53L0X <20><> SCL <20><><EFBFBD><EFBFBD>
#define DL1A_SDA_PIN (P33_5) // <20><><EFBFBD><EFBFBD> IIC SDA <20><><EFBFBD><EFBFBD> <20><><EFBFBD><EFBFBD> VL53L0X <20><> SDA <20><><EFBFBD><EFBFBD>
//====================================================<3D><><EFBFBD><EFBFBD> IIC <20><><EFBFBD><EFBFBD>====================================================
#else
#error "<22>ݲ<EFBFBD>֧<EFBFBD><D6A7>Ӳ<EFBFBD><D3B2>IICͨѶ"
#endif
#define DL1A_XSHUT_PIN (P20_10)
#define DL1A_TIMEOUT_COUNT (0x00FF) // VL53L0X <20><>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
//================================================<3D><><EFBFBD><EFBFBD> DL1A <20>ڲ<EFBFBD><DAB2><EFBFBD>ַ================================================
#define DL1A_DEV_ADDR (0x52 >> 1) // 0b0101001
#define DL1A_SYSRANGE_START (0x00)
#define DL1A_SYSTEM_SEQUENCE_CONFIG (0x01)
#define DL1A_SYSTEM_INTERMEASUREMENT_PERIOD (0x04)
#define DL1A_SYSTEM_RANGE_CONFIG (0x09)
#define DL1A_SYSTEM_INTERRUPT_GPIO_CONFIG (0x0A)
#define DL1A_SYSTEM_INTERRUPT_CLEAR (0x0B)
#define DL1A_SYSTEM_THRESH_HIGH (0x0C)
#define DL1A_SYSTEM_THRESH_LOW (0x0E)
#define DL1A_SYSTEM_HISTOGRAM_BIN (0x81)
#define DL1A_RESULT_INTERRUPT_STATUS (0x13)
#define DL1A_RESULT_RANGE_STATUS (0x14)
#define DL1A_RESULT_PEAK_SIGNAL_RATE_REF (0xB6)
#define DL1A_RESULT_CORE_AMBIENT_WINDOW_EVENTS_RTN (0xBC)
#define DL1A_RESULT_CORE_RANGING_TOTAL_EVENTS_RTN (0xC0)
#define DL1A_RESULT_CORE_AMBIENT_WINDOW_EVENTS_REF (0xD0)
#define DL1A_RESULT_CORE_RANGING_TOTAL_EVENTS_REF (0xD4)
#define DL1A_PRE_RANGE_CONFIG_MIN_SNR (0x27)
#define DL1A_PRE_RANGE_CONFIG_VCSEL_PERIOD (0x50)
#define DL1A_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI (0x51)
#define DL1A_PRE_RANGE_CONFIG_TIMEOUT_MACROP_LO (0x52)
#define DL1A_PRE_RANGE_CONFIG_VALID_PHASE_LOW (0x56)
#define DL1A_PRE_RANGE_CONFIG_VALID_PHASE_HIGH (0x57)
#define DL1A_PRE_RANGE_CONFIG_SIGMA_THRESH_HI (0x61)
#define DL1A_PRE_RANGE_CONFIG_SIGMA_THRESH_LO (0x62)
#define DL1A_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT (0x64)
#define DL1A_FINAL_RANGE_CONFIG_VALID_PHASE_LOW (0x47)
#define DL1A_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH (0x48)
#define DL1A_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT (0x44)
#define DL1A_FINAL_RANGE_CONFIG_MIN_SNR (0x67)
#define DL1A_FINAL_RANGE_CONFIG_VCSEL_PERIOD (0x70)
#define DL1A_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI (0x71)
#define DL1A_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_LO (0x72)
#define DL1A_GLOBAL_CONFIG_VCSEL_WIDTH (0x32)
#define DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_0 (0xB0)
#define DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_1 (0xB1)
#define DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_2 (0xB2)
#define DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_3 (0xB3)
#define DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_4 (0xB4)
#define DL1A_GLOBAL_CONFIG_SPAD_ENABLES_REF_5 (0xB5)
#define DL1A_GLOBAL_CONFIG_REF_EN_START_SELECT (0xB6)
#define DL1A_ALGO_PART_TO_PART_RANGE_OFFSET_MM (0x28)
#define DL1A_ALGO_PHASECAL_LIM (0x30)
#define DL1A_ALGO_PHASECAL_CONFIG_TIMEOUT (0x30)
#define DL1A_HISTOGRAM_CONFIG_INITIAL_PHASE_SELECT (0x33)
#define DL1A_HISTOGRAM_CONFIG_READOUT_CTRL (0x55)
#define DL1A_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD (0x4E)
#define DL1A_DYNAMIC_SPAD_REF_EN_START_OFFSET (0x4F)
#define DL1A_MSRC_CONFIG_TIMEOUT_MACROP (0x46)
#define DL1A_MSRC_CONFIG (0x60)
#define DL1A_IDENTIFICATION_MODEL_ID (0xC0)
#define DL1A_IDENTIFICATION_REVISION_ID (0xC2)
#define DL1A_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS (0x20)
#define DL1A_POWER_MANAGEMENT_GO1_POWER_FORCE (0x80)
#define DL1A_GPIO_HV_MUX_ACTIVE_HIGH (0x84)
#define DL1A_I2C_SLAVE_DEVICE_ADDRESS (0x8A)
#define DL1A_SOFT_RESET_GO2_SOFT_RESET_N (0xBF)
#define DL1A_OSC_CALIBRATE_VAL (0xF8)
#define DL1A_IO_VOLTAGE_CONFIG (0x89) // IO <20><>ѹ<EFBFBD><D1B9><EFBFBD>üĴ<C3BC><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ Ĭ<><C4AC> 1V8 ʹ<><CAB9><EFBFBD>޸<EFBFBD>Ϊ 2V8
//================================================<3D><><EFBFBD><EFBFBD> DL1A <20>ڲ<EFBFBD><DAB2><EFBFBD>ַ================================================
#define DL1A_MIN_TIMING_BUDGET (20000)
#define DL1A_GET_START_OVERHEAD (1910)
#define DL1A_SET_START_OVERHEAD (1320)
#define DL1A_END_OVERHEAD (960 )
#define DL1A_TCC_OVERHEAD (590 )
#define DL1A_DSS_OVERHEAD (690 )
#define DL1A_MSRC_OVERHEAD (660 )
#define DL1A_PRERANGE_OVERHEAD (660 )
#define DL1A_FINALlRANGE_OVERHEAD (550 )
typedef enum
{
DL1A_VCSEL_PERIOD_PER_RANGE,
DL1A_VCSEL_PERIOD_FINAL_RANGE,
}dl1a_vcsel_period_type_enum;
typedef struct
{
uint8 tcc;
uint8 msrc;
uint8 dss;
uint8 pre_range;
uint8 final_range;
}dl1a_sequence_enables_step_struct;
typedef struct
{
uint16 pre_range_vcsel_period_pclks;
uint16 final_range_vcsel_period_pclks;
uint16 msrc_dss_tcc_mclks;
uint16 pre_range_mclks;
uint16 final_range_mclks;
uint32 msrc_dss_tcc_us;
uint32 pre_range_us;
uint32 final_range_us;
}dl1a_sequence_timeout_step_struct;
extern uint8 dl1a_finsh_flag;
extern uint16 dl1a_distance_mm;
void dl1a_get_distance (void);
uint8 dl1a_init (void);
#endif